[deliverable/linux.git] / arch / ia64 / sn / kernel / irq.c

/*
 * Platform dependent support for SGI SN
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
 */

#include <linux/irq.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/shub_mmr.h>
#include <asm/sn/sn_sal.h>

static void force_interrupt(int irq);
static void register_intr_pda(struct sn_irq_info *sn_irq_info);
static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);

int sn_force_interrupt_flag = 1;
extern int sn_ioif_inited;
struct list_head **sn_irq_lh;
static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */

u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
				     struct sn_irq_info *sn_irq_info,
				     int req_irq, nasid_t req_nasid,
				     int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
			(u64) req_nasid, (u64) req_slice);

	return ret_stuff.status;
}

void sn_intr_free(nasid_t local_nasid, int local_widget,
				struct sn_irq_info *sn_irq_info)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_FREE, (u64) local_nasid,
			(u64) local_widget, (u64) sn_irq_info->irq_irq,
			(u64) sn_irq_info->irq_cookie, 0, 0);
}

u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
		      struct sn_irq_info *sn_irq_info,
		      nasid_t req_nasid, int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
			(u64) local_widget, __pa(sn_irq_info),
			(u64) req_nasid, (u64) req_slice, 0);

	return ret_stuff.status;
}

static unsigned int sn_startup_irq(unsigned int irq)
{
	return 0;
}

static void sn_shutdown_irq(unsigned int irq)
{
}

static void sn_disable_irq(unsigned int irq)
{
}

static void sn_enable_irq(unsigned int irq)
{
}

static void sn_ack_irq(unsigned int irq)
{
	u64 event_occurred, mask;

	irq = irq & 0xff;
	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
	mask = event_occurred & SH_ALL_INT_MASK;
	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);

	move_native_irq(irq);
}

static void sn_end_irq(unsigned int irq)
{
	int ivec;
	u64 event_occurred;

	ivec = irq & 0xff;
	if (ivec == SGI_UART_VECTOR) {
		event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
		/* If the UART bit is set here, we may have received an
		 * interrupt from the UART that the driver missed.  To
		 * make sure, we IPI ourselves to force us to look again.
		 */
		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
			platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
					  IA64_IPI_DM_INT, 0);
		}
	}
	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	if (sn_force_interrupt_flag)
		force_interrupt(irq);
}

static void sn_irq_info_free(struct rcu_head *head);

struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
				       nasid_t nasid, int slice)
{
	int vector;
	int cpuid;
#ifdef CONFIG_SMP
	int cpuphys;
#endif
	int64_t bridge;
	int local_widget, status;
	nasid_t local_nasid;
	struct sn_irq_info *new_irq_info;
	struct sn_pcibus_provider *pci_provider;

	bridge = (u64) sn_irq_info->irq_bridge;
	if (!bridge) {
		return NULL; /* irq is not a device interrupt */
	}

	local_nasid = NASID_GET(bridge);

	if (local_nasid & 1)
		local_widget = TIO_SWIN_WIDGETNUM(bridge);
	else
		local_widget = SWIN_WIDGETNUM(bridge);
	vector = sn_irq_info->irq_irq;

	/* Make use of SAL_INTR_REDIRECT if PROM supports it */
	status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
	if (!status) {
		new_irq_info = sn_irq_info;
		goto finish_up;
	}

	/*
	 * PROM does not support SAL_INTR_REDIRECT, or it failed.
	 * Revert to old method.
	 */
	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
	if (new_irq_info == NULL)
		return NULL;

	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));

	/* Free the old PROM new_irq_info structure */
	sn_intr_free(local_nasid, local_widget, new_irq_info);
	unregister_intr_pda(new_irq_info);

	/* allocate a new PROM new_irq_info struct */
	status = sn_intr_alloc(local_nasid, local_widget,
			       new_irq_info, vector,
			       nasid, slice);

	/* SAL call failed */
	if (status) {
		kfree(new_irq_info);
		return NULL;
	}

	register_intr_pda(new_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);


finish_up:
	/* Update kernels new_irq_info with new target info */
	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
				     new_irq_info->irq_slice);
	new_irq_info->irq_cpuid = cpuid;

	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];

	/*
	 * If this represents a line interrupt, target it.  If it's
	 * an msi (irq_int_bit < 0), it's already targeted.
	 */
	if (new_irq_info->irq_int_bit >= 0 &&
	    pci_provider && pci_provider->target_interrupt)
		(pci_provider->target_interrupt)(new_irq_info);

#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpuid);
	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
#endif

	return new_irq_info;
}

static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
{
	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
	nasid_t nasid;
	int slice;

	nasid = cpuid_to_nasid(first_cpu(mask));
	slice = cpuid_to_slice(first_cpu(mask));

	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
				 sn_irq_lh[irq], list)
		(void)sn_retarget_vector(sn_irq_info, nasid, slice);
}

static void
sn_mask_irq(unsigned int irq)
{
}

static void
sn_unmask_irq(unsigned int irq)
{
}

struct irq_chip irq_type_sn = {
	.name		= "SN hub",
	.startup	= sn_startup_irq,
	.shutdown	= sn_shutdown_irq,
	.enable		= sn_enable_irq,
	.disable	= sn_disable_irq,
	.ack		= sn_ack_irq,
	.end		= sn_end_irq,
	.mask		= sn_mask_irq,
	.unmask		= sn_unmask_irq,
	.set_affinity	= sn_set_affinity_irq
};

ia64_vector sn_irq_to_vector(int irq)
{
	if (irq >= IA64_NUM_VECTORS)
		return 0;
	return (ia64_vector)irq;
}

unsigned int sn_local_vector_to_irq(u8 vector)
{
	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
}

void sn_irq_init(void)
{
	int i;
	irq_desc_t *base_desc = irq_desc;

	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;

	for (i = 0; i < NR_IRQS; i++) {
		if (base_desc[i].chip == &no_irq_type) {
			base_desc[i].chip = &irq_type_sn;
		}
	}
}

static void register_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;

	if (pdacpu(cpu)->sn_last_irq < irq) {
		pdacpu(cpu)->sn_last_irq = irq;
	}

	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
		pdacpu(cpu)->sn_first_irq = irq;
}

static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;
	struct sn_irq_info *tmp_irq_info;
	int i, foundmatch;

	rcu_read_lock();
	if (pdacpu(cpu)->sn_last_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_last_irq - 1;
		     i && !foundmatch; i--) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_last_irq = i;
	}

	if (pdacpu(cpu)->sn_first_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_first_irq + 1;
		     i < NR_IRQS && !foundmatch; i++) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	}
	rcu_read_unlock();
}

static void sn_irq_info_free(struct rcu_head *head)
{
	struct sn_irq_info *sn_irq_info;

	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
	kfree(sn_irq_info);
}

void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
{
	nasid_t nasid = sn_irq_info->irq_nasid;
	int slice = sn_irq_info->irq_slice;
	int cpu = nasid_slice_to_cpuid(nasid, slice);
#ifdef CONFIG_SMP
	int cpuphys;
#endif

	pci_dev_get(pci_dev);
	sn_irq_info->irq_cpuid = cpu;
	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);

	/* link it into the sn_irq[irq] list */
	spin_lock(&sn_irq_info_lock);
	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
	reserve_irq_vector(sn_irq_info->irq_irq);
	spin_unlock(&sn_irq_info_lock);

	register_intr_pda(sn_irq_info);
#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpu);
	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
#endif
}

void sn_irq_unfixup(struct pci_dev *pci_dev)
{
	struct sn_irq_info *sn_irq_info;

	/* Only cleanup IRQ stuff if this device has a host bus context */
	if (!SN_PCIDEV_BUSSOFT(pci_dev))
		return;

	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
	if (!sn_irq_info)
		return;
	if (!sn_irq_info->irq_irq) {
		kfree(sn_irq_info);
		return;
	}

	unregister_intr_pda(sn_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_del_rcu(&sn_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
		free_irq_vector(sn_irq_info->irq_irq);
	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
	pci_dev_put(pci_dev);

}

static inline void
sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
{
	struct sn_pcibus_provider *pci_provider;

	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	if (pci_provider && pci_provider->force_interrupt)
		(*pci_provider->force_interrupt)(sn_irq_info);
}

static void force_interrupt(int irq)
{
	struct sn_irq_info *sn_irq_info;

	if (!sn_ioif_inited)
		return;

	rcu_read_lock();
	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
		sn_call_force_intr_provider(sn_irq_info);

	rcu_read_unlock();
}

/*
 * Check for lost interrupts.  If the PIC int_status reg. says that
 * an interrupt has been sent, but not handled, and the interrupt
 * is not pending in either the cpu irr regs or in the soft irr regs,
 * and the interrupt is not in service, then the interrupt may have
 * been lost.  Force an interrupt on that pin.  It is possible that
 * the interrupt is in flight, so we may generate a spurious interrupt,
 * but we should never miss a real lost interrupt.
 */
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
{
	u64 regval;
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;

	/*
	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
	 * since they do not target Shub II interrupt registers.  If that
	 * ever changes, this check needs to accomodate.
	 */
	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (!pcidev_info)
		return;

	pcibus_info =
	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	    pdi_pcibus_info;
	regval = pcireg_intr_status_get(pcibus_info);

	if (!ia64_get_irr(irq_to_vector(irq))) {
		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
			regval &= 0xff;
			if (sn_irq_info->irq_int_bit & regval &
			    sn_irq_info->irq_last_intr) {
				regval &= ~(sn_irq_info->irq_int_bit & regval);
				sn_call_force_intr_provider(sn_irq_info);
			}
		}
	}
	sn_irq_info->irq_last_intr = regval;
}

void sn_lb_int_war_check(void)
{
	struct sn_irq_info *sn_irq_info;
	int i;

	if (!sn_ioif_inited || pda->sn_first_irq == 0)
		return;

	rcu_read_lock();
	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
			sn_check_intr(i, sn_irq_info);
		}
	}
	rcu_read_unlock();
}

void __init sn_irq_lh_init(void)
{
	int i;

	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
	if (!sn_irq_lh)
		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");

	for (i = 0; i < NR_IRQS; i++) {
		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
		if (!sn_irq_lh[i])
			panic("SN PCI INIT: Failed IRQ memory allocation\n");

		INIT_LIST_HEAD(sn_irq_lh[i]);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Platform dependent support for SGI SN
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
2fcc3db0	8	* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
1da177e4 LT	9	*/
	10
	11	#include <linux/irq.h>
cb4cb2cb	12	#include <linux/spinlock.h>
2fcc3db0	13	#include <linux/init.h>
1da177e4 LT	14	#include <asm/sn/addrs.h>
1da177e4 LT	15	#include <asm/sn/arch.h>
c13cf371 PB	16	#include <asm/sn/intr.h>
c13cf371 PB	17	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	18	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	19	#include <asm/sn/pcidev.h>
1da177e4 LT	20	#include <asm/sn/shub_mmr.h>
	21	#include <asm/sn/sn_sal.h>
	22
	23	static void force_interrupt(int irq);
	24	static void register_intr_pda(struct sn_irq_info *sn_irq_info);
	25	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
	26
d0d59b98	27	int sn_force_interrupt_flag = 1;
1da177e4	28	extern int sn_ioif_inited;
83821d3f	29	struct list_head **sn_irq_lh;
34af946a	30	static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
1da177e4	31
83821d3f MM	32	u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
83821d3f MM	33	struct sn_irq_info *sn_irq_info,
1da177e4 LT	34	int req_irq, nasid_t req_nasid,
	35	int req_slice)
	36	{
	37	struct ia64_sal_retval ret_stuff;
	38	ret_stuff.status = 0;
	39	ret_stuff.v0 = 0;
	40
	41	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	42	(u64) SAL_INTR_ALLOC, (u64) local_nasid,
83821d3f	43	(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
1da177e4	44	(u64) req_nasid, (u64) req_slice);
83821d3f	45
1da177e4 LT	46	return ret_stuff.status;
	47	}
	48
83821d3f	49	void sn_intr_free(nasid_t local_nasid, int local_widget,
1da177e4 LT	50	struct sn_irq_info *sn_irq_info)
	51	{
	52	struct ia64_sal_retval ret_stuff;
	53	ret_stuff.status = 0;
	54	ret_stuff.v0 = 0;
	55
	56	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	57	(u64) SAL_INTR_FREE, (u64) local_nasid,
	58	(u64) local_widget, (u64) sn_irq_info->irq_irq,
	59	(u64) sn_irq_info->irq_cookie, 0, 0);
	60	}
	61
0e17b560 JK	62	u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
	63	struct sn_irq_info *sn_irq_info,
	64	nasid_t req_nasid, int req_slice)
	65	{
	66	struct ia64_sal_retval ret_stuff;
	67	ret_stuff.status = 0;
	68	ret_stuff.v0 = 0;
	69
	70	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	71	(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
	72	(u64) local_widget, __pa(sn_irq_info),
	73	(u64) req_nasid, (u64) req_slice, 0);
	74
	75	return ret_stuff.status;
	76	}
	77
1da177e4 LT	78	static unsigned int sn_startup_irq(unsigned int irq)
	79	{
	80	return 0;
	81	}
	82
	83	static void sn_shutdown_irq(unsigned int irq)
	84	{
	85	}
	86
	87	static void sn_disable_irq(unsigned int irq)
	88	{
	89	}
	90
	91	static void sn_enable_irq(unsigned int irq)
	92	{
	93	}
	94
	95	static void sn_ack_irq(unsigned int irq)
	96	{
2fcc3db0	97	u64 event_occurred, mask;
1da177e4 LT	98
1da177e4 LT	99	irq = irq & 0xff;
2fcc3db0	100	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
be539c73	101	mask = event_occurred & SH_ALL_INT_MASK;
2fcc3db0	102	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
1da177e4 LT	103	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
1da177e4 LT	104
689388bb	105	move_native_irq(irq);
1da177e4 LT	106	}
	107
	108	static void sn_end_irq(unsigned int irq)
	109	{
1da177e4	110	int ivec;
0aa2c72e	111	u64 event_occurred;
1da177e4 LT	112
	113	ivec = irq & 0xff;
	114	if (ivec == SGI_UART_VECTOR) {
0aa2c72e	115	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
cb4cb2cb	116	/* If the UART bit is set here, we may have received an
1da177e4 LT	117	* interrupt from the UART that the driver missed. To
	118	* make sure, we IPI ourselves to force us to look again.
	119	*/
	120	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
	121	platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
	122	IA64_IPI_DM_INT, 0);
	123	}
	124	}
	125	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	126	if (sn_force_interrupt_flag)
	127	force_interrupt(irq);
	128	}
	129
cb4cb2cb PB	130	static void sn_irq_info_free(struct rcu_head *head);
cb4cb2cb PB	131
83821d3f MM	132	struct sn_irq_info sn_retarget_vector(struct sn_irq_info sn_irq_info,
83821d3f MM	133	nasid_t nasid, int slice)
1da177e4	134	{
83821d3f	135	int vector;
c6957771 JK	136	int cpuid;
c6957771 JK	137	#ifdef CONFIG_SMP
83821d3f	138	int cpuphys;
c6957771	139	#endif
83821d3f MM	140	int64_t bridge;
	141	int local_widget, status;
	142	nasid_t local_nasid;
	143	struct sn_irq_info *new_irq_info;
	144	struct sn_pcibus_provider *pci_provider;
	145
0e17b560	146	bridge = (u64) sn_irq_info->irq_bridge;
83821d3f	147	if (!bridge) {
83821d3f MM	148	return NULL; /* irq is not a device interrupt */
83821d3f MM	149	}
1da177e4	150
83821d3f	151	local_nasid = NASID_GET(bridge);
1da177e4	152
83821d3f MM	153	if (local_nasid & 1)
	154	local_widget = TIO_SWIN_WIDGETNUM(bridge);
	155	else
	156	local_widget = SWIN_WIDGETNUM(bridge);
83821d3f	157	vector = sn_irq_info->irq_irq;
0e17b560 JK	158
	159	/* Make use of SAL_INTR_REDIRECT if PROM supports it */
	160	status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
	161	if (!status) {
	162	new_irq_info = sn_irq_info;
	163	goto finish_up;
	164	}
	165
	166	/*
	167	* PROM does not support SAL_INTR_REDIRECT, or it failed.
	168	* Revert to old method.
	169	*/
	170	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
	171	if (new_irq_info == NULL)
	172	return NULL;
	173
	174	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
	175
83821d3f MM	176	/* Free the old PROM new_irq_info structure */
83821d3f MM	177	sn_intr_free(local_nasid, local_widget, new_irq_info);
83821d3f	178	unregister_intr_pda(new_irq_info);
1da177e4	179
83821d3f MM	180	/* allocate a new PROM new_irq_info struct */
	181	status = sn_intr_alloc(local_nasid, local_widget,
	182	new_irq_info, vector,
	183	nasid, slice);
1da177e4	184
83821d3f MM	185	/* SAL call failed */
	186	if (status) {
	187	kfree(new_irq_info);
	188	return NULL;
	189	}
cb4cb2cb	190
0e17b560 JK	191	register_intr_pda(new_irq_info);
	192	spin_lock(&sn_irq_info_lock);
	193	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	194	spin_unlock(&sn_irq_info_lock);
	195	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
	196
	197
	198	finish_up:
c6957771 JK	199	/* Update kernels new_irq_info with new target info */
	200	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
	201	new_irq_info->irq_slice);
	202	new_irq_info->irq_cpuid = cpuid;
1da177e4	203
83821d3f	204	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
cb4cb2cb	205
83821d3f MM	206	/*
	207	* If this represents a line interrupt, target it. If it's
	208	* an msi (irq_int_bit < 0), it's already targeted.
	209	*/
	210	if (new_irq_info->irq_int_bit >= 0 &&
	211	pci_provider && pci_provider->target_interrupt)
	212	(pci_provider->target_interrupt)(new_irq_info);
cb4cb2cb	213
1da177e4	214	#ifdef CONFIG_SMP
c6957771	215	cpuphys = cpu_physical_id(cpuid);
83821d3f	216	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
1da177e4	217	#endif
83821d3f MM	218
	219	return new_irq_info;
	220	}
	221
	222	static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
	223	{
	224	struct sn_irq_info sn_irq_info, sn_irq_info_safe;
	225	nasid_t nasid;
	226	int slice;
	227
	228	nasid = cpuid_to_nasid(first_cpu(mask));
	229	slice = cpuid_to_slice(first_cpu(mask));
	230
	231	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
	232	sn_irq_lh[irq], list)
	233	(void)sn_retarget_vector(sn_irq_info, nasid, slice);
1da177e4 LT	234	}
1da177e4 LT	235
e253eb0c KH	236	static void
	237	sn_mask_irq(unsigned int irq)
	238	{
	239	}
	240
	241	static void
	242	sn_unmask_irq(unsigned int irq)
	243	{
	244	}
	245
	246	struct irq_chip irq_type_sn = {
06344db3	247	.name = "SN hub",
cb4cb2cb PB	248	.startup = sn_startup_irq,
	249	.shutdown = sn_shutdown_irq,
	250	.enable = sn_enable_irq,
	251	.disable = sn_disable_irq,
	252	.ack = sn_ack_irq,
	253	.end = sn_end_irq,
e253eb0c KH	254	.mask = sn_mask_irq,
e253eb0c KH	255	.unmask = sn_unmask_irq,
cb4cb2cb	256	.set_affinity = sn_set_affinity_irq
1da177e4 LT	257	};
1da177e4 LT	258
1115200a KK	259	ia64_vector sn_irq_to_vector(int irq)
	260	{
	261	if (irq >= IA64_NUM_VECTORS)
	262	return 0;
	263	return (ia64_vector)irq;
	264	}
	265
1da177e4 LT	266	unsigned int sn_local_vector_to_irq(u8 vector)
	267	{
	268	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
	269	}
	270
	271	void sn_irq_init(void)
	272	{
	273	int i;
	274	irq_desc_t *base_desc = irq_desc;
	275
10083072 MM	276	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	277	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
	278
1da177e4	279	for (i = 0; i < NR_IRQS; i++) {
d1bef4ed IM	280	if (base_desc[i].chip == &no_irq_type) {
d1bef4ed IM	281	base_desc[i].chip = &irq_type_sn;
1da177e4 LT	282	}
	283	}
	284	}
	285
	286	static void register_intr_pda(struct sn_irq_info *sn_irq_info)
	287	{
	288	int irq = sn_irq_info->irq_irq;
	289	int cpu = sn_irq_info->irq_cpuid;
	290
	291	if (pdacpu(cpu)->sn_last_irq < irq) {
	292	pdacpu(cpu)->sn_last_irq = irq;
	293	}
	294
2fcc3db0	295	if (pdacpu(cpu)->sn_first_irq == 0 \|\| pdacpu(cpu)->sn_first_irq > irq)
1da177e4	296	pdacpu(cpu)->sn_first_irq = irq;
1da177e4 LT	297	}
	298
	299	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
	300	{
	301	int irq = sn_irq_info->irq_irq;
	302	int cpu = sn_irq_info->irq_cpuid;
	303	struct sn_irq_info *tmp_irq_info;
	304	int i, foundmatch;
	305
cb4cb2cb	306	rcu_read_lock();
1da177e4 LT	307	if (pdacpu(cpu)->sn_last_irq == irq) {
1da177e4 LT	308	foundmatch = 0;
cb4cb2cb PB	309	for (i = pdacpu(cpu)->sn_last_irq - 1;
	310	i && !foundmatch; i--) {
	311	list_for_each_entry_rcu(tmp_irq_info,
	312	sn_irq_lh[i],
	313	list) {
1da177e4	314	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	315	foundmatch = 1;
1da177e4 LT	316	break;
1da177e4 LT	317	}
1da177e4 LT	318	}
	319	}
	320	pdacpu(cpu)->sn_last_irq = i;
	321	}
	322
	323	if (pdacpu(cpu)->sn_first_irq == irq) {
	324	foundmatch = 0;
cb4cb2cb PB	325	for (i = pdacpu(cpu)->sn_first_irq + 1;
	326	i < NR_IRQS && !foundmatch; i++) {
	327	list_for_each_entry_rcu(tmp_irq_info,
	328	sn_irq_lh[i],
	329	list) {
1da177e4	330	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	331	foundmatch = 1;
1da177e4 LT	332	break;
1da177e4 LT	333	}
1da177e4 LT	334	}
	335	}
	336	pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	337	}
cb4cb2cb	338	rcu_read_unlock();
1da177e4 LT	339	}
1da177e4 LT	340
cb4cb2cb	341	static void sn_irq_info_free(struct rcu_head *head)
1da177e4 LT	342	{
1da177e4 LT	343	struct sn_irq_info *sn_irq_info;
1da177e4	344
cb4cb2cb	345	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
1da177e4 LT	346	kfree(sn_irq_info);
	347	}
	348
	349	void sn_irq_fixup(struct pci_dev pci_dev, struct sn_irq_info sn_irq_info)
	350	{
	351	nasid_t nasid = sn_irq_info->irq_nasid;
	352	int slice = sn_irq_info->irq_slice;
	353	int cpu = nasid_slice_to_cpuid(nasid, slice);
c6957771 JK	354	#ifdef CONFIG_SMP
	355	int cpuphys;
	356	#endif
1da177e4	357
cb4cb2cb	358	pci_dev_get(pci_dev);
1da177e4 LT	359	sn_irq_info->irq_cpuid = cpu;
	360	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
	361
	362	/* link it into the sn_irq[irq] list */
cb4cb2cb PB	363	spin_lock(&sn_irq_info_lock);
cb4cb2cb PB	364	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
10083072	365	reserve_irq_vector(sn_irq_info->irq_irq);
cb4cb2cb	366	spin_unlock(&sn_irq_info_lock);
1da177e4	367
2fcc3db0	368	register_intr_pda(sn_irq_info);
c6957771 JK	369	#ifdef CONFIG_SMP
	370	cpuphys = cpu_physical_id(cpu);
	371	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
	372	#endif
1da177e4 LT	373	}
1da177e4 LT	374
cb4cb2cb PB	375	void sn_irq_unfixup(struct pci_dev *pci_dev)
	376	{
	377	struct sn_irq_info *sn_irq_info;
	378
	379	/* Only cleanup IRQ stuff if this device has a host bus context */
	380	if (!SN_PCIDEV_BUSSOFT(pci_dev))
	381	return;
	382
	383	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
8b34ff42 PB	384	if (!sn_irq_info)
	385	return;
	386	if (!sn_irq_info->irq_irq) {
6f354b01	387	kfree(sn_irq_info);
cb4cb2cb	388	return;
6f354b01	389	}
cb4cb2cb PB	390
	391	unregister_intr_pda(sn_irq_info);
	392	spin_lock(&sn_irq_info_lock);
	393	list_del_rcu(&sn_irq_info->list);
	394	spin_unlock(&sn_irq_info_lock);
10083072 MM	395	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
10083072 MM	396	free_irq_vector(sn_irq_info->irq_irq);
cb4cb2cb	397	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
cb4cb2cb	398	pci_dev_put(pci_dev);
10083072	399
cb4cb2cb PB	400	}
cb4cb2cb PB	401
735e60f4 MM	402	static inline void
	403	sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
	404	{
	405	struct sn_pcibus_provider *pci_provider;
	406
	407	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	408	if (pci_provider && pci_provider->force_interrupt)
	409	(*pci_provider->force_interrupt)(sn_irq_info);
	410	}
	411
1da177e4 LT	412	static void force_interrupt(int irq)
	413	{
	414	struct sn_irq_info *sn_irq_info;
	415
	416	if (!sn_ioif_inited)
	417	return;
cb4cb2cb PB	418
cb4cb2cb PB	419	rcu_read_lock();
735e60f4 MM	420	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
	421	sn_call_force_intr_provider(sn_irq_info);
	422
cb4cb2cb	423	rcu_read_unlock();
1da177e4 LT	424	}
	425
	426	/*
	427	* Check for lost interrupts. If the PIC int_status reg. says that
	428	* an interrupt has been sent, but not handled, and the interrupt
	429	* is not pending in either the cpu irr regs or in the soft irr regs,
	430	* and the interrupt is not in service, then the interrupt may have
	431	* been lost. Force an interrupt on that pin. It is possible that
	432	* the interrupt is in flight, so we may generate a spurious interrupt,
	433	* but we should never miss a real lost interrupt.
	434	*/
	435	static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
	436	{
53493dcf	437	u64 regval;
1da177e4 LT	438	struct pcidev_info *pcidev_info;
	439	struct pcibus_info *pcibus_info;
	440
735e60f4 MM	441	/*
	442	* Bridge types attached to TIO (anything but PIC) do not need this WAR
	443	* since they do not target Shub II interrupt registers. If that
	444	* ever changes, this check needs to accomodate.
	445	*/
	446	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
	447	return;
	448
1da177e4 LT	449	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	450	if (!pcidev_info)
	451	return;
	452
	453	pcibus_info =
	454	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	455	pdi_pcibus_info;
	456	regval = pcireg_intr_status_get(pcibus_info);
	457
9a4e5549	458	if (!ia64_get_irr(irq_to_vector(irq))) {
735e60f4 MM	459	if (!test_bit(irq, pda->sn_in_service_ivecs)) {
	460	regval &= 0xff;
	461	if (sn_irq_info->irq_int_bit & regval &
	462	sn_irq_info->irq_last_intr) {
	463	regval &= ~(sn_irq_info->irq_int_bit & regval);
	464	sn_call_force_intr_provider(sn_irq_info);
1da177e4 LT	465	}
	466	}
	467	}
	468	sn_irq_info->irq_last_intr = regval;
	469	}
	470
	471	void sn_lb_int_war_check(void)
	472	{
cb4cb2cb	473	struct sn_irq_info *sn_irq_info;
1da177e4 LT	474	int i;
	475
	476	if (!sn_ioif_inited \|\| pda->sn_first_irq == 0)
	477	return;
cb4cb2cb PB	478
cb4cb2cb PB	479	rcu_read_lock();
1da177e4	480	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
cb4cb2cb	481	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
735e60f4	482	sn_check_intr(i, sn_irq_info);
1da177e4 LT	483	}
1da177e4 LT	484	}
cb4cb2cb PB	485	rcu_read_unlock();
	486	}
	487
2fcc3db0	488	void __init sn_irq_lh_init(void)
cb4cb2cb PB	489	{
	490	int i;
	491
	492	sn_irq_lh = kmalloc(sizeof(struct list_head ) NR_IRQS, GFP_KERNEL);
	493	if (!sn_irq_lh)
	494	panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
	495
	496	for (i = 0; i < NR_IRQS; i++) {
	497	sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
	498	if (!sn_irq_lh[i])
	499	panic("SN PCI INIT: Failed IRQ memory allocation\n");
	500
	501	INIT_LIST_HEAD(sn_irq_lh[i]);
	502	}
1da177e4	503	}