Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Platform dependent support for SGI SN | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
2fcc3db0 | 8 | * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/irq.h> | |
cb4cb2cb | 12 | #include <linux/spinlock.h> |
2fcc3db0 | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <asm/sn/addrs.h> |
15 | #include <asm/sn/arch.h> | |
c13cf371 PB |
16 | #include <asm/sn/intr.h> |
17 | #include <asm/sn/pcibr_provider.h> | |
9b08ebd1 MM |
18 | #include <asm/sn/pcibus_provider_defs.h> |
19 | #include <asm/sn/pcidev.h> | |
1da177e4 LT |
20 | #include <asm/sn/shub_mmr.h> |
21 | #include <asm/sn/sn_sal.h> | |
6e9de181 | 22 | #include <asm/sn/sn_feature_sets.h> |
1da177e4 LT |
23 | |
24 | static void force_interrupt(int irq); | |
25 | static void register_intr_pda(struct sn_irq_info *sn_irq_info); | |
26 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); | |
27 | ||
d0d59b98 | 28 | int sn_force_interrupt_flag = 1; |
1da177e4 | 29 | extern int sn_ioif_inited; |
83821d3f | 30 | struct list_head **sn_irq_lh; |
34af946a | 31 | static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */ |
1da177e4 | 32 | |
83821d3f MM |
33 | u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, |
34 | struct sn_irq_info *sn_irq_info, | |
1da177e4 LT |
35 | int req_irq, nasid_t req_nasid, |
36 | int req_slice) | |
37 | { | |
38 | struct ia64_sal_retval ret_stuff; | |
39 | ret_stuff.status = 0; | |
40 | ret_stuff.v0 = 0; | |
41 | ||
42 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
43 | (u64) SAL_INTR_ALLOC, (u64) local_nasid, | |
83821d3f | 44 | (u64) local_widget, __pa(sn_irq_info), (u64) req_irq, |
1da177e4 | 45 | (u64) req_nasid, (u64) req_slice); |
83821d3f | 46 | |
1da177e4 LT |
47 | return ret_stuff.status; |
48 | } | |
49 | ||
83821d3f | 50 | void sn_intr_free(nasid_t local_nasid, int local_widget, |
1da177e4 LT |
51 | struct sn_irq_info *sn_irq_info) |
52 | { | |
53 | struct ia64_sal_retval ret_stuff; | |
54 | ret_stuff.status = 0; | |
55 | ret_stuff.v0 = 0; | |
56 | ||
57 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
58 | (u64) SAL_INTR_FREE, (u64) local_nasid, | |
59 | (u64) local_widget, (u64) sn_irq_info->irq_irq, | |
60 | (u64) sn_irq_info->irq_cookie, 0, 0); | |
61 | } | |
62 | ||
0e17b560 JK |
63 | u64 sn_intr_redirect(nasid_t local_nasid, int local_widget, |
64 | struct sn_irq_info *sn_irq_info, | |
65 | nasid_t req_nasid, int req_slice) | |
66 | { | |
67 | struct ia64_sal_retval ret_stuff; | |
68 | ret_stuff.status = 0; | |
69 | ret_stuff.v0 = 0; | |
70 | ||
71 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
72 | (u64) SAL_INTR_REDIRECT, (u64) local_nasid, | |
73 | (u64) local_widget, __pa(sn_irq_info), | |
74 | (u64) req_nasid, (u64) req_slice, 0); | |
75 | ||
76 | return ret_stuff.status; | |
77 | } | |
78 | ||
1da177e4 LT |
79 | static unsigned int sn_startup_irq(unsigned int irq) |
80 | { | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static void sn_shutdown_irq(unsigned int irq) | |
85 | { | |
86 | } | |
87 | ||
88 | static void sn_disable_irq(unsigned int irq) | |
89 | { | |
90 | } | |
91 | ||
92 | static void sn_enable_irq(unsigned int irq) | |
93 | { | |
94 | } | |
95 | ||
96 | static void sn_ack_irq(unsigned int irq) | |
97 | { | |
2fcc3db0 | 98 | u64 event_occurred, mask; |
1da177e4 LT |
99 | |
100 | irq = irq & 0xff; | |
2fcc3db0 | 101 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); |
be539c73 | 102 | mask = event_occurred & SH_ALL_INT_MASK; |
2fcc3db0 | 103 | HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); |
1da177e4 LT |
104 | __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); |
105 | ||
689388bb | 106 | move_native_irq(irq); |
1da177e4 LT |
107 | } |
108 | ||
109 | static void sn_end_irq(unsigned int irq) | |
110 | { | |
1da177e4 | 111 | int ivec; |
0aa2c72e | 112 | u64 event_occurred; |
1da177e4 LT |
113 | |
114 | ivec = irq & 0xff; | |
115 | if (ivec == SGI_UART_VECTOR) { | |
0aa2c72e | 116 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED)); |
cb4cb2cb | 117 | /* If the UART bit is set here, we may have received an |
1da177e4 LT |
118 | * interrupt from the UART that the driver missed. To |
119 | * make sure, we IPI ourselves to force us to look again. | |
120 | */ | |
121 | if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) { | |
122 | platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, | |
123 | IA64_IPI_DM_INT, 0); | |
124 | } | |
125 | } | |
126 | __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs); | |
127 | if (sn_force_interrupt_flag) | |
128 | force_interrupt(irq); | |
129 | } | |
130 | ||
cb4cb2cb PB |
131 | static void sn_irq_info_free(struct rcu_head *head); |
132 | ||
83821d3f MM |
133 | struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info, |
134 | nasid_t nasid, int slice) | |
1da177e4 | 135 | { |
83821d3f | 136 | int vector; |
c6957771 JK |
137 | int cpuid; |
138 | #ifdef CONFIG_SMP | |
83821d3f | 139 | int cpuphys; |
c6957771 | 140 | #endif |
83821d3f MM |
141 | int64_t bridge; |
142 | int local_widget, status; | |
143 | nasid_t local_nasid; | |
144 | struct sn_irq_info *new_irq_info; | |
145 | struct sn_pcibus_provider *pci_provider; | |
146 | ||
0e17b560 | 147 | bridge = (u64) sn_irq_info->irq_bridge; |
83821d3f | 148 | if (!bridge) { |
83821d3f MM |
149 | return NULL; /* irq is not a device interrupt */ |
150 | } | |
1da177e4 | 151 | |
83821d3f | 152 | local_nasid = NASID_GET(bridge); |
1da177e4 | 153 | |
83821d3f MM |
154 | if (local_nasid & 1) |
155 | local_widget = TIO_SWIN_WIDGETNUM(bridge); | |
156 | else | |
157 | local_widget = SWIN_WIDGETNUM(bridge); | |
83821d3f | 158 | vector = sn_irq_info->irq_irq; |
0e17b560 JK |
159 | |
160 | /* Make use of SAL_INTR_REDIRECT if PROM supports it */ | |
161 | status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice); | |
162 | if (!status) { | |
163 | new_irq_info = sn_irq_info; | |
164 | goto finish_up; | |
165 | } | |
166 | ||
167 | /* | |
168 | * PROM does not support SAL_INTR_REDIRECT, or it failed. | |
169 | * Revert to old method. | |
170 | */ | |
171 | new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); | |
172 | if (new_irq_info == NULL) | |
173 | return NULL; | |
174 | ||
175 | memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); | |
176 | ||
83821d3f MM |
177 | /* Free the old PROM new_irq_info structure */ |
178 | sn_intr_free(local_nasid, local_widget, new_irq_info); | |
83821d3f | 179 | unregister_intr_pda(new_irq_info); |
1da177e4 | 180 | |
83821d3f MM |
181 | /* allocate a new PROM new_irq_info struct */ |
182 | status = sn_intr_alloc(local_nasid, local_widget, | |
183 | new_irq_info, vector, | |
184 | nasid, slice); | |
1da177e4 | 185 | |
83821d3f MM |
186 | /* SAL call failed */ |
187 | if (status) { | |
188 | kfree(new_irq_info); | |
189 | return NULL; | |
190 | } | |
cb4cb2cb | 191 | |
0e17b560 JK |
192 | register_intr_pda(new_irq_info); |
193 | spin_lock(&sn_irq_info_lock); | |
194 | list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); | |
195 | spin_unlock(&sn_irq_info_lock); | |
196 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); | |
197 | ||
198 | ||
199 | finish_up: | |
c6957771 JK |
200 | /* Update kernels new_irq_info with new target info */ |
201 | cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid, | |
202 | new_irq_info->irq_slice); | |
203 | new_irq_info->irq_cpuid = cpuid; | |
1da177e4 | 204 | |
83821d3f | 205 | pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type]; |
cb4cb2cb | 206 | |
83821d3f MM |
207 | /* |
208 | * If this represents a line interrupt, target it. If it's | |
209 | * an msi (irq_int_bit < 0), it's already targeted. | |
210 | */ | |
211 | if (new_irq_info->irq_int_bit >= 0 && | |
212 | pci_provider && pci_provider->target_interrupt) | |
213 | (pci_provider->target_interrupt)(new_irq_info); | |
cb4cb2cb | 214 | |
1da177e4 | 215 | #ifdef CONFIG_SMP |
c6957771 | 216 | cpuphys = cpu_physical_id(cpuid); |
83821d3f | 217 | set_irq_affinity_info((vector & 0xff), cpuphys, 0); |
1da177e4 | 218 | #endif |
83821d3f MM |
219 | |
220 | return new_irq_info; | |
221 | } | |
222 | ||
223 | static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) | |
224 | { | |
225 | struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; | |
226 | nasid_t nasid; | |
227 | int slice; | |
228 | ||
229 | nasid = cpuid_to_nasid(first_cpu(mask)); | |
230 | slice = cpuid_to_slice(first_cpu(mask)); | |
231 | ||
232 | list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, | |
233 | sn_irq_lh[irq], list) | |
234 | (void)sn_retarget_vector(sn_irq_info, nasid, slice); | |
1da177e4 LT |
235 | } |
236 | ||
6e9de181 JK |
237 | #ifdef CONFIG_SMP |
238 | void sn_set_err_irq_affinity(unsigned int irq) | |
239 | { | |
240 | /* | |
241 | * On systems which support CPU disabling (SHub2), all error interrupts | |
242 | * are targetted at the boot CPU. | |
243 | */ | |
244 | if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) | |
245 | set_irq_affinity_info(irq, cpu_physical_id(0), 0); | |
246 | } | |
247 | #else | |
248 | void sn_set_err_irq_affinity(unsigned int irq) { } | |
249 | #endif | |
250 | ||
e253eb0c KH |
251 | static void |
252 | sn_mask_irq(unsigned int irq) | |
253 | { | |
254 | } | |
255 | ||
256 | static void | |
257 | sn_unmask_irq(unsigned int irq) | |
258 | { | |
259 | } | |
260 | ||
261 | struct irq_chip irq_type_sn = { | |
06344db3 | 262 | .name = "SN hub", |
cb4cb2cb PB |
263 | .startup = sn_startup_irq, |
264 | .shutdown = sn_shutdown_irq, | |
265 | .enable = sn_enable_irq, | |
266 | .disable = sn_disable_irq, | |
267 | .ack = sn_ack_irq, | |
268 | .end = sn_end_irq, | |
e253eb0c KH |
269 | .mask = sn_mask_irq, |
270 | .unmask = sn_unmask_irq, | |
cb4cb2cb | 271 | .set_affinity = sn_set_affinity_irq |
1da177e4 LT |
272 | }; |
273 | ||
1115200a KK |
274 | ia64_vector sn_irq_to_vector(int irq) |
275 | { | |
276 | if (irq >= IA64_NUM_VECTORS) | |
277 | return 0; | |
278 | return (ia64_vector)irq; | |
279 | } | |
280 | ||
1da177e4 LT |
281 | unsigned int sn_local_vector_to_irq(u8 vector) |
282 | { | |
283 | return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector)); | |
284 | } | |
285 | ||
286 | void sn_irq_init(void) | |
287 | { | |
288 | int i; | |
289 | irq_desc_t *base_desc = irq_desc; | |
290 | ||
10083072 MM |
291 | ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; |
292 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; | |
293 | ||
1da177e4 | 294 | for (i = 0; i < NR_IRQS; i++) { |
d1bef4ed IM |
295 | if (base_desc[i].chip == &no_irq_type) { |
296 | base_desc[i].chip = &irq_type_sn; | |
1da177e4 LT |
297 | } |
298 | } | |
299 | } | |
300 | ||
301 | static void register_intr_pda(struct sn_irq_info *sn_irq_info) | |
302 | { | |
303 | int irq = sn_irq_info->irq_irq; | |
304 | int cpu = sn_irq_info->irq_cpuid; | |
305 | ||
306 | if (pdacpu(cpu)->sn_last_irq < irq) { | |
307 | pdacpu(cpu)->sn_last_irq = irq; | |
308 | } | |
309 | ||
2fcc3db0 | 310 | if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) |
1da177e4 | 311 | pdacpu(cpu)->sn_first_irq = irq; |
1da177e4 LT |
312 | } |
313 | ||
314 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info) | |
315 | { | |
316 | int irq = sn_irq_info->irq_irq; | |
317 | int cpu = sn_irq_info->irq_cpuid; | |
318 | struct sn_irq_info *tmp_irq_info; | |
319 | int i, foundmatch; | |
320 | ||
cb4cb2cb | 321 | rcu_read_lock(); |
1da177e4 LT |
322 | if (pdacpu(cpu)->sn_last_irq == irq) { |
323 | foundmatch = 0; | |
cb4cb2cb PB |
324 | for (i = pdacpu(cpu)->sn_last_irq - 1; |
325 | i && !foundmatch; i--) { | |
326 | list_for_each_entry_rcu(tmp_irq_info, | |
327 | sn_irq_lh[i], | |
328 | list) { | |
1da177e4 | 329 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 330 | foundmatch = 1; |
1da177e4 LT |
331 | break; |
332 | } | |
1da177e4 LT |
333 | } |
334 | } | |
335 | pdacpu(cpu)->sn_last_irq = i; | |
336 | } | |
337 | ||
338 | if (pdacpu(cpu)->sn_first_irq == irq) { | |
339 | foundmatch = 0; | |
cb4cb2cb PB |
340 | for (i = pdacpu(cpu)->sn_first_irq + 1; |
341 | i < NR_IRQS && !foundmatch; i++) { | |
342 | list_for_each_entry_rcu(tmp_irq_info, | |
343 | sn_irq_lh[i], | |
344 | list) { | |
1da177e4 | 345 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 346 | foundmatch = 1; |
1da177e4 LT |
347 | break; |
348 | } | |
1da177e4 LT |
349 | } |
350 | } | |
351 | pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i); | |
352 | } | |
cb4cb2cb | 353 | rcu_read_unlock(); |
1da177e4 LT |
354 | } |
355 | ||
cb4cb2cb | 356 | static void sn_irq_info_free(struct rcu_head *head) |
1da177e4 LT |
357 | { |
358 | struct sn_irq_info *sn_irq_info; | |
1da177e4 | 359 | |
cb4cb2cb | 360 | sn_irq_info = container_of(head, struct sn_irq_info, rcu); |
1da177e4 LT |
361 | kfree(sn_irq_info); |
362 | } | |
363 | ||
364 | void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) | |
365 | { | |
366 | nasid_t nasid = sn_irq_info->irq_nasid; | |
367 | int slice = sn_irq_info->irq_slice; | |
368 | int cpu = nasid_slice_to_cpuid(nasid, slice); | |
c6957771 JK |
369 | #ifdef CONFIG_SMP |
370 | int cpuphys; | |
371 | #endif | |
1da177e4 | 372 | |
cb4cb2cb | 373 | pci_dev_get(pci_dev); |
1da177e4 LT |
374 | sn_irq_info->irq_cpuid = cpu; |
375 | sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev); | |
376 | ||
377 | /* link it into the sn_irq[irq] list */ | |
cb4cb2cb PB |
378 | spin_lock(&sn_irq_info_lock); |
379 | list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]); | |
10083072 | 380 | reserve_irq_vector(sn_irq_info->irq_irq); |
cb4cb2cb | 381 | spin_unlock(&sn_irq_info_lock); |
1da177e4 | 382 | |
2fcc3db0 | 383 | register_intr_pda(sn_irq_info); |
c6957771 JK |
384 | #ifdef CONFIG_SMP |
385 | cpuphys = cpu_physical_id(cpu); | |
386 | set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); | |
387 | #endif | |
1da177e4 LT |
388 | } |
389 | ||
cb4cb2cb PB |
390 | void sn_irq_unfixup(struct pci_dev *pci_dev) |
391 | { | |
392 | struct sn_irq_info *sn_irq_info; | |
393 | ||
394 | /* Only cleanup IRQ stuff if this device has a host bus context */ | |
395 | if (!SN_PCIDEV_BUSSOFT(pci_dev)) | |
396 | return; | |
397 | ||
398 | sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info; | |
8b34ff42 PB |
399 | if (!sn_irq_info) |
400 | return; | |
401 | if (!sn_irq_info->irq_irq) { | |
6f354b01 | 402 | kfree(sn_irq_info); |
cb4cb2cb | 403 | return; |
6f354b01 | 404 | } |
cb4cb2cb PB |
405 | |
406 | unregister_intr_pda(sn_irq_info); | |
407 | spin_lock(&sn_irq_info_lock); | |
408 | list_del_rcu(&sn_irq_info->list); | |
409 | spin_unlock(&sn_irq_info_lock); | |
10083072 MM |
410 | if (list_empty(sn_irq_lh[sn_irq_info->irq_irq])) |
411 | free_irq_vector(sn_irq_info->irq_irq); | |
cb4cb2cb | 412 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); |
cb4cb2cb | 413 | pci_dev_put(pci_dev); |
10083072 | 414 | |
cb4cb2cb PB |
415 | } |
416 | ||
735e60f4 MM |
417 | static inline void |
418 | sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info) | |
419 | { | |
420 | struct sn_pcibus_provider *pci_provider; | |
421 | ||
422 | pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; | |
352b0ef5 MH |
423 | |
424 | /* Don't force an interrupt if the irq has been disabled */ | |
425 | if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) && | |
426 | pci_provider && pci_provider->force_interrupt) | |
735e60f4 MM |
427 | (*pci_provider->force_interrupt)(sn_irq_info); |
428 | } | |
429 | ||
1da177e4 LT |
430 | static void force_interrupt(int irq) |
431 | { | |
432 | struct sn_irq_info *sn_irq_info; | |
433 | ||
434 | if (!sn_ioif_inited) | |
435 | return; | |
cb4cb2cb PB |
436 | |
437 | rcu_read_lock(); | |
735e60f4 MM |
438 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) |
439 | sn_call_force_intr_provider(sn_irq_info); | |
440 | ||
cb4cb2cb | 441 | rcu_read_unlock(); |
1da177e4 LT |
442 | } |
443 | ||
444 | /* | |
445 | * Check for lost interrupts. If the PIC int_status reg. says that | |
446 | * an interrupt has been sent, but not handled, and the interrupt | |
447 | * is not pending in either the cpu irr regs or in the soft irr regs, | |
448 | * and the interrupt is not in service, then the interrupt may have | |
449 | * been lost. Force an interrupt on that pin. It is possible that | |
450 | * the interrupt is in flight, so we may generate a spurious interrupt, | |
451 | * but we should never miss a real lost interrupt. | |
452 | */ | |
453 | static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) | |
454 | { | |
53493dcf | 455 | u64 regval; |
1da177e4 LT |
456 | struct pcidev_info *pcidev_info; |
457 | struct pcibus_info *pcibus_info; | |
458 | ||
735e60f4 MM |
459 | /* |
460 | * Bridge types attached to TIO (anything but PIC) do not need this WAR | |
461 | * since they do not target Shub II interrupt registers. If that | |
462 | * ever changes, this check needs to accomodate. | |
463 | */ | |
464 | if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC) | |
465 | return; | |
466 | ||
1da177e4 LT |
467 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; |
468 | if (!pcidev_info) | |
469 | return; | |
470 | ||
471 | pcibus_info = | |
472 | (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info-> | |
473 | pdi_pcibus_info; | |
474 | regval = pcireg_intr_status_get(pcibus_info); | |
475 | ||
9a4e5549 | 476 | if (!ia64_get_irr(irq_to_vector(irq))) { |
735e60f4 MM |
477 | if (!test_bit(irq, pda->sn_in_service_ivecs)) { |
478 | regval &= 0xff; | |
479 | if (sn_irq_info->irq_int_bit & regval & | |
480 | sn_irq_info->irq_last_intr) { | |
481 | regval &= ~(sn_irq_info->irq_int_bit & regval); | |
482 | sn_call_force_intr_provider(sn_irq_info); | |
1da177e4 LT |
483 | } |
484 | } | |
485 | } | |
486 | sn_irq_info->irq_last_intr = regval; | |
487 | } | |
488 | ||
489 | void sn_lb_int_war_check(void) | |
490 | { | |
cb4cb2cb | 491 | struct sn_irq_info *sn_irq_info; |
1da177e4 LT |
492 | int i; |
493 | ||
494 | if (!sn_ioif_inited || pda->sn_first_irq == 0) | |
495 | return; | |
cb4cb2cb PB |
496 | |
497 | rcu_read_lock(); | |
1da177e4 | 498 | for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) { |
cb4cb2cb | 499 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) { |
735e60f4 | 500 | sn_check_intr(i, sn_irq_info); |
1da177e4 LT |
501 | } |
502 | } | |
cb4cb2cb PB |
503 | rcu_read_unlock(); |
504 | } | |
505 | ||
2fcc3db0 | 506 | void __init sn_irq_lh_init(void) |
cb4cb2cb PB |
507 | { |
508 | int i; | |
509 | ||
510 | sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL); | |
511 | if (!sn_irq_lh) | |
512 | panic("SN PCI INIT: Failed to allocate memory for PCI init\n"); | |
513 | ||
514 | for (i = 0; i < NR_IRQS; i++) { | |
515 | sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL); | |
516 | if (!sn_irq_lh[i]) | |
517 | panic("SN PCI INIT: Failed IRQ memory allocation\n"); | |
518 | ||
519 | INIT_LIST_HEAD(sn_irq_lh[i]); | |
520 | } | |
1da177e4 | 521 | } |