[deliverable/linux.git] / arch / ia64 / sn / kernel / irq.c

/*
 * Platform dependent support for SGI SN
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
 */

#include <linux/irq.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/shub_mmr.h>
#include <asm/sn/sn_sal.h>

static void force_interrupt(int irq);
static void register_intr_pda(struct sn_irq_info *sn_irq_info);
static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);

int sn_force_interrupt_flag = 1;
extern int sn_ioif_inited;
struct list_head **sn_irq_lh;
static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */

u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
				     struct sn_irq_info *sn_irq_info,
				     int req_irq, nasid_t req_nasid,
				     int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
			(u64) req_nasid, (u64) req_slice);

	return ret_stuff.status;
}

void sn_intr_free(nasid_t local_nasid, int local_widget,
				struct sn_irq_info *sn_irq_info)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_FREE, (u64) local_nasid,
			(u64) local_widget, (u64) sn_irq_info->irq_irq,
			(u64) sn_irq_info->irq_cookie, 0, 0);
}

static unsigned int sn_startup_irq(unsigned int irq)
{
	return 0;
}

static void sn_shutdown_irq(unsigned int irq)
{
}

static void sn_disable_irq(unsigned int irq)
{
}

static void sn_enable_irq(unsigned int irq)
{
}

static void sn_ack_irq(unsigned int irq)
{
	u64 event_occurred, mask;

	irq = irq & 0xff;
	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
	mask = event_occurred & SH_ALL_INT_MASK;
	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);

	move_native_irq(irq);
}

static void sn_end_irq(unsigned int irq)
{
	int ivec;
	u64 event_occurred;

	ivec = irq & 0xff;
	if (ivec == SGI_UART_VECTOR) {
		event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
		/* If the UART bit is set here, we may have received an
		 * interrupt from the UART that the driver missed.  To
		 * make sure, we IPI ourselves to force us to look again.
		 */
		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
			platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
					  IA64_IPI_DM_INT, 0);
		}
	}
	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	if (sn_force_interrupt_flag)
		force_interrupt(irq);
}

static void sn_irq_info_free(struct rcu_head *head);

struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
				       nasid_t nasid, int slice)
{
	int vector;
	int cpuid;
#ifdef CONFIG_SMP
	int cpuphys;
#endif
	int64_t bridge;
	int local_widget, status;
	nasid_t local_nasid;
	struct sn_irq_info *new_irq_info;
	struct sn_pcibus_provider *pci_provider;

	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
	if (new_irq_info == NULL)
		return NULL;

	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));

	bridge = (u64) new_irq_info->irq_bridge;
	if (!bridge) {
		kfree(new_irq_info);
		return NULL; /* irq is not a device interrupt */
	}

	local_nasid = NASID_GET(bridge);

	if (local_nasid & 1)
		local_widget = TIO_SWIN_WIDGETNUM(bridge);
	else
		local_widget = SWIN_WIDGETNUM(bridge);

	vector = sn_irq_info->irq_irq;
	/* Free the old PROM new_irq_info structure */
	sn_intr_free(local_nasid, local_widget, new_irq_info);
	unregister_intr_pda(new_irq_info);

	/* allocate a new PROM new_irq_info struct */
	status = sn_intr_alloc(local_nasid, local_widget,
			       new_irq_info, vector,
			       nasid, slice);

	/* SAL call failed */
	if (status) {
		kfree(new_irq_info);
		return NULL;
	}

	/* Update kernels new_irq_info with new target info */
	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
				     new_irq_info->irq_slice);
	new_irq_info->irq_cpuid = cpuid;
	register_intr_pda(new_irq_info);

	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];

	/*
	 * If this represents a line interrupt, target it.  If it's
	 * an msi (irq_int_bit < 0), it's already targeted.
	 */
	if (new_irq_info->irq_int_bit >= 0 &&
	    pci_provider && pci_provider->target_interrupt)
		(pci_provider->target_interrupt)(new_irq_info);

	spin_lock(&sn_irq_info_lock);
	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);

#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpuid);
	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
#endif

	return new_irq_info;
}

static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
{
	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
	nasid_t nasid;
	int slice;

	nasid = cpuid_to_nasid(first_cpu(mask));
	slice = cpuid_to_slice(first_cpu(mask));

	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
				 sn_irq_lh[irq], list)
		(void)sn_retarget_vector(sn_irq_info, nasid, slice);
}

static void
sn_mask_irq(unsigned int irq)
{
}

static void
sn_unmask_irq(unsigned int irq)
{
}

struct irq_chip irq_type_sn = {
	.name		= "SN hub",
	.startup	= sn_startup_irq,
	.shutdown	= sn_shutdown_irq,
	.enable		= sn_enable_irq,
	.disable	= sn_disable_irq,
	.ack		= sn_ack_irq,
	.end		= sn_end_irq,
	.mask		= sn_mask_irq,
	.unmask		= sn_unmask_irq,
	.set_affinity	= sn_set_affinity_irq
};

unsigned int sn_local_vector_to_irq(u8 vector)
{
	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
}

void sn_irq_init(void)
{
	int i;
	irq_desc_t *base_desc = irq_desc;

	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;

	for (i = 0; i < NR_IRQS; i++) {
		if (base_desc[i].chip == &no_irq_type) {
			base_desc[i].chip = &irq_type_sn;
		}
	}
}

static void register_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;

	if (pdacpu(cpu)->sn_last_irq < irq) {
		pdacpu(cpu)->sn_last_irq = irq;
	}

	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
		pdacpu(cpu)->sn_first_irq = irq;
}

static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;
	struct sn_irq_info *tmp_irq_info;
	int i, foundmatch;

	rcu_read_lock();
	if (pdacpu(cpu)->sn_last_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_last_irq - 1;
		     i && !foundmatch; i--) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_last_irq = i;
	}

	if (pdacpu(cpu)->sn_first_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_first_irq + 1;
		     i < NR_IRQS && !foundmatch; i++) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	}
	rcu_read_unlock();
}

static void sn_irq_info_free(struct rcu_head *head)
{
	struct sn_irq_info *sn_irq_info;

	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
	kfree(sn_irq_info);
}

void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
{
	nasid_t nasid = sn_irq_info->irq_nasid;
	int slice = sn_irq_info->irq_slice;
	int cpu = nasid_slice_to_cpuid(nasid, slice);
#ifdef CONFIG_SMP
	int cpuphys;
#endif

	pci_dev_get(pci_dev);
	sn_irq_info->irq_cpuid = cpu;
	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);

	/* link it into the sn_irq[irq] list */
	spin_lock(&sn_irq_info_lock);
	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
	reserve_irq_vector(sn_irq_info->irq_irq);
	spin_unlock(&sn_irq_info_lock);

	register_intr_pda(sn_irq_info);
#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpu);
	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
#endif
}

void sn_irq_unfixup(struct pci_dev *pci_dev)
{
	struct sn_irq_info *sn_irq_info;

	/* Only cleanup IRQ stuff if this device has a host bus context */
	if (!SN_PCIDEV_BUSSOFT(pci_dev))
		return;

	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
	if (!sn_irq_info)
		return;
	if (!sn_irq_info->irq_irq) {
		kfree(sn_irq_info);
		return;
	}

	unregister_intr_pda(sn_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_del_rcu(&sn_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
		free_irq_vector(sn_irq_info->irq_irq);
	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
	pci_dev_put(pci_dev);

}

static inline void
sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
{
	struct sn_pcibus_provider *pci_provider;

	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	if (pci_provider && pci_provider->force_interrupt)
		(*pci_provider->force_interrupt)(sn_irq_info);
}

static void force_interrupt(int irq)
{
	struct sn_irq_info *sn_irq_info;

	if (!sn_ioif_inited)
		return;

	rcu_read_lock();
	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
		sn_call_force_intr_provider(sn_irq_info);

	rcu_read_unlock();
}

/*
 * Check for lost interrupts.  If the PIC int_status reg. says that
 * an interrupt has been sent, but not handled, and the interrupt
 * is not pending in either the cpu irr regs or in the soft irr regs,
 * and the interrupt is not in service, then the interrupt may have
 * been lost.  Force an interrupt on that pin.  It is possible that
 * the interrupt is in flight, so we may generate a spurious interrupt,
 * but we should never miss a real lost interrupt.
 */
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
{
	u64 regval;
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;

	/*
	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
	 * since they do not target Shub II interrupt registers.  If that
	 * ever changes, this check needs to accomodate.
	 */
	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (!pcidev_info)
		return;

	pcibus_info =
	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	    pdi_pcibus_info;
	regval = pcireg_intr_status_get(pcibus_info);

	if (!ia64_get_irr(irq_to_vector(irq))) {
		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
			regval &= 0xff;
			if (sn_irq_info->irq_int_bit & regval &
			    sn_irq_info->irq_last_intr) {
				regval &= ~(sn_irq_info->irq_int_bit & regval);
				sn_call_force_intr_provider(sn_irq_info);
			}
		}
	}
	sn_irq_info->irq_last_intr = regval;
}

void sn_lb_int_war_check(void)
{
	struct sn_irq_info *sn_irq_info;
	int i;

	if (!sn_ioif_inited || pda->sn_first_irq == 0)
		return;

	rcu_read_lock();
	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
			sn_check_intr(i, sn_irq_info);
		}
	}
	rcu_read_unlock();
}

void __init sn_irq_lh_init(void)
{
	int i;

	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
	if (!sn_irq_lh)
		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");

	for (i = 0; i < NR_IRQS; i++) {
		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
		if (!sn_irq_lh[i])
			panic("SN PCI INIT: Failed IRQ memory allocation\n");

		INIT_LIST_HEAD(sn_irq_lh[i]);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Platform dependent support for SGI SN
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
2fcc3db0	8	* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
1da177e4 LT	9	*/
	10
	11	#include <linux/irq.h>
cb4cb2cb	12	#include <linux/spinlock.h>
2fcc3db0	13	#include <linux/init.h>
1da177e4 LT	14	#include <asm/sn/addrs.h>
1da177e4 LT	15	#include <asm/sn/arch.h>
c13cf371 PB	16	#include <asm/sn/intr.h>
c13cf371 PB	17	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	18	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	19	#include <asm/sn/pcidev.h>
1da177e4 LT	20	#include <asm/sn/shub_mmr.h>
	21	#include <asm/sn/sn_sal.h>
	22
	23	static void force_interrupt(int irq);
	24	static void register_intr_pda(struct sn_irq_info *sn_irq_info);
	25	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
	26
d0d59b98	27	int sn_force_interrupt_flag = 1;
1da177e4	28	extern int sn_ioif_inited;
83821d3f	29	struct list_head **sn_irq_lh;
34af946a	30	static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
1da177e4	31
83821d3f MM	32	u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
83821d3f MM	33	struct sn_irq_info *sn_irq_info,
1da177e4 LT	34	int req_irq, nasid_t req_nasid,
	35	int req_slice)
	36	{
	37	struct ia64_sal_retval ret_stuff;
	38	ret_stuff.status = 0;
	39	ret_stuff.v0 = 0;
	40
	41	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	42	(u64) SAL_INTR_ALLOC, (u64) local_nasid,
83821d3f	43	(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
1da177e4	44	(u64) req_nasid, (u64) req_slice);
83821d3f	45
1da177e4 LT	46	return ret_stuff.status;
	47	}
	48
83821d3f	49	void sn_intr_free(nasid_t local_nasid, int local_widget,
1da177e4 LT	50	struct sn_irq_info *sn_irq_info)
	51	{
	52	struct ia64_sal_retval ret_stuff;
	53	ret_stuff.status = 0;
	54	ret_stuff.v0 = 0;
	55
	56	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	57	(u64) SAL_INTR_FREE, (u64) local_nasid,
	58	(u64) local_widget, (u64) sn_irq_info->irq_irq,
	59	(u64) sn_irq_info->irq_cookie, 0, 0);
	60	}
	61
	62	static unsigned int sn_startup_irq(unsigned int irq)
	63	{
	64	return 0;
	65	}
	66
	67	static void sn_shutdown_irq(unsigned int irq)
	68	{
	69	}
	70
	71	static void sn_disable_irq(unsigned int irq)
	72	{
	73	}
	74
	75	static void sn_enable_irq(unsigned int irq)
	76	{
	77	}
	78
	79	static void sn_ack_irq(unsigned int irq)
	80	{
2fcc3db0	81	u64 event_occurred, mask;
1da177e4 LT	82
1da177e4 LT	83	irq = irq & 0xff;
2fcc3db0	84	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
be539c73	85	mask = event_occurred & SH_ALL_INT_MASK;
2fcc3db0	86	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
1da177e4 LT	87	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
1da177e4 LT	88
689388bb	89	move_native_irq(irq);
1da177e4 LT	90	}
	91
	92	static void sn_end_irq(unsigned int irq)
	93	{
1da177e4	94	int ivec;
0aa2c72e	95	u64 event_occurred;
1da177e4 LT	96
	97	ivec = irq & 0xff;
	98	if (ivec == SGI_UART_VECTOR) {
0aa2c72e	99	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
cb4cb2cb	100	/* If the UART bit is set here, we may have received an
1da177e4 LT	101	* interrupt from the UART that the driver missed. To
	102	* make sure, we IPI ourselves to force us to look again.
	103	*/
	104	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
	105	platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
	106	IA64_IPI_DM_INT, 0);
	107	}
	108	}
	109	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
	110	if (sn_force_interrupt_flag)
	111	force_interrupt(irq);
	112	}
	113
cb4cb2cb PB	114	static void sn_irq_info_free(struct rcu_head *head);
cb4cb2cb PB	115
83821d3f MM	116	struct sn_irq_info sn_retarget_vector(struct sn_irq_info sn_irq_info,
83821d3f MM	117	nasid_t nasid, int slice)
1da177e4	118	{
83821d3f	119	int vector;
c6957771 JK	120	int cpuid;
c6957771 JK	121	#ifdef CONFIG_SMP
83821d3f	122	int cpuphys;
c6957771	123	#endif
83821d3f MM	124	int64_t bridge;
	125	int local_widget, status;
	126	nasid_t local_nasid;
	127	struct sn_irq_info *new_irq_info;
	128	struct sn_pcibus_provider *pci_provider;
	129
	130	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
	131	if (new_irq_info == NULL)
	132	return NULL;
	133
	134	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
	135
	136	bridge = (u64) new_irq_info->irq_bridge;
	137	if (!bridge) {
	138	kfree(new_irq_info);
	139	return NULL; /* irq is not a device interrupt */
	140	}
1da177e4	141
83821d3f	142	local_nasid = NASID_GET(bridge);
1da177e4	143
83821d3f MM	144	if (local_nasid & 1)
	145	local_widget = TIO_SWIN_WIDGETNUM(bridge);
	146	else
	147	local_widget = SWIN_WIDGETNUM(bridge);
1da177e4	148
83821d3f MM	149	vector = sn_irq_info->irq_irq;
	150	/* Free the old PROM new_irq_info structure */
	151	sn_intr_free(local_nasid, local_widget, new_irq_info);
83821d3f	152	unregister_intr_pda(new_irq_info);
1da177e4	153
83821d3f MM	154	/* allocate a new PROM new_irq_info struct */
	155	status = sn_intr_alloc(local_nasid, local_widget,
	156	new_irq_info, vector,
	157	nasid, slice);
1da177e4	158
83821d3f MM	159	/* SAL call failed */
	160	if (status) {
	161	kfree(new_irq_info);
	162	return NULL;
	163	}
cb4cb2cb	164
c6957771 JK	165	/* Update kernels new_irq_info with new target info */
	166	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
	167	new_irq_info->irq_slice);
	168	new_irq_info->irq_cpuid = cpuid;
83821d3f	169	register_intr_pda(new_irq_info);
1da177e4	170
83821d3f	171	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
cb4cb2cb	172
83821d3f MM	173	/*
	174	* If this represents a line interrupt, target it. If it's
	175	* an msi (irq_int_bit < 0), it's already targeted.
	176	*/
	177	if (new_irq_info->irq_int_bit >= 0 &&
	178	pci_provider && pci_provider->target_interrupt)
	179	(pci_provider->target_interrupt)(new_irq_info);
cb4cb2cb	180
83821d3f MM	181	spin_lock(&sn_irq_info_lock);
	182	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	183	spin_unlock(&sn_irq_info_lock);
	184	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
1da177e4 LT	185
1da177e4 LT	186	#ifdef CONFIG_SMP
c6957771	187	cpuphys = cpu_physical_id(cpuid);
83821d3f	188	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
1da177e4	189	#endif
83821d3f MM	190
	191	return new_irq_info;
	192	}
	193
	194	static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
	195	{
	196	struct sn_irq_info sn_irq_info, sn_irq_info_safe;
	197	nasid_t nasid;
	198	int slice;
	199
	200	nasid = cpuid_to_nasid(first_cpu(mask));
	201	slice = cpuid_to_slice(first_cpu(mask));
	202
	203	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
	204	sn_irq_lh[irq], list)
	205	(void)sn_retarget_vector(sn_irq_info, nasid, slice);
1da177e4 LT	206	}
1da177e4 LT	207
e253eb0c KH	208	static void
	209	sn_mask_irq(unsigned int irq)
	210	{
	211	}
	212
	213	static void
	214	sn_unmask_irq(unsigned int irq)
	215	{
	216	}
	217
	218	struct irq_chip irq_type_sn = {
06344db3	219	.name = "SN hub",
cb4cb2cb PB	220	.startup = sn_startup_irq,
	221	.shutdown = sn_shutdown_irq,
	222	.enable = sn_enable_irq,
	223	.disable = sn_disable_irq,
	224	.ack = sn_ack_irq,
	225	.end = sn_end_irq,
e253eb0c KH	226	.mask = sn_mask_irq,
e253eb0c KH	227	.unmask = sn_unmask_irq,
cb4cb2cb	228	.set_affinity = sn_set_affinity_irq
1da177e4 LT	229	};
	230
	231	unsigned int sn_local_vector_to_irq(u8 vector)
	232	{
	233	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
	234	}
	235
	236	void sn_irq_init(void)
	237	{
	238	int i;
	239	irq_desc_t *base_desc = irq_desc;
	240
10083072 MM	241	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	242	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
	243
1da177e4	244	for (i = 0; i < NR_IRQS; i++) {
d1bef4ed IM	245	if (base_desc[i].chip == &no_irq_type) {
d1bef4ed IM	246	base_desc[i].chip = &irq_type_sn;
1da177e4 LT	247	}
	248	}
	249	}
	250
	251	static void register_intr_pda(struct sn_irq_info *sn_irq_info)
	252	{
	253	int irq = sn_irq_info->irq_irq;
	254	int cpu = sn_irq_info->irq_cpuid;
	255
	256	if (pdacpu(cpu)->sn_last_irq < irq) {
	257	pdacpu(cpu)->sn_last_irq = irq;
	258	}
	259
2fcc3db0	260	if (pdacpu(cpu)->sn_first_irq == 0 \|\| pdacpu(cpu)->sn_first_irq > irq)
1da177e4	261	pdacpu(cpu)->sn_first_irq = irq;
1da177e4 LT	262	}
	263
	264	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
	265	{
	266	int irq = sn_irq_info->irq_irq;
	267	int cpu = sn_irq_info->irq_cpuid;
	268	struct sn_irq_info *tmp_irq_info;
	269	int i, foundmatch;
	270
cb4cb2cb	271	rcu_read_lock();
1da177e4 LT	272	if (pdacpu(cpu)->sn_last_irq == irq) {
1da177e4 LT	273	foundmatch = 0;
cb4cb2cb PB	274	for (i = pdacpu(cpu)->sn_last_irq - 1;
	275	i && !foundmatch; i--) {
	276	list_for_each_entry_rcu(tmp_irq_info,
	277	sn_irq_lh[i],
	278	list) {
1da177e4	279	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	280	foundmatch = 1;
1da177e4 LT	281	break;
1da177e4 LT	282	}
1da177e4 LT	283	}
	284	}
	285	pdacpu(cpu)->sn_last_irq = i;
	286	}
	287
	288	if (pdacpu(cpu)->sn_first_irq == irq) {
	289	foundmatch = 0;
cb4cb2cb PB	290	for (i = pdacpu(cpu)->sn_first_irq + 1;
	291	i < NR_IRQS && !foundmatch; i++) {
	292	list_for_each_entry_rcu(tmp_irq_info,
	293	sn_irq_lh[i],
	294	list) {
1da177e4	295	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	296	foundmatch = 1;
1da177e4 LT	297	break;
1da177e4 LT	298	}
1da177e4 LT	299	}
	300	}
	301	pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	302	}
cb4cb2cb	303	rcu_read_unlock();
1da177e4 LT	304	}
1da177e4 LT	305
cb4cb2cb	306	static void sn_irq_info_free(struct rcu_head *head)
1da177e4 LT	307	{
1da177e4 LT	308	struct sn_irq_info *sn_irq_info;
1da177e4	309
cb4cb2cb	310	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
1da177e4 LT	311	kfree(sn_irq_info);
	312	}
	313
	314	void sn_irq_fixup(struct pci_dev pci_dev, struct sn_irq_info sn_irq_info)
	315	{
	316	nasid_t nasid = sn_irq_info->irq_nasid;
	317	int slice = sn_irq_info->irq_slice;
	318	int cpu = nasid_slice_to_cpuid(nasid, slice);
c6957771 JK	319	#ifdef CONFIG_SMP
	320	int cpuphys;
	321	#endif
1da177e4	322
cb4cb2cb	323	pci_dev_get(pci_dev);
1da177e4 LT	324	sn_irq_info->irq_cpuid = cpu;
	325	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
	326
	327	/* link it into the sn_irq[irq] list */
cb4cb2cb PB	328	spin_lock(&sn_irq_info_lock);
cb4cb2cb PB	329	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
10083072	330	reserve_irq_vector(sn_irq_info->irq_irq);
cb4cb2cb	331	spin_unlock(&sn_irq_info_lock);
1da177e4	332
2fcc3db0	333	register_intr_pda(sn_irq_info);
c6957771 JK	334	#ifdef CONFIG_SMP
	335	cpuphys = cpu_physical_id(cpu);
	336	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
	337	#endif
1da177e4 LT	338	}
1da177e4 LT	339
cb4cb2cb PB	340	void sn_irq_unfixup(struct pci_dev *pci_dev)
	341	{
	342	struct sn_irq_info *sn_irq_info;
	343
	344	/* Only cleanup IRQ stuff if this device has a host bus context */
	345	if (!SN_PCIDEV_BUSSOFT(pci_dev))
	346	return;
	347
	348	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
8b34ff42 PB	349	if (!sn_irq_info)
	350	return;
	351	if (!sn_irq_info->irq_irq) {
6f354b01	352	kfree(sn_irq_info);
cb4cb2cb	353	return;
6f354b01	354	}
cb4cb2cb PB	355
	356	unregister_intr_pda(sn_irq_info);
	357	spin_lock(&sn_irq_info_lock);
	358	list_del_rcu(&sn_irq_info->list);
	359	spin_unlock(&sn_irq_info_lock);
10083072 MM	360	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
10083072 MM	361	free_irq_vector(sn_irq_info->irq_irq);
cb4cb2cb	362	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
cb4cb2cb	363	pci_dev_put(pci_dev);
10083072	364
cb4cb2cb PB	365	}
cb4cb2cb PB	366
735e60f4 MM	367	static inline void
	368	sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
	369	{
	370	struct sn_pcibus_provider *pci_provider;
	371
	372	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
	373	if (pci_provider && pci_provider->force_interrupt)
	374	(*pci_provider->force_interrupt)(sn_irq_info);
	375	}
	376
1da177e4 LT	377	static void force_interrupt(int irq)
	378	{
	379	struct sn_irq_info *sn_irq_info;
	380
	381	if (!sn_ioif_inited)
	382	return;
cb4cb2cb PB	383
cb4cb2cb PB	384	rcu_read_lock();
735e60f4 MM	385	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
	386	sn_call_force_intr_provider(sn_irq_info);
	387
cb4cb2cb	388	rcu_read_unlock();
1da177e4 LT	389	}
	390
	391	/*
	392	* Check for lost interrupts. If the PIC int_status reg. says that
	393	* an interrupt has been sent, but not handled, and the interrupt
	394	* is not pending in either the cpu irr regs or in the soft irr regs,
	395	* and the interrupt is not in service, then the interrupt may have
	396	* been lost. Force an interrupt on that pin. It is possible that
	397	* the interrupt is in flight, so we may generate a spurious interrupt,
	398	* but we should never miss a real lost interrupt.
	399	*/
	400	static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
	401	{
53493dcf	402	u64 regval;
1da177e4 LT	403	struct pcidev_info *pcidev_info;
	404	struct pcibus_info *pcibus_info;
	405
735e60f4 MM	406	/*
	407	* Bridge types attached to TIO (anything but PIC) do not need this WAR
	408	* since they do not target Shub II interrupt registers. If that
	409	* ever changes, this check needs to accomodate.
	410	*/
	411	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
	412	return;
	413
1da177e4 LT	414	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	415	if (!pcidev_info)
	416	return;
	417
	418	pcibus_info =
	419	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	420	pdi_pcibus_info;
	421	regval = pcireg_intr_status_get(pcibus_info);
	422
9a4e5549	423	if (!ia64_get_irr(irq_to_vector(irq))) {
735e60f4 MM	424	if (!test_bit(irq, pda->sn_in_service_ivecs)) {
	425	regval &= 0xff;
	426	if (sn_irq_info->irq_int_bit & regval &
	427	sn_irq_info->irq_last_intr) {
	428	regval &= ~(sn_irq_info->irq_int_bit & regval);
	429	sn_call_force_intr_provider(sn_irq_info);
1da177e4 LT	430	}
	431	}
	432	}
	433	sn_irq_info->irq_last_intr = regval;
	434	}
	435
	436	void sn_lb_int_war_check(void)
	437	{
cb4cb2cb	438	struct sn_irq_info *sn_irq_info;
1da177e4 LT	439	int i;
	440
	441	if (!sn_ioif_inited \|\| pda->sn_first_irq == 0)
	442	return;
cb4cb2cb PB	443
cb4cb2cb PB	444	rcu_read_lock();
1da177e4	445	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
cb4cb2cb	446	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
735e60f4	447	sn_check_intr(i, sn_irq_info);
1da177e4 LT	448	}
1da177e4 LT	449	}
cb4cb2cb PB	450	rcu_read_unlock();
	451	}
	452
2fcc3db0	453	void __init sn_irq_lh_init(void)
cb4cb2cb PB	454	{
	455	int i;
	456
	457	sn_irq_lh = kmalloc(sizeof(struct list_head ) NR_IRQS, GFP_KERNEL);
	458	if (!sn_irq_lh)
	459	panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
	460
	461	for (i = 0; i < NR_IRQS; i++) {
	462	sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
	463	if (!sn_irq_lh[i])
	464	panic("SN PCI INIT: Failed IRQ memory allocation\n");
	465
	466	INIT_LIST_HEAD(sn_irq_lh[i]);
	467	}
1da177e4	468	}