Commit | Line | Data |
---|---|---|
dcc1dd23 JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. | |
7 | * | |
8 | * This file contains macros used to access MMR registers via | |
9 | * uncached physical addresses. | |
10 | * pio_phys_read_mmr - read an MMR | |
11 | * pio_phys_write_mmr - write an MMR | |
12 | * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0 | |
13 | * Second MMR will be skipped if address is NULL | |
14 | * | |
15 | * Addresses passed to these routines should be uncached physical addresses | |
16 | * ie., 0x80000.... | |
17 | */ | |
18 | ||
19 | ||
20 | ||
21 | #include <asm/asmmacro.h> | |
22 | #include <asm/page.h> | |
23 | ||
24 | GLOBAL_ENTRY(pio_phys_read_mmr) | |
25 | .prologue | |
26 | .regstk 1,0,0,0 | |
27 | .body | |
28 | mov r2=psr | |
29 | rsm psr.i | psr.dt | |
30 | ;; | |
31 | srlz.d | |
32 | ld8.acq r8=[r32] | |
33 | ;; | |
34 | mov psr.l=r2;; | |
35 | srlz.d | |
36 | br.ret.sptk.many rp | |
37 | END(pio_phys_read_mmr) | |
38 | ||
39 | GLOBAL_ENTRY(pio_phys_write_mmr) | |
40 | .prologue | |
41 | .regstk 2,0,0,0 | |
42 | .body | |
43 | mov r2=psr | |
44 | rsm psr.i | psr.dt | |
45 | ;; | |
46 | srlz.d | |
47 | st8.rel [r32]=r33 | |
48 | ;; | |
49 | mov psr.l=r2;; | |
50 | srlz.d | |
51 | br.ret.sptk.many rp | |
52 | END(pio_phys_write_mmr) | |
53 | ||
54 | GLOBAL_ENTRY(pio_atomic_phys_write_mmrs) | |
55 | .prologue | |
56 | .regstk 4,0,0,0 | |
57 | .body | |
58 | mov r2=psr | |
59 | cmp.ne p9,p0=r34,r0; | |
60 | rsm psr.i | psr.dt | psr.ic | |
61 | ;; | |
62 | srlz.d | |
63 | st8.rel [r32]=r33 | |
64 | (p9) st8.rel [r34]=r35 | |
65 | ;; | |
66 | mov psr.l=r2;; | |
67 | srlz.d | |
68 | br.ret.sptk.many rp | |
69 | END(pio_atomic_phys_write_mmrs) | |
70 | ||
71 |