Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved. | |
7 | * | |
8 | * Routines for PCI DMA mapping. See Documentation/DMA-API.txt for | |
9 | * a description of how these routines should be used. | |
10 | */ | |
11 | ||
5a0e3ad6 | 12 | #include <linux/gfp.h> |
1da177e4 | 13 | #include <linux/module.h> |
b4391dd1 | 14 | #include <linux/dma-mapping.h> |
1da177e4 | 15 | #include <asm/dma.h> |
83821d3f | 16 | #include <asm/sn/intr.h> |
9b08ebd1 MM |
17 | #include <asm/sn/pcibus_provider_defs.h> |
18 | #include <asm/sn/pcidev.h> | |
c13cf371 | 19 | #include <asm/sn/sn_sal.h> |
1da177e4 | 20 | |
58b053e4 | 21 | #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg))) |
1da177e4 LT |
22 | #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG)) |
23 | ||
24 | /** | |
25 | * sn_dma_supported - test a DMA mask | |
26 | * @dev: device to test | |
27 | * @mask: DMA mask to test | |
28 | * | |
29 | * Return whether the given PCI device DMA address mask can be supported | |
30 | * properly. For example, if your device can only drive the low 24-bits | |
31 | * during PCI bus mastering, then you would pass 0x00ffffff as the mask to | |
32 | * this function. Of course, SN only supports devices that have 32 or more | |
33 | * address bits when using the PMU. | |
34 | */ | |
cdc28d59 | 35 | static int sn_dma_supported(struct device *dev, u64 mask) |
1da177e4 | 36 | { |
c7797d67 | 37 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 LT |
38 | |
39 | if (mask < 0x7fffffff) | |
40 | return 0; | |
41 | return 1; | |
42 | } | |
1da177e4 LT |
43 | |
44 | /** | |
45 | * sn_dma_set_mask - set the DMA mask | |
46 | * @dev: device to set | |
47 | * @dma_mask: new mask | |
48 | * | |
49 | * Set @dev's DMA mask if the hw supports it. | |
50 | */ | |
51 | int sn_dma_set_mask(struct device *dev, u64 dma_mask) | |
52 | { | |
c7797d67 | 53 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 LT |
54 | |
55 | if (!sn_dma_supported(dev, dma_mask)) | |
56 | return 0; | |
57 | ||
58 | *dev->dma_mask = dma_mask; | |
59 | return 1; | |
60 | } | |
61 | EXPORT_SYMBOL(sn_dma_set_mask); | |
62 | ||
63 | /** | |
64 | * sn_dma_alloc_coherent - allocate memory for coherent DMA | |
65 | * @dev: device to allocate for | |
66 | * @size: size of the region | |
67 | * @dma_handle: DMA (bus) address | |
68 | * @flags: memory allocation flags | |
69 | * | |
70 | * dma_alloc_coherent() returns a pointer to a memory region suitable for | |
71 | * coherent DMA traffic to/from a PCI device. On SN platforms, this means | |
72 | * that @dma_handle will have the %PCIIO_DMA_CMD flag set. | |
73 | * | |
74 | * This interface is usually used for "command" streams (e.g. the command | |
75 | * queue for a SCSI controller). See Documentation/DMA-API.txt for | |
76 | * more information. | |
77 | */ | |
cdc28d59 | 78 | static void *sn_dma_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
79 | dma_addr_t * dma_handle, gfp_t flags, |
80 | struct dma_attrs *attrs) | |
1da177e4 LT |
81 | { |
82 | void *cpuaddr; | |
83 | unsigned long phys_addr; | |
7c2a6c62 | 84 | int node; |
e955d825 MM |
85 | struct pci_dev *pdev = to_pci_dev(dev); |
86 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 | 87 | |
c7797d67 | 88 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 LT |
89 | |
90 | /* | |
91 | * Allocate the memory. | |
1da177e4 | 92 | */ |
7c2a6c62 CL |
93 | node = pcibus_to_node(pdev->bus); |
94 | if (likely(node >=0)) { | |
96db800f | 95 | struct page *p = __alloc_pages_node(node, |
6484eb3e | 96 | flags, get_order(size)); |
7c2a6c62 CL |
97 | |
98 | if (likely(p)) | |
99 | cpuaddr = page_address(p); | |
100 | else | |
101 | return NULL; | |
102 | } else | |
dc641613 | 103 | cpuaddr = (void *)__get_free_pages(flags, get_order(size)); |
7c2a6c62 CL |
104 | |
105 | if (unlikely(!cpuaddr)) | |
1da177e4 LT |
106 | return NULL; |
107 | ||
108 | memset(cpuaddr, 0x0, size); | |
109 | ||
110 | /* physical addr. of the memory we just got */ | |
111 | phys_addr = __pa(cpuaddr); | |
112 | ||
113 | /* | |
114 | * 64 bit address translations should never fail. | |
115 | * 32 bit translations can fail if there are insufficient mapping | |
116 | * resources. | |
117 | */ | |
118 | ||
83821d3f MM |
119 | *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size, |
120 | SN_DMA_ADDR_PHYS); | |
1da177e4 | 121 | if (!*dma_handle) { |
d4ed8084 | 122 | printk(KERN_ERR "%s: out of ATEs\n", __func__); |
1da177e4 LT |
123 | free_pages((unsigned long)cpuaddr, get_order(size)); |
124 | return NULL; | |
125 | } | |
126 | ||
127 | return cpuaddr; | |
128 | } | |
1da177e4 LT |
129 | |
130 | /** | |
131 | * sn_pci_free_coherent - free memory associated with coherent DMAable region | |
132 | * @dev: device to free for | |
133 | * @size: size to free | |
134 | * @cpu_addr: kernel virtual address to free | |
135 | * @dma_handle: DMA address associated with this region | |
136 | * | |
137 | * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping | |
138 | * any associated IOMMU mappings. | |
139 | */ | |
cdc28d59 | 140 | static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, |
baa676fc | 141 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
1da177e4 | 142 | { |
e955d825 MM |
143 | struct pci_dev *pdev = to_pci_dev(dev); |
144 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 | 145 | |
c7797d67 | 146 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 147 | |
e955d825 | 148 | provider->dma_unmap(pdev, dma_handle, 0); |
1da177e4 LT |
149 | free_pages((unsigned long)cpu_addr, get_order(size)); |
150 | } | |
1da177e4 LT |
151 | |
152 | /** | |
309df0c5 | 153 | * sn_dma_map_single_attrs - map a single page for DMA |
1da177e4 LT |
154 | * @dev: device to map for |
155 | * @cpu_addr: kernel virtual address of the region to map | |
156 | * @size: size of the region | |
157 | * @direction: DMA direction | |
309df0c5 | 158 | * @attrs: optional dma attributes |
1da177e4 LT |
159 | * |
160 | * Map the region pointed to by @cpu_addr for DMA and return the | |
161 | * DMA address. | |
162 | * | |
163 | * We map this to the one step pcibr_dmamap_trans interface rather than | |
164 | * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have | |
165 | * no way of saving the dmamap handle from the alloc to later free | |
166 | * (which is pretty much unacceptable). | |
167 | * | |
309df0c5 AK |
168 | * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with |
169 | * dma_map_consistent() so that writes force a flush of pending DMA. | |
170 | * (See "SGI Altix Architecture Considerations for Linux Device Drivers", | |
171 | * Document Number: 007-4763-001) | |
172 | * | |
1da177e4 LT |
173 | * TODO: simplify our interface; |
174 | * figure out how to save dmamap handle so can use two step. | |
175 | */ | |
160c1d8e FT |
176 | static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page, |
177 | unsigned long offset, size_t size, | |
178 | enum dma_data_direction dir, | |
179 | struct dma_attrs *attrs) | |
1da177e4 | 180 | { |
160c1d8e | 181 | void *cpu_addr = page_address(page) + offset; |
1da177e4 LT |
182 | dma_addr_t dma_addr; |
183 | unsigned long phys_addr; | |
e955d825 MM |
184 | struct pci_dev *pdev = to_pci_dev(dev); |
185 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
309df0c5 AK |
186 | int dmabarr; |
187 | ||
188 | dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs); | |
1da177e4 | 189 | |
c7797d67 | 190 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 LT |
191 | |
192 | phys_addr = __pa(cpu_addr); | |
309df0c5 AK |
193 | if (dmabarr) |
194 | dma_addr = provider->dma_map_consistent(pdev, phys_addr, | |
195 | size, SN_DMA_ADDR_PHYS); | |
196 | else | |
197 | dma_addr = provider->dma_map(pdev, phys_addr, size, | |
198 | SN_DMA_ADDR_PHYS); | |
199 | ||
1da177e4 | 200 | if (!dma_addr) { |
d4ed8084 | 201 | printk(KERN_ERR "%s: out of ATEs\n", __func__); |
1da177e4 LT |
202 | return 0; |
203 | } | |
204 | return dma_addr; | |
205 | } | |
1da177e4 LT |
206 | |
207 | /** | |
309df0c5 | 208 | * sn_dma_unmap_single_attrs - unamp a DMA mapped page |
1da177e4 LT |
209 | * @dev: device to sync |
210 | * @dma_addr: DMA address to sync | |
211 | * @size: size of region | |
212 | * @direction: DMA direction | |
309df0c5 | 213 | * @attrs: optional dma attributes |
1da177e4 LT |
214 | * |
215 | * This routine is supposed to sync the DMA region specified | |
216 | * by @dma_handle into the coherence domain. On SN, we're always cache | |
217 | * coherent, so we just need to free any ATEs associated with this mapping. | |
218 | */ | |
160c1d8e FT |
219 | static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, |
220 | size_t size, enum dma_data_direction dir, | |
221 | struct dma_attrs *attrs) | |
1da177e4 | 222 | { |
e955d825 MM |
223 | struct pci_dev *pdev = to_pci_dev(dev); |
224 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 | 225 | |
c7797d67 | 226 | BUG_ON(!dev_is_pci(dev)); |
e955d825 | 227 | |
160c1d8e | 228 | provider->dma_unmap(pdev, dma_addr, dir); |
1da177e4 | 229 | } |
1da177e4 LT |
230 | |
231 | /** | |
160c1d8e | 232 | * sn_dma_unmap_sg - unmap a DMA scatterlist |
1da177e4 LT |
233 | * @dev: device to unmap |
234 | * @sg: scatterlist to unmap | |
235 | * @nhwentries: number of scatterlist entries | |
236 | * @direction: DMA direction | |
309df0c5 | 237 | * @attrs: optional dma attributes |
1da177e4 LT |
238 | * |
239 | * Unmap a set of streaming mode DMA translations. | |
240 | */ | |
160c1d8e FT |
241 | static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, |
242 | int nhwentries, enum dma_data_direction dir, | |
243 | struct dma_attrs *attrs) | |
1da177e4 LT |
244 | { |
245 | int i; | |
e955d825 MM |
246 | struct pci_dev *pdev = to_pci_dev(dev); |
247 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
9b6eccfc | 248 | struct scatterlist *sg; |
1da177e4 | 249 | |
c7797d67 | 250 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 251 | |
9b6eccfc | 252 | for_each_sg(sgl, sg, nhwentries, i) { |
160c1d8e | 253 | provider->dma_unmap(pdev, sg->dma_address, dir); |
1da177e4 LT |
254 | sg->dma_address = (dma_addr_t) NULL; |
255 | sg->dma_length = 0; | |
256 | } | |
257 | } | |
1da177e4 LT |
258 | |
259 | /** | |
160c1d8e | 260 | * sn_dma_map_sg - map a scatterlist for DMA |
1da177e4 LT |
261 | * @dev: device to map for |
262 | * @sg: scatterlist to map | |
263 | * @nhwentries: number of entries | |
264 | * @direction: direction of the DMA transaction | |
309df0c5 AK |
265 | * @attrs: optional dma attributes |
266 | * | |
267 | * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with | |
268 | * dma_map_consistent() so that writes force a flush of pending DMA. | |
269 | * (See "SGI Altix Architecture Considerations for Linux Device Drivers", | |
270 | * Document Number: 007-4763-001) | |
1da177e4 LT |
271 | * |
272 | * Maps each entry of @sg for DMA. | |
273 | */ | |
160c1d8e FT |
274 | static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl, |
275 | int nhwentries, enum dma_data_direction dir, | |
276 | struct dma_attrs *attrs) | |
1da177e4 LT |
277 | { |
278 | unsigned long phys_addr; | |
9b6eccfc | 279 | struct scatterlist *saved_sg = sgl, *sg; |
e955d825 MM |
280 | struct pci_dev *pdev = to_pci_dev(dev); |
281 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 | 282 | int i; |
309df0c5 AK |
283 | int dmabarr; |
284 | ||
285 | dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs); | |
1da177e4 | 286 | |
c7797d67 | 287 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 LT |
288 | |
289 | /* | |
290 | * Setup a DMA address for each entry in the scatterlist. | |
291 | */ | |
9b6eccfc | 292 | for_each_sg(sgl, sg, nhwentries, i) { |
309df0c5 | 293 | dma_addr_t dma_addr; |
1da177e4 | 294 | phys_addr = SG_ENT_PHYS_ADDRESS(sg); |
309df0c5 AK |
295 | if (dmabarr) |
296 | dma_addr = provider->dma_map_consistent(pdev, | |
297 | phys_addr, | |
298 | sg->length, | |
299 | SN_DMA_ADDR_PHYS); | |
300 | else | |
301 | dma_addr = provider->dma_map(pdev, phys_addr, | |
302 | sg->length, | |
303 | SN_DMA_ADDR_PHYS); | |
1da177e4 | 304 | |
309df0c5 | 305 | sg->dma_address = dma_addr; |
1da177e4 | 306 | if (!sg->dma_address) { |
d4ed8084 | 307 | printk(KERN_ERR "%s: out of ATEs\n", __func__); |
1da177e4 LT |
308 | |
309 | /* | |
310 | * Free any successfully allocated entries. | |
311 | */ | |
312 | if (i > 0) | |
160c1d8e | 313 | sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs); |
1da177e4 LT |
314 | return 0; |
315 | } | |
316 | ||
317 | sg->dma_length = sg->length; | |
318 | } | |
319 | ||
320 | return nhwentries; | |
321 | } | |
1da177e4 | 322 | |
cdc28d59 | 323 | static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, |
160c1d8e | 324 | size_t size, enum dma_data_direction dir) |
1da177e4 | 325 | { |
c7797d67 | 326 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 327 | } |
1da177e4 | 328 | |
cdc28d59 | 329 | static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, |
160c1d8e FT |
330 | size_t size, |
331 | enum dma_data_direction dir) | |
1da177e4 | 332 | { |
c7797d67 | 333 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 334 | } |
1da177e4 | 335 | |
cdc28d59 | 336 | static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
160c1d8e | 337 | int nelems, enum dma_data_direction dir) |
1da177e4 | 338 | { |
c7797d67 | 339 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 340 | } |
1da177e4 | 341 | |
cdc28d59 | 342 | static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
160c1d8e | 343 | int nelems, enum dma_data_direction dir) |
1da177e4 | 344 | { |
c7797d67 | 345 | BUG_ON(!dev_is_pci(dev)); |
1da177e4 | 346 | } |
1da177e4 | 347 | |
cdc28d59 | 348 | static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
1da177e4 LT |
349 | { |
350 | return 0; | |
351 | } | |
1da177e4 | 352 | |
175add19 JK |
353 | u64 sn_dma_get_required_mask(struct device *dev) |
354 | { | |
6a35528a | 355 | return DMA_BIT_MASK(64); |
175add19 JK |
356 | } |
357 | EXPORT_SYMBOL_GPL(sn_dma_get_required_mask); | |
358 | ||
1da177e4 LT |
359 | char *sn_pci_get_legacy_mem(struct pci_bus *bus) |
360 | { | |
361 | if (!SN_PCIBUS_BUSSOFT(bus)) | |
362 | return ERR_PTR(-ENODEV); | |
363 | ||
364 | return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET); | |
365 | } | |
366 | ||
367 | int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
368 | { | |
369 | unsigned long addr; | |
370 | int ret; | |
61b9cf7c MM |
371 | struct ia64_sal_retval isrv; |
372 | ||
373 | /* | |
374 | * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work | |
375 | * around hw issues at the pci bus level. SGI proms older than | |
72fdbdce | 376 | * 4.10 don't implement this. |
61b9cf7c MM |
377 | */ |
378 | ||
379 | SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE, | |
8ed9b2c7 JS |
380 | pci_domain_nr(bus), bus->number, |
381 | 0, /* io */ | |
382 | 0, /* read */ | |
383 | port, size, __pa(val)); | |
61b9cf7c MM |
384 | |
385 | if (isrv.status == 0) | |
386 | return size; | |
387 | ||
388 | /* | |
389 | * If the above failed, retry using the SAL_PROBE call which should | |
390 | * be present in all proms (but which cannot work round PCI chipset | |
72fdbdce | 391 | * bugs). This code is retained for compatibility with old |
61b9cf7c MM |
392 | * pre-4.10 proms, and should be removed at some point in the future. |
393 | */ | |
1da177e4 LT |
394 | |
395 | if (!SN_PCIBUS_BUSSOFT(bus)) | |
396 | return -ENODEV; | |
397 | ||
398 | addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET; | |
399 | addr += port; | |
400 | ||
401 | ret = ia64_sn_probe_mem(addr, (long)size, (void *)val); | |
402 | ||
403 | if (ret == 2) | |
404 | return -EINVAL; | |
405 | ||
406 | if (ret == 1) | |
407 | *val = -1; | |
408 | ||
409 | return size; | |
410 | } | |
411 | ||
412 | int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) | |
413 | { | |
414 | int ret = size; | |
415 | unsigned long paddr; | |
416 | unsigned long *addr; | |
61b9cf7c MM |
417 | struct ia64_sal_retval isrv; |
418 | ||
419 | /* | |
420 | * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work | |
421 | * around hw issues at the pci bus level. SGI proms older than | |
72fdbdce | 422 | * 4.10 don't implement this. |
61b9cf7c MM |
423 | */ |
424 | ||
425 | SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE, | |
8ed9b2c7 JS |
426 | pci_domain_nr(bus), bus->number, |
427 | 0, /* io */ | |
428 | 1, /* write */ | |
429 | port, size, __pa(&val)); | |
61b9cf7c MM |
430 | |
431 | if (isrv.status == 0) | |
432 | return size; | |
433 | ||
434 | /* | |
435 | * If the above failed, retry using the SAL_PROBE call which should | |
436 | * be present in all proms (but which cannot work round PCI chipset | |
72fdbdce | 437 | * bugs). This code is retained for compatibility with old |
61b9cf7c MM |
438 | * pre-4.10 proms, and should be removed at some point in the future. |
439 | */ | |
1da177e4 LT |
440 | |
441 | if (!SN_PCIBUS_BUSSOFT(bus)) { | |
442 | ret = -ENODEV; | |
443 | goto out; | |
444 | } | |
445 | ||
446 | /* Put the phys addr in uncached space */ | |
447 | paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET; | |
448 | paddr += port; | |
449 | addr = (unsigned long *)paddr; | |
450 | ||
451 | switch (size) { | |
452 | case 1: | |
453 | *(volatile u8 *)(addr) = (u8)(val); | |
454 | break; | |
455 | case 2: | |
456 | *(volatile u16 *)(addr) = (u16)(val); | |
457 | break; | |
458 | case 4: | |
459 | *(volatile u32 *)(addr) = (u32)(val); | |
460 | break; | |
461 | default: | |
462 | ret = -EINVAL; | |
463 | break; | |
464 | } | |
465 | out: | |
466 | return ret; | |
467 | } | |
b4391dd1 | 468 | |
160c1d8e | 469 | static struct dma_map_ops sn_dma_ops = { |
baa676fc AP |
470 | .alloc = sn_dma_alloc_coherent, |
471 | .free = sn_dma_free_coherent, | |
160c1d8e FT |
472 | .map_page = sn_dma_map_page, |
473 | .unmap_page = sn_dma_unmap_page, | |
474 | .map_sg = sn_dma_map_sg, | |
475 | .unmap_sg = sn_dma_unmap_sg, | |
b4391dd1 FT |
476 | .sync_single_for_cpu = sn_dma_sync_single_for_cpu, |
477 | .sync_sg_for_cpu = sn_dma_sync_sg_for_cpu, | |
478 | .sync_single_for_device = sn_dma_sync_single_for_device, | |
479 | .sync_sg_for_device = sn_dma_sync_sg_for_device, | |
480 | .mapping_error = sn_dma_mapping_error, | |
160c1d8e | 481 | .dma_supported = sn_dma_supported, |
b4391dd1 | 482 | }; |
4d9b977c FT |
483 | |
484 | void sn_dma_init(void) | |
485 | { | |
486 | dma_ops = &sn_dma_ops; | |
487 | } |