Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved. | |
7 | * | |
8 | * Routines for PCI DMA mapping. See Documentation/DMA-API.txt for | |
9 | * a description of how these routines should be used. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <asm/dma.h> | |
83821d3f | 14 | #include <asm/sn/intr.h> |
9b08ebd1 MM |
15 | #include <asm/sn/pcibus_provider_defs.h> |
16 | #include <asm/sn/pcidev.h> | |
c13cf371 | 17 | #include <asm/sn/sn_sal.h> |
1da177e4 LT |
18 | |
19 | #define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset) | |
20 | #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG)) | |
21 | ||
22 | /** | |
23 | * sn_dma_supported - test a DMA mask | |
24 | * @dev: device to test | |
25 | * @mask: DMA mask to test | |
26 | * | |
27 | * Return whether the given PCI device DMA address mask can be supported | |
28 | * properly. For example, if your device can only drive the low 24-bits | |
29 | * during PCI bus mastering, then you would pass 0x00ffffff as the mask to | |
30 | * this function. Of course, SN only supports devices that have 32 or more | |
31 | * address bits when using the PMU. | |
32 | */ | |
33 | int sn_dma_supported(struct device *dev, u64 mask) | |
34 | { | |
35 | BUG_ON(dev->bus != &pci_bus_type); | |
36 | ||
37 | if (mask < 0x7fffffff) | |
38 | return 0; | |
39 | return 1; | |
40 | } | |
41 | EXPORT_SYMBOL(sn_dma_supported); | |
42 | ||
43 | /** | |
44 | * sn_dma_set_mask - set the DMA mask | |
45 | * @dev: device to set | |
46 | * @dma_mask: new mask | |
47 | * | |
48 | * Set @dev's DMA mask if the hw supports it. | |
49 | */ | |
50 | int sn_dma_set_mask(struct device *dev, u64 dma_mask) | |
51 | { | |
52 | BUG_ON(dev->bus != &pci_bus_type); | |
53 | ||
54 | if (!sn_dma_supported(dev, dma_mask)) | |
55 | return 0; | |
56 | ||
57 | *dev->dma_mask = dma_mask; | |
58 | return 1; | |
59 | } | |
60 | EXPORT_SYMBOL(sn_dma_set_mask); | |
61 | ||
62 | /** | |
63 | * sn_dma_alloc_coherent - allocate memory for coherent DMA | |
64 | * @dev: device to allocate for | |
65 | * @size: size of the region | |
66 | * @dma_handle: DMA (bus) address | |
67 | * @flags: memory allocation flags | |
68 | * | |
69 | * dma_alloc_coherent() returns a pointer to a memory region suitable for | |
70 | * coherent DMA traffic to/from a PCI device. On SN platforms, this means | |
71 | * that @dma_handle will have the %PCIIO_DMA_CMD flag set. | |
72 | * | |
73 | * This interface is usually used for "command" streams (e.g. the command | |
74 | * queue for a SCSI controller). See Documentation/DMA-API.txt for | |
75 | * more information. | |
76 | */ | |
77 | void *sn_dma_alloc_coherent(struct device *dev, size_t size, | |
06a54497 | 78 | dma_addr_t * dma_handle, gfp_t flags) |
1da177e4 LT |
79 | { |
80 | void *cpuaddr; | |
81 | unsigned long phys_addr; | |
7c2a6c62 | 82 | int node; |
e955d825 MM |
83 | struct pci_dev *pdev = to_pci_dev(dev); |
84 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 LT |
85 | |
86 | BUG_ON(dev->bus != &pci_bus_type); | |
87 | ||
88 | /* | |
89 | * Allocate the memory. | |
1da177e4 | 90 | */ |
7c2a6c62 CL |
91 | node = pcibus_to_node(pdev->bus); |
92 | if (likely(node >=0)) { | |
dc641613 | 93 | struct page *p = alloc_pages_node(node, flags, get_order(size)); |
7c2a6c62 CL |
94 | |
95 | if (likely(p)) | |
96 | cpuaddr = page_address(p); | |
97 | else | |
98 | return NULL; | |
99 | } else | |
dc641613 | 100 | cpuaddr = (void *)__get_free_pages(flags, get_order(size)); |
7c2a6c62 CL |
101 | |
102 | if (unlikely(!cpuaddr)) | |
1da177e4 LT |
103 | return NULL; |
104 | ||
105 | memset(cpuaddr, 0x0, size); | |
106 | ||
107 | /* physical addr. of the memory we just got */ | |
108 | phys_addr = __pa(cpuaddr); | |
109 | ||
110 | /* | |
111 | * 64 bit address translations should never fail. | |
112 | * 32 bit translations can fail if there are insufficient mapping | |
113 | * resources. | |
114 | */ | |
115 | ||
83821d3f MM |
116 | *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size, |
117 | SN_DMA_ADDR_PHYS); | |
1da177e4 LT |
118 | if (!*dma_handle) { |
119 | printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); | |
120 | free_pages((unsigned long)cpuaddr, get_order(size)); | |
121 | return NULL; | |
122 | } | |
123 | ||
124 | return cpuaddr; | |
125 | } | |
126 | EXPORT_SYMBOL(sn_dma_alloc_coherent); | |
127 | ||
128 | /** | |
129 | * sn_pci_free_coherent - free memory associated with coherent DMAable region | |
130 | * @dev: device to free for | |
131 | * @size: size to free | |
132 | * @cpu_addr: kernel virtual address to free | |
133 | * @dma_handle: DMA address associated with this region | |
134 | * | |
135 | * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping | |
136 | * any associated IOMMU mappings. | |
137 | */ | |
138 | void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, | |
139 | dma_addr_t dma_handle) | |
140 | { | |
e955d825 MM |
141 | struct pci_dev *pdev = to_pci_dev(dev); |
142 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 LT |
143 | |
144 | BUG_ON(dev->bus != &pci_bus_type); | |
145 | ||
e955d825 | 146 | provider->dma_unmap(pdev, dma_handle, 0); |
1da177e4 LT |
147 | free_pages((unsigned long)cpu_addr, get_order(size)); |
148 | } | |
149 | EXPORT_SYMBOL(sn_dma_free_coherent); | |
150 | ||
151 | /** | |
152 | * sn_dma_map_single - map a single page for DMA | |
153 | * @dev: device to map for | |
154 | * @cpu_addr: kernel virtual address of the region to map | |
155 | * @size: size of the region | |
156 | * @direction: DMA direction | |
157 | * | |
158 | * Map the region pointed to by @cpu_addr for DMA and return the | |
159 | * DMA address. | |
160 | * | |
161 | * We map this to the one step pcibr_dmamap_trans interface rather than | |
162 | * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have | |
163 | * no way of saving the dmamap handle from the alloc to later free | |
164 | * (which is pretty much unacceptable). | |
165 | * | |
166 | * TODO: simplify our interface; | |
167 | * figure out how to save dmamap handle so can use two step. | |
168 | */ | |
169 | dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size, | |
170 | int direction) | |
171 | { | |
172 | dma_addr_t dma_addr; | |
173 | unsigned long phys_addr; | |
e955d825 MM |
174 | struct pci_dev *pdev = to_pci_dev(dev); |
175 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 LT |
176 | |
177 | BUG_ON(dev->bus != &pci_bus_type); | |
178 | ||
179 | phys_addr = __pa(cpu_addr); | |
83821d3f | 180 | dma_addr = provider->dma_map(pdev, phys_addr, size, SN_DMA_ADDR_PHYS); |
1da177e4 LT |
181 | if (!dma_addr) { |
182 | printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); | |
183 | return 0; | |
184 | } | |
185 | return dma_addr; | |
186 | } | |
187 | EXPORT_SYMBOL(sn_dma_map_single); | |
188 | ||
189 | /** | |
190 | * sn_dma_unmap_single - unamp a DMA mapped page | |
191 | * @dev: device to sync | |
192 | * @dma_addr: DMA address to sync | |
193 | * @size: size of region | |
194 | * @direction: DMA direction | |
195 | * | |
196 | * This routine is supposed to sync the DMA region specified | |
197 | * by @dma_handle into the coherence domain. On SN, we're always cache | |
198 | * coherent, so we just need to free any ATEs associated with this mapping. | |
199 | */ | |
200 | void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | |
201 | int direction) | |
202 | { | |
e955d825 MM |
203 | struct pci_dev *pdev = to_pci_dev(dev); |
204 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 LT |
205 | |
206 | BUG_ON(dev->bus != &pci_bus_type); | |
e955d825 MM |
207 | |
208 | provider->dma_unmap(pdev, dma_addr, direction); | |
1da177e4 LT |
209 | } |
210 | EXPORT_SYMBOL(sn_dma_unmap_single); | |
211 | ||
212 | /** | |
213 | * sn_dma_unmap_sg - unmap a DMA scatterlist | |
214 | * @dev: device to unmap | |
215 | * @sg: scatterlist to unmap | |
216 | * @nhwentries: number of scatterlist entries | |
217 | * @direction: DMA direction | |
218 | * | |
219 | * Unmap a set of streaming mode DMA translations. | |
220 | */ | |
9b6eccfc | 221 | void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, |
1da177e4 LT |
222 | int nhwentries, int direction) |
223 | { | |
224 | int i; | |
e955d825 MM |
225 | struct pci_dev *pdev = to_pci_dev(dev); |
226 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
9b6eccfc | 227 | struct scatterlist *sg; |
1da177e4 LT |
228 | |
229 | BUG_ON(dev->bus != &pci_bus_type); | |
230 | ||
9b6eccfc | 231 | for_each_sg(sgl, sg, nhwentries, i) { |
e955d825 | 232 | provider->dma_unmap(pdev, sg->dma_address, direction); |
1da177e4 LT |
233 | sg->dma_address = (dma_addr_t) NULL; |
234 | sg->dma_length = 0; | |
235 | } | |
236 | } | |
237 | EXPORT_SYMBOL(sn_dma_unmap_sg); | |
238 | ||
239 | /** | |
240 | * sn_dma_map_sg - map a scatterlist for DMA | |
241 | * @dev: device to map for | |
242 | * @sg: scatterlist to map | |
243 | * @nhwentries: number of entries | |
244 | * @direction: direction of the DMA transaction | |
245 | * | |
246 | * Maps each entry of @sg for DMA. | |
247 | */ | |
9b6eccfc | 248 | int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl, int nhwentries, |
1da177e4 LT |
249 | int direction) |
250 | { | |
251 | unsigned long phys_addr; | |
9b6eccfc | 252 | struct scatterlist *saved_sg = sgl, *sg; |
e955d825 MM |
253 | struct pci_dev *pdev = to_pci_dev(dev); |
254 | struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); | |
1da177e4 LT |
255 | int i; |
256 | ||
257 | BUG_ON(dev->bus != &pci_bus_type); | |
258 | ||
259 | /* | |
260 | * Setup a DMA address for each entry in the scatterlist. | |
261 | */ | |
9b6eccfc | 262 | for_each_sg(sgl, sg, nhwentries, i) { |
1da177e4 | 263 | phys_addr = SG_ENT_PHYS_ADDRESS(sg); |
e955d825 | 264 | sg->dma_address = provider->dma_map(pdev, |
83821d3f MM |
265 | phys_addr, sg->length, |
266 | SN_DMA_ADDR_PHYS); | |
1da177e4 LT |
267 | |
268 | if (!sg->dma_address) { | |
269 | printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); | |
270 | ||
271 | /* | |
272 | * Free any successfully allocated entries. | |
273 | */ | |
274 | if (i > 0) | |
275 | sn_dma_unmap_sg(dev, saved_sg, i, direction); | |
276 | return 0; | |
277 | } | |
278 | ||
279 | sg->dma_length = sg->length; | |
280 | } | |
281 | ||
282 | return nhwentries; | |
283 | } | |
284 | EXPORT_SYMBOL(sn_dma_map_sg); | |
285 | ||
286 | void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, | |
287 | size_t size, int direction) | |
288 | { | |
289 | BUG_ON(dev->bus != &pci_bus_type); | |
290 | } | |
291 | EXPORT_SYMBOL(sn_dma_sync_single_for_cpu); | |
292 | ||
293 | void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, | |
294 | size_t size, int direction) | |
295 | { | |
296 | BUG_ON(dev->bus != &pci_bus_type); | |
297 | } | |
298 | EXPORT_SYMBOL(sn_dma_sync_single_for_device); | |
299 | ||
300 | void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
301 | int nelems, int direction) | |
302 | { | |
303 | BUG_ON(dev->bus != &pci_bus_type); | |
304 | } | |
305 | EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu); | |
306 | ||
307 | void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
308 | int nelems, int direction) | |
309 | { | |
310 | BUG_ON(dev->bus != &pci_bus_type); | |
311 | } | |
312 | EXPORT_SYMBOL(sn_dma_sync_sg_for_device); | |
313 | ||
314 | int sn_dma_mapping_error(dma_addr_t dma_addr) | |
315 | { | |
316 | return 0; | |
317 | } | |
318 | EXPORT_SYMBOL(sn_dma_mapping_error); | |
319 | ||
320 | char *sn_pci_get_legacy_mem(struct pci_bus *bus) | |
321 | { | |
322 | if (!SN_PCIBUS_BUSSOFT(bus)) | |
323 | return ERR_PTR(-ENODEV); | |
324 | ||
325 | return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET); | |
326 | } | |
327 | ||
328 | int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
329 | { | |
330 | unsigned long addr; | |
331 | int ret; | |
61b9cf7c MM |
332 | struct ia64_sal_retval isrv; |
333 | ||
334 | /* | |
335 | * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work | |
336 | * around hw issues at the pci bus level. SGI proms older than | |
72fdbdce | 337 | * 4.10 don't implement this. |
61b9cf7c MM |
338 | */ |
339 | ||
340 | SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE, | |
8ed9b2c7 JS |
341 | pci_domain_nr(bus), bus->number, |
342 | 0, /* io */ | |
343 | 0, /* read */ | |
344 | port, size, __pa(val)); | |
61b9cf7c MM |
345 | |
346 | if (isrv.status == 0) | |
347 | return size; | |
348 | ||
349 | /* | |
350 | * If the above failed, retry using the SAL_PROBE call which should | |
351 | * be present in all proms (but which cannot work round PCI chipset | |
72fdbdce | 352 | * bugs). This code is retained for compatibility with old |
61b9cf7c MM |
353 | * pre-4.10 proms, and should be removed at some point in the future. |
354 | */ | |
1da177e4 LT |
355 | |
356 | if (!SN_PCIBUS_BUSSOFT(bus)) | |
357 | return -ENODEV; | |
358 | ||
359 | addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET; | |
360 | addr += port; | |
361 | ||
362 | ret = ia64_sn_probe_mem(addr, (long)size, (void *)val); | |
363 | ||
364 | if (ret == 2) | |
365 | return -EINVAL; | |
366 | ||
367 | if (ret == 1) | |
368 | *val = -1; | |
369 | ||
370 | return size; | |
371 | } | |
372 | ||
373 | int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) | |
374 | { | |
375 | int ret = size; | |
376 | unsigned long paddr; | |
377 | unsigned long *addr; | |
61b9cf7c MM |
378 | struct ia64_sal_retval isrv; |
379 | ||
380 | /* | |
381 | * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work | |
382 | * around hw issues at the pci bus level. SGI proms older than | |
72fdbdce | 383 | * 4.10 don't implement this. |
61b9cf7c MM |
384 | */ |
385 | ||
386 | SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE, | |
8ed9b2c7 JS |
387 | pci_domain_nr(bus), bus->number, |
388 | 0, /* io */ | |
389 | 1, /* write */ | |
390 | port, size, __pa(&val)); | |
61b9cf7c MM |
391 | |
392 | if (isrv.status == 0) | |
393 | return size; | |
394 | ||
395 | /* | |
396 | * If the above failed, retry using the SAL_PROBE call which should | |
397 | * be present in all proms (but which cannot work round PCI chipset | |
72fdbdce | 398 | * bugs). This code is retained for compatibility with old |
61b9cf7c MM |
399 | * pre-4.10 proms, and should be removed at some point in the future. |
400 | */ | |
1da177e4 LT |
401 | |
402 | if (!SN_PCIBUS_BUSSOFT(bus)) { | |
403 | ret = -ENODEV; | |
404 | goto out; | |
405 | } | |
406 | ||
407 | /* Put the phys addr in uncached space */ | |
408 | paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET; | |
409 | paddr += port; | |
410 | addr = (unsigned long *)paddr; | |
411 | ||
412 | switch (size) { | |
413 | case 1: | |
414 | *(volatile u8 *)(addr) = (u8)(val); | |
415 | break; | |
416 | case 2: | |
417 | *(volatile u16 *)(addr) = (u16)(val); | |
418 | break; | |
419 | case 4: | |
420 | *(volatile u32 *)(addr) = (u32)(val); | |
421 | break; | |
422 | default: | |
423 | ret = -EINVAL; | |
424 | break; | |
425 | } | |
426 | out: | |
427 | return ret; | |
428 | } |