projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| fabb626a HT |
1 | #ifndef _OPSPUT_OPSPUT_PLD_H |
| 2 | #define _OPSPUT_OPSPUT_PLD_H | |
| 3 | ||
| 1da177e4 | 4 | /* |
| f30c2269 | 5 | * include/asm-m32r/opsput/opsput_pld.h |
| 1da177e4 LT |
6 | * |
| 7 | * Definitions for Programable Logic Device(PLD) on OPSPUT board. | |
| 8 | * | |
| 9 | * Copyright (c) 2002 Takeo Takahashi | |
| 10 | * | |
| 11 | * This file is subject to the terms and conditions of the GNU General | |
| 12 | * Public License. See the file "COPYING" in the main directory of | |
| 13 | * this archive for more details. | |
| 1da177e4 LT |
14 | */ |
| 15 | ||
| 1da177e4 LT |
16 | #define PLD_PLAT_BASE 0x1cc00000 |
| 17 | ||
| 18 | #ifndef __ASSEMBLY__ | |
| 19 | /* | |
| 20 | * C functions use non-cache address. | |
| 21 | */ | |
| 22 | #define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */) | |
| 23 | #define __reg8 (volatile unsigned char *) | |
| 24 | #define __reg16 (volatile unsigned short *) | |
| 25 | #define __reg32 (volatile unsigned int *) | |
| 26 | #else | |
| 27 | #define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET) | |
| 28 | #define __reg8 | |
| 29 | #define __reg16 | |
| 30 | #define __reg32 | |
| fabb626a | 31 | #endif /* __ASSEMBLY__ */ |
| 1da177e4 LT |
32 | |
| 33 | /* CFC */ | |
| 34 | #define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000) | |
| 35 | #define PLD_CFSTS __reg16(PLD_BASE + 0x0002) | |
| 36 | #define PLD_CFIMASK __reg16(PLD_BASE + 0x0004) | |
| 37 | #define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006) | |
| 38 | #define PLD_CFVENCR __reg16(PLD_BASE + 0x0008) | |
| 39 | #define PLD_CFCR0 __reg16(PLD_BASE + 0x000a) | |
| 40 | #define PLD_CFCR1 __reg16(PLD_BASE + 0x000c) | |
| 41 | #define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010) | |
| 42 | ||
| 43 | /* MMC */ | |
| 44 | #define PLD_MMCCR __reg16(PLD_BASE + 0x4000) | |
| 45 | #define PLD_MMCMOD __reg16(PLD_BASE + 0x4002) | |
| 46 | #define PLD_MMCSTS __reg16(PLD_BASE + 0x4006) | |
| 47 | #define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a) | |
| 48 | #define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c) | |
| 49 | #define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e) | |
| 50 | #define PLD_MMCDET __reg16(PLD_BASE + 0x4010) | |
| 51 | #define PLD_MMCWP __reg16(PLD_BASE + 0x4012) | |
| 52 | #define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000) | |
| 53 | #define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000) | |
| 54 | #define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000) | |
| 55 | #define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006) | |
| 56 | ||
| 57 | /* ICU | |
| 58 | * ICUISTS: status register | |
| 59 | * ICUIREQ0: request register | |
| 60 | * ICUIREQ1: request register | |
| 61 | * ICUCR3: control register for CFIREQ# interrupt | |
| 62 | * ICUCR4: control register for CFC Card insert interrupt | |
| 63 | * ICUCR5: control register for CFC Card eject interrupt | |
| 64 | * ICUCR6: control register for external interrupt | |
| 65 | * ICUCR11: control register for MMC Card insert/eject interrupt | |
| 66 | * ICUCR13: control register for SC error interrupt | |
| 67 | * ICUCR14: control register for SC receive interrupt | |
| 68 | * ICUCR15: control register for SC send interrupt | |
| 69 | * ICUCR16: control register for SIO0 receive interrupt | |
| 70 | * ICUCR17: control register for SIO0 send interrupt | |
| 71 | */ | |
| 72 | #if !defined(CONFIG_PLAT_USRV) | |
| 73 | #define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */ | |
| 74 | #define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */ | |
| 75 | #define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */ | |
| 76 | #define PLD_IRQ_CFIREQ (OPSPUT_PLD_IRQ_BASE + 3) /* CF IREQ */ | |
| 77 | #define PLD_IRQ_CFC_INSERT (OPSPUT_PLD_IRQ_BASE + 4) /* CF Insert */ | |
| 78 | #define PLD_IRQ_CFC_EJECT (OPSPUT_PLD_IRQ_BASE + 5) /* CF Eject */ | |
| 79 | #define PLD_IRQ_EXINT (OPSPUT_PLD_IRQ_BASE + 6) /* EXINT */ | |
| 80 | #define PLD_IRQ_INT7 (OPSPUT_PLD_IRQ_BASE + 7) /* reserved */ | |
| 81 | #define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */ | |
| 82 | #define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */ | |
| 83 | #define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */ | |
| 84 | #define PLD_IRQ_MMCCARD (OPSPUT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */ | |
| 85 | #define PLD_IRQ_INT12 (OPSPUT_PLD_IRQ_BASE + 12) /* reserved */ | |
| 86 | #define PLD_IRQ_SC_ERROR (OPSPUT_PLD_IRQ_BASE + 13) /* SC error */ | |
| 87 | #define PLD_IRQ_SC_RCV (OPSPUT_PLD_IRQ_BASE + 14) /* SC receive */ | |
| 88 | #define PLD_IRQ_SC_SND (OPSPUT_PLD_IRQ_BASE + 15) /* SC send */ | |
| 89 | #define PLD_IRQ_SIO0_RCV (OPSPUT_PLD_IRQ_BASE + 16) /* SIO receive */ | |
| 90 | #define PLD_IRQ_SIO0_SND (OPSPUT_PLD_IRQ_BASE + 17) /* SIO send */ | |
| 91 | #define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */ | |
| 92 | #define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */ | |
| 93 | #define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */ | |
| 94 | #define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */ | |
| 95 | #define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */ | |
| 96 | #define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */ | |
| 97 | #define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */ | |
| 98 | #define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */ | |
| 99 | #define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */ | |
| 100 | #define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */ | |
| 101 | #define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */ | |
| 102 | #define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */ | |
| 103 | #define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */ | |
| 104 | #define PLD_IRQ_INT31 (OPSPUT_PLD_IRQ_BASE + 31) /* reserved */ | |
| 105 | ||
| 106 | #else /* CONFIG_PLAT_USRV */ | |
| 107 | ||
| 108 | #define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */ | |
| 109 | #define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */ | |
| 110 | #define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */ | |
| 111 | #define PLD_IRQ_CF0 (OPSPUT_PLD_IRQ_BASE + 3) /* CF0# */ | |
| 112 | #define PLD_IRQ_CF1 (OPSPUT_PLD_IRQ_BASE + 4) /* CF1# */ | |
| 113 | #define PLD_IRQ_CF2 (OPSPUT_PLD_IRQ_BASE + 5) /* CF2# */ | |
| 114 | #define PLD_IRQ_CF3 (OPSPUT_PLD_IRQ_BASE + 6) /* CF3# */ | |
| 115 | #define PLD_IRQ_CF4 (OPSPUT_PLD_IRQ_BASE + 7) /* CF4# */ | |
| 116 | #define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */ | |
| 117 | #define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */ | |
| 118 | #define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */ | |
| 119 | #define PLD_IRQ_INT11 (OPSPUT_PLD_IRQ_BASE + 11) /* reserved */ | |
| 120 | #define PLD_IRQ_UART0 (OPSPUT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */ | |
| 121 | #define PLD_IRQ_UART1 (OPSPUT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */ | |
| 122 | #define PLD_IRQ_INT14 (OPSPUT_PLD_IRQ_BASE + 14) /* reserved */ | |
| 123 | #define PLD_IRQ_INT15 (OPSPUT_PLD_IRQ_BASE + 15) /* reserved */ | |
| 124 | #define PLD_IRQ_SNDINT (OPSPUT_PLD_IRQ_BASE + 16) /* SNDINT# */ | |
| 125 | #define PLD_IRQ_INT17 (OPSPUT_PLD_IRQ_BASE + 17) /* reserved */ | |
| 126 | #define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */ | |
| 127 | #define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */ | |
| 128 | #define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */ | |
| 129 | #define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */ | |
| 130 | #define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */ | |
| 131 | #define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */ | |
| 132 | #define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */ | |
| 133 | #define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */ | |
| 134 | #define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */ | |
| 135 | #define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */ | |
| 136 | #define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */ | |
| 137 | #define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */ | |
| 138 | #define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */ | |
| 139 | ||
| 140 | #endif /* CONFIG_PLAT_USRV */ | |
| 141 | ||
| 142 | #define PLD_ICUISTS __reg16(PLD_BASE + 0x8002) | |
| 143 | #define PLD_ICUISTS_VECB_MASK (0xf000) | |
| 144 | #define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK) | |
| 145 | #define PLD_ICUISTS_ISN_MASK (0x07c0) | |
| 146 | #define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK) | |
| 147 | #define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004) | |
| 148 | #define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006) | |
| 149 | #define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100) | |
| 150 | #define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102) | |
| 151 | #define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104) | |
| 152 | #define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106) | |
| 153 | #define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108) | |
| 154 | #define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a) | |
| 155 | #define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c) | |
| 156 | #define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e) | |
| 157 | #define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110) | |
| 158 | #define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112) | |
| 159 | #define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114) | |
| 160 | #define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116) | |
| 161 | #define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118) | |
| 162 | #define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a) | |
| 163 | #define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c) | |
| 164 | #define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e) | |
| 165 | #define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120) | |
| 166 | #define PLD_ICUCR_IEN (0x1000) | |
| 167 | #define PLD_ICUCR_IREQ (0x0100) | |
| 168 | #define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */ | |
| 169 | #define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */ | |
| 170 | #define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */ | |
| 171 | #define PLD_ICUCR_ISMOD03 (0x0030) /* High level */ | |
| 172 | #define PLD_ICUCR_ILEVEL0 (0x0000) | |
| 173 | #define PLD_ICUCR_ILEVEL1 (0x0001) | |
| 174 | #define PLD_ICUCR_ILEVEL2 (0x0002) | |
| 175 | #define PLD_ICUCR_ILEVEL3 (0x0003) | |
| 176 | #define PLD_ICUCR_ILEVEL4 (0x0004) | |
| 177 | #define PLD_ICUCR_ILEVEL5 (0x0005) | |
| 178 | #define PLD_ICUCR_ILEVEL6 (0x0006) | |
| 179 | #define PLD_ICUCR_ILEVEL7 (0x0007) | |
| 180 | ||
| 181 | /* Power Control of MMC and CF */ | |
| 182 | #define PLD_CPCR __reg16(PLD_BASE + 0x14000) | |
| 183 | #define PLD_CPCR_CF 0x0001 | |
| 184 | #define PLD_CPCR_MMC 0x0002 | |
| 185 | ||
| 186 | /* LED Control | |
| 187 | * | |
| 188 | * 1: DIP swich side | |
| 189 | * 2: Reset switch side | |
| 190 | */ | |
| 191 | #define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002) | |
| 192 | #define PLD_IOLED_1_ON 0x001 | |
| 193 | #define PLD_IOLED_1_OFF 0x000 | |
| 194 | #define PLD_IOLED_2_ON 0x002 | |
| 195 | #define PLD_IOLED_2_OFF 0x000 | |
| 196 | ||
| 197 | /* DIP Switch | |
| 198 | * 0: Write-protect of Flash Memory (0:protected, 1:non-protected) | |
| 199 | * 1: - | |
| 200 | * 2: - | |
| 201 | * 3: - | |
| 202 | */ | |
| 203 | #define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004) | |
| 204 | #define PLD_IOSWSTS_IOSW2 0x0200 | |
| 205 | #define PLD_IOSWSTS_IOSW1 0x0100 | |
| 206 | #define PLD_IOSWSTS_IOWP0 0x0001 | |
| 207 | ||
| 208 | /* CRC */ | |
| 209 | #define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000) | |
| 210 | #define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002) | |
| 211 | #define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004) | |
| 212 | #define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006) | |
| 213 | #define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008) | |
| 214 | #define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a) | |
| 215 | ||
| 216 | /* RTC */ | |
| 217 | #define PLD_RTCCR __reg16(PLD_BASE + 0x1c000) | |
| 218 | #define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002) | |
| 219 | #define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004) | |
| 220 | #define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006) | |
| 221 | #define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008) | |
| 222 | ||
| 223 | /* SIO0 */ | |
| 224 | #define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000) | |
| 225 | #define PLD_ESIO0CR_TXEN 0x0001 | |
| 226 | #define PLD_ESIO0CR_RXEN 0x0002 | |
| 227 | #define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002) | |
| 228 | #define PLD_ESIO0MOD0_CTSS 0x0040 | |
| 229 | #define PLD_ESIO0MOD0_RTSS 0x0080 | |
| 230 | #define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004) | |
| 231 | #define PLD_ESIO0MOD1_LMFS 0x0010 | |
| 232 | #define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006) | |
| 233 | #define PLD_ESIO0STS_TEMP 0x0001 | |
| 234 | #define PLD_ESIO0STS_TXCP 0x0002 | |
| 235 | #define PLD_ESIO0STS_RXCP 0x0004 | |
| 236 | #define PLD_ESIO0STS_TXSC 0x0100 | |
| 237 | #define PLD_ESIO0STS_RXSC 0x0200 | |
| 238 | #define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP) | |
| 239 | #define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008) | |
| 240 | #define PLD_ESIO0INTCR_TXIEN 0x0002 | |
| 241 | #define PLD_ESIO0INTCR_RXCEN 0x0004 | |
| 242 | #define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a) | |
| 243 | #define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c) | |
| 244 | #define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e) | |
| 245 | ||
| 246 | /* SIM Card */ | |
| 247 | #define PLD_SCCR __reg16(PLD_BASE + 0x38000) | |
| 248 | #define PLD_SCMOD __reg16(PLD_BASE + 0x38004) | |
| 249 | #define PLD_SCSTS __reg16(PLD_BASE + 0x38006) | |
| 250 | #define PLD_SCINTCR __reg16(PLD_BASE + 0x38008) | |
| 251 | #define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a) | |
| 252 | #define PLD_SCTXB __reg16(PLD_BASE + 0x3800c) | |
| 253 | #define PLD_SCRXB __reg16(PLD_BASE + 0x3800e) | |
| 254 | ||
| fabb626a | 255 | #endif /* _OPSPUT_OPSPUT_PLD.H */ |