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1da177e4 LT |
1 | /* |
2 | * linux/arch/m32r/lib/ashxdi3.S | |
3 | * | |
4 | * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata | |
5 | * | |
6 | */ | |
1da177e4 LT |
7 | |
8 | ; | |
9 | ; input (r0,r1) src | |
10 | ; input r2 shift val | |
11 | ; r3 scratch | |
12 | ; output (r0,r1) | |
13 | ; | |
14 | ||
15 | #ifdef CONFIG_ISA_DUAL_ISSUE | |
16 | ||
17 | #ifndef __LITTLE_ENDIAN__ | |
18 | ||
19 | .text | |
20 | .align 4 | |
21 | .globl __ashrdi3 | |
22 | __ashrdi3: | |
23 | cmpz r2 || ldi r3, #32 | |
24 | jc r14 || cmpu r2, r3 | |
25 | bc 1f | |
26 | ; case 32 =< shift | |
27 | mv r1, r0 || srai r0, #31 | |
28 | addi r2, #-32 | |
29 | sra r1, r2 | |
30 | jmp r14 | |
31 | .fillinsn | |
32 | 1: ; case shift <32 | |
33 | mv r3, r0 || srl r1, r2 | |
34 | sra r0, r2 || neg r2, r2 | |
35 | sll r3, r2 | |
36 | or r1, r3 || jmp r14 | |
37 | ||
38 | .align 4 | |
39 | .globl __ashldi3 | |
40 | .globl __lshldi3 | |
41 | __ashldi3: | |
42 | __lshldi3: | |
43 | cmpz r2 || ldi r3, #32 | |
44 | jc r14 || cmpu r2, r3 | |
45 | bc 1f | |
46 | ; case 32 =< shift | |
47 | mv r0, r1 || addi r2, #-32 | |
48 | sll r0, r2 || ldi r1, #0 | |
49 | jmp r14 | |
50 | .fillinsn | |
51 | 1: ; case shift <32 | |
52 | mv r3, r1 || sll r0, r2 | |
53 | sll r1, r2 || neg r2, r2 | |
54 | srl r3, r2 | |
55 | or r0, r3 || jmp r14 | |
56 | ||
57 | .align 4 | |
58 | .globl __lshrdi3 | |
59 | __lshrdi3: | |
60 | cmpz r2 || ldi r3, #32 | |
61 | jc r14 || cmpu r2, r3 | |
62 | bc 1f | |
63 | ; case 32 =< shift | |
64 | mv r1, r0 || addi r2, #-32 | |
65 | ldi r0, #0 || srl r1, r2 | |
66 | jmp r14 | |
67 | .fillinsn | |
68 | 1: ; case shift <32 | |
69 | mv r3, r0 || srl r1, r2 | |
70 | srl r0, r2 || neg r2, r2 | |
71 | sll r3, r2 | |
72 | or r1, r3 || jmp r14 | |
73 | ||
74 | #else /* LITTLE_ENDIAN */ | |
75 | ||
76 | .text | |
77 | .align 4 | |
78 | .globl __ashrdi3 | |
79 | __ashrdi3: | |
80 | cmpz r2 || ldi r3, #32 | |
81 | jc r14 || cmpu r2, r3 | |
82 | bc 1f | |
83 | ; case 32 =< shift | |
84 | mv r0, r1 || srai r1, #31 | |
85 | addi r2, #-32 | |
86 | sra r0, r2 | |
87 | jmp r14 | |
88 | .fillinsn | |
89 | 1: ; case shift <32 | |
90 | mv r3, r1 || srl r0, r2 | |
91 | sra r1, r2 || neg r2, r2 | |
92 | sll r3, r2 | |
93 | or r0, r3 || jmp r14 | |
94 | ||
95 | .align 4 | |
96 | .globl __ashldi3 | |
97 | .globl __lshldi3 | |
98 | __ashldi3: | |
99 | __lshldi3: | |
100 | cmpz r2 || ldi r3, #32 | |
101 | jc r14 || cmpu r2, r3 | |
102 | bc 1f | |
103 | ; case 32 =< shift | |
104 | mv r1, r0 || addi r2, #-32 | |
105 | sll r1, r2 || ldi r0, #0 | |
106 | jmp r14 | |
107 | .fillinsn | |
108 | 1: ; case shift <32 | |
109 | mv r3, r0 || sll r1, r2 | |
110 | sll r0, r2 || neg r2, r2 | |
111 | srl r3, r2 | |
112 | or r1, r3 || jmp r14 | |
113 | ||
114 | .align 4 | |
115 | .globl __lshrdi3 | |
116 | __lshrdi3: | |
117 | cmpz r2 || ldi r3, #32 | |
118 | jc r14 || cmpu r2, r3 | |
119 | bc 1f | |
120 | ; case 32 =< shift | |
121 | mv r0, r1 || addi r2, #-32 | |
122 | ldi r1, #0 || srl r0, r2 | |
123 | jmp r14 | |
124 | .fillinsn | |
125 | 1: ; case shift <32 | |
126 | mv r3, r1 || srl r0, r2 | |
127 | srl r1, r2 || neg r2, r2 | |
128 | sll r3, r2 | |
129 | or r0, r3 || jmp r14 | |
130 | ||
131 | #endif | |
132 | ||
133 | #else /* not CONFIG_ISA_DUAL_ISSUE */ | |
134 | ||
135 | #ifndef __LITTLE_ENDIAN__ | |
136 | ||
137 | .text | |
138 | .align 4 | |
139 | .globl __ashrdi3 | |
140 | __ashrdi3: | |
141 | beqz r2, 2f | |
142 | cmpui r2, #32 | |
143 | bc 1f | |
144 | ; case 32 =< shift | |
145 | mv r1, r0 | |
146 | srai r0, #31 | |
147 | addi r2, #-32 | |
148 | sra r1, r2 | |
149 | jmp r14 | |
150 | .fillinsn | |
151 | 1: ; case shift <32 | |
152 | mv r3, r0 | |
153 | srl r1, r2 | |
154 | sra r0, r2 | |
155 | neg r2, r2 | |
156 | sll r3, r2 | |
157 | or r1, r3 | |
158 | .fillinsn | |
159 | 2: | |
160 | jmp r14 | |
161 | ||
162 | .align 4 | |
163 | .globl __ashldi3 | |
164 | .globl __lshldi3 | |
165 | __ashldi3: | |
166 | __lshldi3: | |
167 | beqz r2, 2f | |
168 | cmpui r2, #32 | |
169 | bc 1f | |
170 | ; case 32 =< shift | |
171 | mv r0, r1 | |
172 | addi r2, #-32 | |
173 | sll r0, r2 | |
174 | ldi r1, #0 | |
175 | jmp r14 | |
176 | .fillinsn | |
177 | 1: ; case shift <32 | |
178 | mv r3, r1 | |
179 | sll r0, r2 | |
180 | sll r1, r2 | |
181 | neg r2, r2 | |
182 | srl r3, r2 | |
183 | or r0, r3 | |
184 | .fillinsn | |
185 | 2: | |
186 | jmp r14 | |
187 | ||
188 | .align 4 | |
189 | .globl __lshrdi3 | |
190 | __lshrdi3: | |
191 | beqz r2, 2f | |
192 | cmpui r2, #32 | |
193 | bc 1f | |
194 | ; case 32 =< shift | |
195 | mv r1, r0 | |
196 | ldi r0, #0 | |
197 | addi r2, #-32 | |
198 | srl r1, r2 | |
199 | jmp r14 | |
200 | .fillinsn | |
201 | 1: ; case shift <32 | |
202 | mv r3, r0 | |
203 | srl r1, r2 | |
204 | srl r0, r2 | |
205 | neg r2, r2 | |
206 | sll r3, r2 | |
207 | or r1, r3 | |
208 | .fillinsn | |
209 | 2: | |
210 | jmp r14 | |
211 | ||
212 | #else | |
213 | ||
214 | .text | |
215 | .align 4 | |
216 | .globl __ashrdi3 | |
217 | __ashrdi3: | |
218 | beqz r2, 2f | |
219 | cmpui r2, #32 | |
220 | bc 1f | |
221 | ; case 32 =< shift | |
222 | mv r0, r1 | |
223 | srai r1, #31 | |
224 | addi r2, #-32 | |
225 | sra r0, r2 | |
226 | jmp r14 | |
227 | .fillinsn | |
228 | 1: ; case shift <32 | |
229 | mv r3, r1 | |
230 | srl r0, r2 | |
231 | sra r1, r2 | |
232 | neg r2, r2 | |
233 | sll r3, r2 | |
234 | or r0, r3 | |
235 | .fillinsn | |
236 | 2: | |
237 | jmp r14 | |
238 | ||
239 | .align 4 | |
240 | .globl __ashldi3 | |
241 | .globl __lshldi3 | |
242 | __ashldi3: | |
243 | __lshldi3: | |
244 | beqz r2, 2f | |
245 | cmpui r2, #32 | |
246 | bc 1f | |
247 | ; case 32 =< shift | |
248 | mv r1, r0 | |
249 | addi r2, #-32 | |
250 | sll r1, r2 | |
251 | ldi r0, #0 | |
252 | jmp r14 | |
253 | .fillinsn | |
254 | 1: ; case shift <32 | |
255 | mv r3, r0 | |
256 | sll r1, r2 | |
257 | sll r0, r2 | |
258 | neg r2, r2 | |
259 | srl r3, r2 | |
260 | or r1, r3 | |
261 | .fillinsn | |
262 | 2: | |
263 | jmp r14 | |
264 | ||
265 | .align 4 | |
266 | .globl __lshrdi3 | |
267 | __lshrdi3: | |
268 | beqz r2, 2f | |
269 | cmpui r2, #32 | |
270 | bc 1f | |
271 | ; case 32 =< shift | |
272 | mv r0, r1 | |
273 | ldi r1, #0 | |
274 | addi r2, #-32 | |
275 | srl r0, r2 | |
276 | jmp r14 | |
277 | .fillinsn | |
278 | 1: ; case shift <32 | |
279 | mv r3, r1 | |
280 | srl r0, r2 | |
281 | srl r1, r2 | |
282 | neg r2, r2 | |
283 | sll r3, r2 | |
284 | or r0, r3 | |
285 | .fillinsn | |
286 | 2: | |
287 | jmp r14 | |
288 | ||
289 | #endif | |
290 | ||
291 | #endif /* not CONFIG_ISA_DUAL_ISSUE */ | |
292 | ||
293 | .end |