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bea8bcb1 SK |
1 | /* |
2 | * m5441xsim.h -- Coldfire 5441x register definitions | |
3 | * | |
4 | * (C) Copyright 2012, Steven King <sfking@fdwdc.com> | |
5 | */ | |
6 | ||
7 | #ifndef m5441xsim_h | |
8 | #define m5441xsim_h | |
9 | ||
10 | #define CPU_NAME "COLDFIRE(m5441x)" | |
11 | #define CPU_INSTR_PER_JIFFY 2 | |
12 | #define MCF_BUSCLK (MCF_CLK / 2) | |
657ae75f | 13 | #define MACHINE MACH_M5441X |
00c3532b | 14 | #define FPUTYPE 0 |
bea8bcb1 SK |
15 | |
16 | #include <asm/m54xxacr.h> | |
17 | ||
18 | /* | |
19 | * Reset Controller Module. | |
20 | */ | |
21 | ||
22 | #define MCF_RCR 0xec090000 | |
23 | #define MCF_RSR 0xec090001 | |
24 | ||
25 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
26 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
27 | ||
28 | /* | |
29 | * Interrupt Controller Modules. | |
30 | */ | |
31 | /* the 5441x have 3 interrupt controllers, each control 64 interrupts */ | |
32 | #define MCFINT_VECBASE 64 | |
33 | #define MCFINT0_VECBASE MCFINT_VECBASE | |
34 | #define MCFINT1_VECBASE (MCFINT0_VECBASE + 64) | |
35 | #define MCFINT2_VECBASE (MCFINT1_VECBASE + 64) | |
36 | ||
37 | /* interrupt controller 0 */ | |
38 | #define MCFINTC0_SIMR 0xfc04801c | |
39 | #define MCFINTC0_CIMR 0xfc04801d | |
40 | #define MCFINTC0_ICR0 0xfc048040 | |
41 | /* interrupt controller 1 */ | |
42 | #define MCFINTC1_SIMR 0xfc04c01c | |
43 | #define MCFINTC1_CIMR 0xfc04c01d | |
44 | #define MCFINTC1_ICR0 0xfc04c040 | |
45 | /* interrupt controller 2 */ | |
46 | #define MCFINTC2_SIMR 0xfc05001c | |
47 | #define MCFINTC2_CIMR 0xfc05001d | |
48 | #define MCFINTC2_ICR0 0xfc050040 | |
49 | ||
50 | /* on interrupt controller 0 */ | |
51 | #define MCFINT0_EPORT0 1 | |
52 | #define MCFINT0_UART0 26 | |
53 | #define MCFINT0_UART1 27 | |
54 | #define MCFINT0_UART2 28 | |
55 | #define MCFINT0_UART3 29 | |
56 | #define MCFINT0_I2C0 30 | |
57 | #define MCFINT0_DSPI0 31 | |
58 | ||
59 | #define MCFINT0_TIMER0 32 | |
60 | #define MCFINT0_TIMER1 33 | |
61 | #define MCFINT0_TIMER2 34 | |
62 | #define MCFINT0_TIMER3 35 | |
63 | ||
64 | #define MCFINT0_FECRX0 36 | |
65 | #define MCFINT0_FECTX0 40 | |
66 | #define MCFINT0_FECENTC0 42 | |
67 | ||
68 | #define MCFINT0_FECRX1 49 | |
69 | #define MCFINT0_FECTX1 53 | |
70 | #define MCFINT0_FECENTC1 55 | |
71 | ||
72 | /* on interrupt controller 1 */ | |
73 | #define MCFINT1_UART4 48 | |
74 | #define MCFINT1_UART5 49 | |
75 | #define MCFINT1_UART6 50 | |
76 | #define MCFINT1_UART7 51 | |
77 | #define MCFINT1_UART8 52 | |
78 | #define MCFINT1_UART9 53 | |
79 | #define MCFINT1_DSPI1 54 | |
80 | #define MCFINT1_DSPI2 55 | |
81 | #define MCFINT1_DSPI3 56 | |
82 | #define MCFINT1_I2C1 57 | |
83 | #define MCFINT1_I2C2 58 | |
84 | #define MCFINT1_I2C3 59 | |
85 | #define MCFINT1_I2C4 60 | |
86 | #define MCFINT1_I2C5 61 | |
87 | ||
88 | /* on interrupt controller 2 */ | |
89 | #define MCFINT2_PIT0 13 | |
90 | #define MCFINT2_PIT1 14 | |
91 | #define MCFINT2_PIT2 15 | |
92 | #define MCFINT2_PIT3 16 | |
93 | #define MCFINT2_RTC 26 | |
94 | ||
95 | /* | |
96 | * PIT timer module. | |
97 | */ | |
98 | #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */ | |
99 | #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */ | |
100 | #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */ | |
101 | #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */ | |
102 | ||
103 | ||
104 | #define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1) | |
105 | ||
106 | /* | |
107 | * Power Management | |
108 | */ | |
109 | #define MCFPM_WCR 0xfc040013 | |
110 | #define MCFPM_PPMSR0 0xfc04002c | |
111 | #define MCFPM_PPMCR0 0xfc04002d | |
112 | #define MCFPM_PPMSR1 0xfc04002e | |
113 | #define MCFPM_PPMCR1 0xfc04002f | |
114 | #define MCFPM_PPMHR0 0xfc040030 | |
115 | #define MCFPM_PPMLR0 0xfc040034 | |
116 | #define MCFPM_PPMHR1 0xfc040038 | |
117 | #define MCFPM_PPMLR1 0xfc04003c | |
118 | #define MCFPM_LPCR 0xec090007 | |
119 | /* | |
120 | * UART module. | |
121 | */ | |
122 | #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */ | |
123 | #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */ | |
124 | #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */ | |
125 | #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */ | |
126 | #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */ | |
127 | #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */ | |
128 | #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */ | |
129 | #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */ | |
130 | #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */ | |
131 | #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */ | |
132 | ||
133 | #define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0) | |
134 | #define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1) | |
135 | #define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2) | |
136 | #define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3) | |
137 | #define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4) | |
138 | #define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5) | |
139 | #define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6) | |
140 | #define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7) | |
141 | #define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8) | |
142 | #define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9) | |
143 | /* | |
144 | * FEC modules. | |
145 | */ | |
146 | #define MCFFEC_BASE0 0xfc0d4000 | |
147 | #define MCFFEC_SIZE0 0x800 | |
148 | #define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0) | |
149 | #define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0) | |
150 | #define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0) | |
151 | ||
152 | #define MCFFEC_BASE1 0xfc0d8000 | |
153 | #define MCFFEC_SIZE1 0x800 | |
154 | #define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1) | |
155 | #define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1) | |
156 | #define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1) | |
157 | /* | |
158 | * I2C modules. | |
159 | */ | |
160 | #define MCFI2C_BASE0 0xfc058000 | |
161 | #define MCFI2C_SIZE0 0x20 | |
162 | #define MCFI2C_BASE1 0xfc038000 | |
163 | #define MCFI2C_SIZE1 0x20 | |
164 | #define MCFI2C_BASE2 0xec010000 | |
165 | #define MCFI2C_SIZE2 0x20 | |
166 | #define MCFI2C_BASE3 0xec014000 | |
167 | #define MCFI2C_SIZE3 0x20 | |
168 | #define MCFI2C_BASE4 0xec018000 | |
169 | #define MCFI2C_SIZE4 0x20 | |
170 | #define MCFI2C_BASE5 0xec01c000 | |
171 | #define MCFI2C_SIZE5 0x20 | |
172 | ||
173 | #define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0) | |
174 | #define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1) | |
175 | #define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2) | |
176 | #define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3) | |
177 | #define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4) | |
178 | #define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5) | |
179 | /* | |
180 | * EPORT Module. | |
181 | */ | |
182 | #define MCFEPORT_EPPAR 0xfc090000 | |
183 | #define MCFEPORT_EPIER 0xfc090003 | |
184 | #define MCFEPORT_EPFR 0xfc090006 | |
c785a3d7 SK |
185 | /* |
186 | * RTC Module. | |
187 | */ | |
188 | #define MCFRTC_BASE 0xfc0a8000 | |
189 | #define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000) | |
190 | #define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC) | |
bea8bcb1 SK |
191 | |
192 | /* | |
193 | * GPIO Module. | |
194 | */ | |
195 | #define MCFGPIO_PODR_A 0xec094000 | |
196 | #define MCFGPIO_PODR_B 0xec094001 | |
197 | #define MCFGPIO_PODR_C 0xec094002 | |
198 | #define MCFGPIO_PODR_D 0xec094003 | |
199 | #define MCFGPIO_PODR_E 0xec094004 | |
200 | #define MCFGPIO_PODR_F 0xec094005 | |
201 | #define MCFGPIO_PODR_G 0xec094006 | |
202 | #define MCFGPIO_PODR_H 0xec094007 | |
203 | #define MCFGPIO_PODR_I 0xec094008 | |
204 | #define MCFGPIO_PODR_J 0xec094009 | |
205 | #define MCFGPIO_PODR_K 0xec09400a | |
206 | ||
207 | #define MCFGPIO_PDDR_A 0xec09400c | |
208 | #define MCFGPIO_PDDR_B 0xec09400d | |
209 | #define MCFGPIO_PDDR_C 0xec09400e | |
210 | #define MCFGPIO_PDDR_D 0xec09400f | |
211 | #define MCFGPIO_PDDR_E 0xec094010 | |
212 | #define MCFGPIO_PDDR_F 0xec094011 | |
213 | #define MCFGPIO_PDDR_G 0xec094012 | |
214 | #define MCFGPIO_PDDR_H 0xec094013 | |
215 | #define MCFGPIO_PDDR_I 0xec094014 | |
216 | #define MCFGPIO_PDDR_J 0xec094015 | |
217 | #define MCFGPIO_PDDR_K 0xec094016 | |
218 | ||
219 | #define MCFGPIO_PPDSDR_A 0xec094018 | |
220 | #define MCFGPIO_PPDSDR_B 0xec094019 | |
221 | #define MCFGPIO_PPDSDR_C 0xec09401a | |
222 | #define MCFGPIO_PPDSDR_D 0xec09401b | |
223 | #define MCFGPIO_PPDSDR_E 0xec09401c | |
224 | #define MCFGPIO_PPDSDR_F 0xec09401d | |
225 | #define MCFGPIO_PPDSDR_G 0xec09401e | |
226 | #define MCFGPIO_PPDSDR_H 0xec09401f | |
227 | #define MCFGPIO_PPDSDR_I 0xec094020 | |
228 | #define MCFGPIO_PPDSDR_J 0xec094021 | |
229 | #define MCFGPIO_PPDSDR_K 0xec094022 | |
230 | ||
231 | #define MCFGPIO_PCLRR_A 0xec094024 | |
232 | #define MCFGPIO_PCLRR_B 0xec094025 | |
233 | #define MCFGPIO_PCLRR_C 0xec094026 | |
234 | #define MCFGPIO_PCLRR_D 0xec094027 | |
235 | #define MCFGPIO_PCLRR_E 0xec094028 | |
236 | #define MCFGPIO_PCLRR_F 0xec094029 | |
237 | #define MCFGPIO_PCLRR_G 0xec09402a | |
238 | #define MCFGPIO_PCLRR_H 0xec09402b | |
239 | #define MCFGPIO_PCLRR_I 0xec09402c | |
240 | #define MCFGPIO_PCLRR_J 0xec09402d | |
241 | #define MCFGPIO_PCLRR_K 0xec09402e | |
242 | ||
243 | #define MCFGPIO_PAR_FBCTL 0xec094048 | |
244 | #define MCFGPIO_PAR_BE 0xec094049 | |
245 | #define MCFGPIO_PAR_CS 0xec09404a | |
246 | #define MCFGPIO_PAR_CANI2C 0xec09404b | |
247 | #define MCFGPIO_PAR_IRQ0H 0xec09404c | |
248 | #define MCFGPIO_PAR_IRQ0L 0xec09404d | |
249 | #define MCFGPIO_PAR_DSPIOWH 0xec09404e | |
250 | #define MCFGPIO_PAR_DSPIOWL 0xec09404f | |
251 | #define MCFGPIO_PAR_TIMER 0xec094050 | |
252 | #define MCFGPIO_PAR_UART2 0xec094051 | |
253 | #define MCFGPIO_PAR_UART1 0xec094052 | |
254 | #define MCFGPIO_PAR_UART0 0xec094053 | |
255 | #define MCFGPIO_PAR_SDHCH 0xec094054 | |
256 | #define MCFGPIO_PAR_SDHCL 0xec094055 | |
257 | #define MCFGPIO_PAR_SIMP0H 0xec094056 | |
258 | #define MCFGPIO_PAR_SIMP0L 0xec094057 | |
259 | #define MCFGPIO_PAR_SSI0H 0xec094058 | |
260 | #define MCFGPIO_PAR_SSI0L 0xec094059 | |
261 | #define MCFGPIO_PAR_DEBUGH1 0xec09405a | |
262 | #define MCFGPIO_PAR_DEBUGH0 0xec09405b | |
263 | #define MCFGPIO_PAR_DEBUGl 0xec09405c | |
264 | #define MCFGPIO_PAR_FEC 0xec09405e | |
265 | ||
266 | /* generalization for generic gpio support */ | |
267 | #define MCFGPIO_PODR MCFGPIO_PODR_A | |
268 | #define MCFGPIO_PDDR MCFGPIO_PDDR_A | |
269 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A | |
270 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_A | |
271 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_A | |
272 | ||
273 | #define MCFGPIO_IRQ_MIN 17 | |
274 | #define MCFGPIO_IRQ_MAX 24 | |
275 | #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN) | |
276 | #define MCFGPIO_PIN_MAX 87 | |
277 | ||
278 | #endif /* m5441xsim_h */ |