Commit | Line | Data |
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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
2462bacd | 12 | #include <linux/irqdomain.h> |
eedbdab9 | 13 | #include <linux/irq.h> |
bcff661d | 14 | #include <linux/of_address.h> |
eedbdab9 | 15 | #include <linux/io.h> |
892ee92b | 16 | #include <linux/bug.h> |
eedbdab9 | 17 | |
8a9e90a1 | 18 | #include "../../drivers/irqchip/irqchip.h" |
eedbdab9 | 19 | |
bcff661d | 20 | static void __iomem *intc_baseaddr; |
eedbdab9 | 21 | |
eedbdab9 MS |
22 | /* No one else should require these constants, so define them locally here. */ |
23 | #define ISR 0x00 /* Interrupt Status Register */ | |
24 | #define IPR 0x04 /* Interrupt Pending Register */ | |
25 | #define IER 0x08 /* Interrupt Enable Register */ | |
26 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
27 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
28 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
29 | #define IVR 0x18 /* Interrupt Vector Register */ | |
30 | #define MER 0x1c /* Master Enable Register */ | |
31 | ||
32 | #define MER_ME (1<<0) | |
33 | #define MER_HIE (1<<1) | |
34 | ||
6f205a4c | 35 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 36 | { |
6c7a2676 MS |
37 | unsigned long mask = 1 << d->hwirq; |
38 | ||
39 | pr_debug("enable_or_unmask: %ld\n", d->hwirq); | |
33d9ff59 | 40 | |
41 | /* ack level irqs because they can't be acked during | |
42 | * ack function since the handle_level_irq function | |
43 | * acks the irq before calling the interrupt handler | |
44 | */ | |
4adc192e | 45 | if (irqd_is_level_type(d)) |
9e77dab6 | 46 | out_be32(intc_baseaddr + IAR, mask); |
7958a689 | 47 | |
9e77dab6 | 48 | out_be32(intc_baseaddr + SIE, mask); |
eedbdab9 MS |
49 | } |
50 | ||
6f205a4c | 51 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 52 | { |
6c7a2676 | 53 | pr_debug("disable: %ld\n", d->hwirq); |
9e77dab6 | 54 | out_be32(intc_baseaddr + CIE, 1 << d->hwirq); |
eedbdab9 MS |
55 | } |
56 | ||
6f205a4c | 57 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 58 | { |
6c7a2676 | 59 | pr_debug("ack: %ld\n", d->hwirq); |
9e77dab6 | 60 | out_be32(intc_baseaddr + IAR, 1 << d->hwirq); |
eedbdab9 MS |
61 | } |
62 | ||
6f205a4c | 63 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 64 | { |
6c7a2676 MS |
65 | unsigned long mask = 1 << d->hwirq; |
66 | ||
67 | pr_debug("disable_and_ack: %ld\n", d->hwirq); | |
9e77dab6 MS |
68 | out_be32(intc_baseaddr + CIE, mask); |
69 | out_be32(intc_baseaddr + IAR, mask); | |
eedbdab9 MS |
70 | } |
71 | ||
eedbdab9 MS |
72 | static struct irq_chip intc_dev = { |
73 | .name = "Xilinx INTC", | |
6f205a4c TG |
74 | .irq_unmask = intc_enable_or_unmask, |
75 | .irq_mask = intc_disable_or_mask, | |
76 | .irq_ack = intc_ack, | |
77 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
78 | }; |
79 | ||
2462bacd GL |
80 | static struct irq_domain *root_domain; |
81 | ||
82 | unsigned int get_irq(void) | |
eedbdab9 | 83 | { |
2462bacd | 84 | unsigned int hwirq, irq = -1; |
eedbdab9 | 85 | |
9e77dab6 | 86 | hwirq = in_be32(intc_baseaddr + IVR); |
2462bacd GL |
87 | if (hwirq != -1U) |
88 | irq = irq_find_mapping(root_domain, hwirq); | |
89 | ||
90 | pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq); | |
eedbdab9 MS |
91 | |
92 | return irq; | |
93 | } | |
94 | ||
c0d997fb | 95 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd GL |
96 | { |
97 | u32 intr_mask = (u32)d->host_data; | |
98 | ||
99 | if (intr_mask & (1 << hw)) { | |
100 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
101 | handle_edge_irq, "edge"); | |
102 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
103 | } else { | |
104 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
105 | handle_level_irq, "level"); | |
106 | irq_set_status_flags(irq, IRQ_LEVEL); | |
107 | } | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
112 | .xlate = irq_domain_xlate_onetwocell, | |
113 | .map = xintc_map, | |
114 | }; | |
115 | ||
8a9e90a1 MS |
116 | static int __init xilinx_intc_of_init(struct device_node *intc, |
117 | struct device_node *parent) | |
eedbdab9 | 118 | { |
2462bacd | 119 | u32 nr_irq, intr_mask; |
bcff661d | 120 | int ret; |
eedbdab9 | 121 | |
bcff661d MS |
122 | intc_baseaddr = of_iomap(intc, 0); |
123 | BUG_ON(!intc_baseaddr); | |
124 | ||
125 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); | |
126 | if (ret < 0) { | |
127 | pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); | |
128 | return -EINVAL; | |
129 | } | |
130 | ||
131 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); | |
132 | if (ret < 0) { | |
133 | pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); | |
134 | return -EINVAL; | |
135 | } | |
eedbdab9 | 136 | |
2ecb899b | 137 | if (intr_mask > (u32)((1ULL << nr_irq) - 1)) |
6bd55f0b | 138 | pr_info(" ERROR: Mismatch in kind-of-intr param\n"); |
eedbdab9 | 139 | |
bcff661d MS |
140 | pr_info("%s: num_irq=%d, edge=0x%x\n", |
141 | intc->full_name, nr_irq, intr_mask); | |
eedbdab9 MS |
142 | |
143 | /* | |
144 | * Disable all external interrupts until they are | |
145 | * explicity requested. | |
146 | */ | |
147 | out_be32(intc_baseaddr + IER, 0); | |
148 | ||
149 | /* Acknowledge any pending interrupts just in case. */ | |
150 | out_be32(intc_baseaddr + IAR, 0xffffffff); | |
151 | ||
152 | /* Turn on the Master Enable. */ | |
153 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); | |
154 | ||
2462bacd GL |
155 | /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm |
156 | * lazy and Michal can clean it up to something nicer when he tests | |
157 | * and commits this patch. ~~gcl */ | |
158 | root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, | |
159 | (void *)intr_mask); | |
7c2c8513 DC |
160 | |
161 | irq_set_default_host(root_domain); | |
8a9e90a1 MS |
162 | |
163 | return 0; | |
eedbdab9 | 164 | } |
8a9e90a1 MS |
165 | |
166 | IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |