Commit | Line | Data |
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eedbdab9 | 1 | /* |
1e529803 MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
eedbdab9 | 12 | #include <linux/interrupt.h> |
eedbdab9 MS |
13 | #include <linux/delay.h> |
14 | #include <linux/sched.h> | |
eedbdab9 | 15 | #include <linux/clk.h> |
eedbdab9 | 16 | #include <linux/clockchips.h> |
cfd4eaef | 17 | #include <linux/of_address.h> |
5c9f303e | 18 | #include <linux/of_irq.h> |
eedbdab9 | 19 | #include <asm/cpuinfo.h> |
c8f77436 | 20 | #include <linux/cnt32_to_63.h> |
eedbdab9 | 21 | |
cfd4eaef | 22 | static void __iomem *timer_baseaddr; |
eedbdab9 | 23 | |
29e3dbb1 MS |
24 | static unsigned int freq_div_hz; |
25 | static unsigned int timer_clock_freq; | |
ccea0e6e | 26 | |
eedbdab9 MS |
27 | #define TCSR0 (0x00) |
28 | #define TLR0 (0x04) | |
29 | #define TCR0 (0x08) | |
30 | #define TCSR1 (0x10) | |
31 | #define TLR1 (0x14) | |
32 | #define TCR1 (0x18) | |
33 | ||
34 | #define TCSR_MDT (1<<0) | |
35 | #define TCSR_UDT (1<<1) | |
36 | #define TCSR_GENT (1<<2) | |
37 | #define TCSR_CAPT (1<<3) | |
38 | #define TCSR_ARHT (1<<4) | |
39 | #define TCSR_LOAD (1<<5) | |
40 | #define TCSR_ENIT (1<<6) | |
41 | #define TCSR_ENT (1<<7) | |
42 | #define TCSR_TINT (1<<8) | |
43 | #define TCSR_PWMA (1<<9) | |
44 | #define TCSR_ENALL (1<<10) | |
45 | ||
5955563a | 46 | static inline void xilinx_timer0_stop(void) |
eedbdab9 | 47 | { |
9e77dab6 MS |
48 | out_be32(timer_baseaddr + TCSR0, |
49 | in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); | |
eedbdab9 MS |
50 | } |
51 | ||
5955563a | 52 | static inline void xilinx_timer0_start_periodic(unsigned long load_val) |
eedbdab9 MS |
53 | { |
54 | if (!load_val) | |
55 | load_val = 1; | |
9e77dab6 MS |
56 | /* loading value to timer reg */ |
57 | out_be32(timer_baseaddr + TLR0, load_val); | |
eedbdab9 MS |
58 | |
59 | /* load the initial value */ | |
9e77dab6 | 60 | out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); |
eedbdab9 MS |
61 | |
62 | /* see timer data sheet for detail | |
63 | * !ENALL - don't enable 'em all | |
64 | * !PWMA - disable pwm | |
65 | * TINT - clear interrupt status | |
66 | * ENT- enable timer itself | |
f7f4786c | 67 | * ENIT - enable interrupt |
eedbdab9 MS |
68 | * !LOAD - clear the bit to let go |
69 | * ARHT - auto reload | |
70 | * !CAPT - no external trigger | |
71 | * !GENT - no external signal | |
72 | * UDT - set the timer as down counter | |
73 | * !MDT0 - generate mode | |
74 | */ | |
9e77dab6 | 75 | out_be32(timer_baseaddr + TCSR0, |
eedbdab9 MS |
76 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
77 | } | |
78 | ||
5955563a | 79 | static inline void xilinx_timer0_start_oneshot(unsigned long load_val) |
eedbdab9 MS |
80 | { |
81 | if (!load_val) | |
82 | load_val = 1; | |
9e77dab6 MS |
83 | /* loading value to timer reg */ |
84 | out_be32(timer_baseaddr + TLR0, load_val); | |
eedbdab9 MS |
85 | |
86 | /* load the initial value */ | |
9e77dab6 | 87 | out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); |
eedbdab9 | 88 | |
9e77dab6 | 89 | out_be32(timer_baseaddr + TCSR0, |
eedbdab9 MS |
90 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
91 | } | |
92 | ||
5955563a | 93 | static int xilinx_timer_set_next_event(unsigned long delta, |
eedbdab9 MS |
94 | struct clock_event_device *dev) |
95 | { | |
96 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); | |
5955563a | 97 | xilinx_timer0_start_oneshot(delta); |
eedbdab9 MS |
98 | return 0; |
99 | } | |
100 | ||
5955563a | 101 | static void xilinx_timer_set_mode(enum clock_event_mode mode, |
eedbdab9 MS |
102 | struct clock_event_device *evt) |
103 | { | |
104 | switch (mode) { | |
105 | case CLOCK_EVT_MODE_PERIODIC: | |
aaa5241e | 106 | pr_info("%s: periodic\n", __func__); |
5955563a | 107 | xilinx_timer0_start_periodic(freq_div_hz); |
eedbdab9 MS |
108 | break; |
109 | case CLOCK_EVT_MODE_ONESHOT: | |
aaa5241e | 110 | pr_info("%s: oneshot\n", __func__); |
eedbdab9 MS |
111 | break; |
112 | case CLOCK_EVT_MODE_UNUSED: | |
aaa5241e | 113 | pr_info("%s: unused\n", __func__); |
eedbdab9 MS |
114 | break; |
115 | case CLOCK_EVT_MODE_SHUTDOWN: | |
aaa5241e | 116 | pr_info("%s: shutdown\n", __func__); |
5955563a | 117 | xilinx_timer0_stop(); |
eedbdab9 MS |
118 | break; |
119 | case CLOCK_EVT_MODE_RESUME: | |
aaa5241e | 120 | pr_info("%s: resume\n", __func__); |
eedbdab9 MS |
121 | break; |
122 | } | |
123 | } | |
124 | ||
5955563a MS |
125 | static struct clock_event_device clockevent_xilinx_timer = { |
126 | .name = "xilinx_clockevent", | |
eedbdab9 | 127 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
c8f77436 | 128 | .shift = 8, |
eedbdab9 | 129 | .rating = 300, |
5955563a MS |
130 | .set_next_event = xilinx_timer_set_next_event, |
131 | .set_mode = xilinx_timer_set_mode, | |
eedbdab9 MS |
132 | }; |
133 | ||
134 | static inline void timer_ack(void) | |
135 | { | |
9e77dab6 | 136 | out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); |
eedbdab9 MS |
137 | } |
138 | ||
139 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
140 | { | |
5955563a | 141 | struct clock_event_device *evt = &clockevent_xilinx_timer; |
eedbdab9 MS |
142 | #ifdef CONFIG_HEART_BEAT |
143 | heartbeat(); | |
144 | #endif | |
145 | timer_ack(); | |
146 | evt->event_handler(evt); | |
147 | return IRQ_HANDLED; | |
148 | } | |
149 | ||
150 | static struct irqaction timer_irqaction = { | |
151 | .handler = timer_interrupt, | |
db2a7df0 | 152 | .flags = IRQF_TIMER, |
eedbdab9 | 153 | .name = "timer", |
5955563a | 154 | .dev_id = &clockevent_xilinx_timer, |
eedbdab9 MS |
155 | }; |
156 | ||
5955563a | 157 | static __init void xilinx_clockevent_init(void) |
eedbdab9 | 158 | { |
5955563a | 159 | clockevent_xilinx_timer.mult = |
ccea0e6e | 160 | div_sc(timer_clock_freq, NSEC_PER_SEC, |
5955563a MS |
161 | clockevent_xilinx_timer.shift); |
162 | clockevent_xilinx_timer.max_delta_ns = | |
163 | clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); | |
164 | clockevent_xilinx_timer.min_delta_ns = | |
165 | clockevent_delta2ns(1, &clockevent_xilinx_timer); | |
166 | clockevent_xilinx_timer.cpumask = cpumask_of(0); | |
167 | clockevents_register_device(&clockevent_xilinx_timer); | |
eedbdab9 MS |
168 | } |
169 | ||
5955563a | 170 | static cycle_t xilinx_read(struct clocksource *cs) |
eedbdab9 MS |
171 | { |
172 | /* reading actual value of timer 1 */ | |
9e77dab6 | 173 | return (cycle_t) (in_be32(timer_baseaddr + TCR1)); |
eedbdab9 MS |
174 | } |
175 | ||
5955563a | 176 | static struct timecounter xilinx_tc = { |
519e9f41 MS |
177 | .cc = NULL, |
178 | }; | |
179 | ||
5955563a | 180 | static cycle_t xilinx_cc_read(const struct cyclecounter *cc) |
519e9f41 | 181 | { |
5955563a | 182 | return xilinx_read(NULL); |
519e9f41 MS |
183 | } |
184 | ||
5955563a MS |
185 | static struct cyclecounter xilinx_cc = { |
186 | .read = xilinx_cc_read, | |
519e9f41 | 187 | .mask = CLOCKSOURCE_MASK(32), |
c8f77436 | 188 | .shift = 8, |
519e9f41 MS |
189 | }; |
190 | ||
5955563a | 191 | static int __init init_xilinx_timecounter(void) |
519e9f41 | 192 | { |
5955563a MS |
193 | xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, |
194 | xilinx_cc.shift); | |
519e9f41 | 195 | |
5955563a | 196 | timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); |
519e9f41 MS |
197 | |
198 | return 0; | |
199 | } | |
200 | ||
eedbdab9 | 201 | static struct clocksource clocksource_microblaze = { |
5955563a | 202 | .name = "xilinx_clocksource", |
eedbdab9 | 203 | .rating = 300, |
5955563a | 204 | .read = xilinx_read, |
eedbdab9 | 205 | .mask = CLOCKSOURCE_MASK(32), |
eedbdab9 MS |
206 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
207 | }; | |
208 | ||
5955563a | 209 | static int __init xilinx_clocksource_init(void) |
eedbdab9 | 210 | { |
b8f39f7d | 211 | if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) |
eedbdab9 MS |
212 | panic("failed to register clocksource"); |
213 | ||
214 | /* stop timer1 */ | |
9e77dab6 MS |
215 | out_be32(timer_baseaddr + TCSR1, |
216 | in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); | |
eedbdab9 | 217 | /* start timer1 - up counting without interrupt */ |
9e77dab6 | 218 | out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); |
519e9f41 MS |
219 | |
220 | /* register timecounter - for ftrace support */ | |
5955563a | 221 | init_xilinx_timecounter(); |
eedbdab9 MS |
222 | return 0; |
223 | } | |
224 | ||
6f34b08f MS |
225 | /* |
226 | * We have to protect accesses before timer initialization | |
227 | * and return 0 for sched_clock function below. | |
228 | */ | |
229 | static int timer_initialized; | |
230 | ||
4bcd943e | 231 | static void __init xilinx_timer_init(struct device_node *timer) |
eedbdab9 | 232 | { |
5a26cd69 | 233 | u32 irq; |
eedbdab9 | 234 | u32 timer_num = 1; |
cfd4eaef MS |
235 | int ret; |
236 | ||
237 | timer_baseaddr = of_iomap(timer, 0); | |
238 | if (!timer_baseaddr) { | |
239 | pr_err("ERROR: invalid timer base address\n"); | |
240 | BUG(); | |
241 | } | |
9e77dab6 | 242 | |
9d0ced00 | 243 | irq = irq_of_parse_and_map(timer, 0); |
cfd4eaef MS |
244 | |
245 | of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); | |
eedbdab9 | 246 | if (timer_num) { |
cfd4eaef | 247 | pr_emerg("Please enable two timers in HW\n"); |
eedbdab9 MS |
248 | BUG(); |
249 | } | |
250 | ||
cfd4eaef | 251 | pr_info("%s: irq=%d\n", timer->full_name, irq); |
eedbdab9 | 252 | |
ccea0e6e | 253 | /* If there is clock-frequency property than use it */ |
cfd4eaef MS |
254 | ret = of_property_read_u32(timer, "clock-frequency", &timer_clock_freq); |
255 | if (ret < 0) | |
ccea0e6e MS |
256 | timer_clock_freq = cpuinfo.cpu_clock_freq; |
257 | ||
258 | freq_div_hz = timer_clock_freq / HZ; | |
eedbdab9 MS |
259 | |
260 | setup_irq(irq, &timer_irqaction); | |
261 | #ifdef CONFIG_HEART_BEAT | |
262 | setup_heartbeat(); | |
263 | #endif | |
5955563a MS |
264 | xilinx_clocksource_init(); |
265 | xilinx_clockevent_init(); | |
6f34b08f MS |
266 | timer_initialized = 1; |
267 | } | |
268 | ||
269 | unsigned long long notrace sched_clock(void) | |
270 | { | |
271 | if (timer_initialized) { | |
272 | struct clocksource *cs = &clocksource_microblaze; | |
9c6f6f54 MS |
273 | |
274 | cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX; | |
6f34b08f MS |
275 | return clocksource_cyc2ns(cyc, cs->mult, cs->shift); |
276 | } | |
277 | return 0; | |
eedbdab9 | 278 | } |
4bcd943e MS |
279 | |
280 | CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", | |
281 | xilinx_timer_init); |