[deliverable/linux.git] / arch / microblaze / kernel / timer.c

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <asm/cpuinfo.h>
#include <asm/setup.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <linux/cnt32_to_63.h>

#ifdef CONFIG_SELFMOD_TIMER
#include <asm/selfmod.h>
#define TIMER_BASE	BARRIER_BASE_ADDR
#else
static unsigned int timer_baseaddr;
#define TIMER_BASE	timer_baseaddr
#endif

static unsigned int freq_div_hz;
static unsigned int timer_clock_freq;

#define TCSR0	(0x00)
#define TLR0	(0x04)
#define TCR0	(0x08)
#define TCSR1	(0x10)
#define TLR1	(0x14)
#define TCR1	(0x18)

#define TCSR_MDT	(1<<0)
#define TCSR_UDT	(1<<1)
#define TCSR_GENT	(1<<2)
#define TCSR_CAPT	(1<<3)
#define TCSR_ARHT	(1<<4)
#define TCSR_LOAD	(1<<5)
#define TCSR_ENIT	(1<<6)
#define TCSR_ENT	(1<<7)
#define TCSR_TINT	(1<<8)
#define TCSR_PWMA	(1<<9)
#define TCSR_ENALL	(1<<10)

static inline void microblaze_timer0_stop(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
}

static inline void microblaze_timer0_start_periodic(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	/* see timer data sheet for detail
	 * !ENALL - don't enable 'em all
	 * !PWMA - disable pwm
	 * TINT - clear interrupt status
	 * ENT- enable timer itself
	 * EINT - enable interrupt
	 * !LOAD - clear the bit to let go
	 * ARHT - auto reload
	 * !CAPT - no external trigger
	 * !GENT - no external signal
	 * UDT - set the timer as down counter
	 * !MDT0 - generate mode
	 */
	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static int microblaze_timer_set_next_event(unsigned long delta,
					struct clock_event_device *dev)
{
	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
	microblaze_timer0_start_oneshot(delta);
	return 0;
}

static void microblaze_timer_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_INFO "%s: periodic\n", __func__);
		microblaze_timer0_start_periodic(freq_div_hz);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		printk(KERN_INFO "%s: oneshot\n", __func__);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		printk(KERN_INFO "%s: unused\n", __func__);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
		printk(KERN_INFO "%s: shutdown\n", __func__);
		microblaze_timer0_stop();
		break;
	case CLOCK_EVT_MODE_RESUME:
		printk(KERN_INFO "%s: resume\n", __func__);
		break;
	}
}

static struct clock_event_device clockevent_microblaze_timer = {
	.name		= "microblaze_clockevent",
	.features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.shift		= 8,
	.rating		= 300,
	.set_next_event	= microblaze_timer_set_next_event,
	.set_mode	= microblaze_timer_set_mode,
};

static inline void timer_ack(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
}

static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_microblaze_timer;
#ifdef CONFIG_HEART_BEAT
	heartbeat();
#endif
	timer_ack();
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction timer_irqaction = {
	.handler = timer_interrupt,
	.flags = IRQF_DISABLED | IRQF_TIMER,
	.name = "timer",
	.dev_id = &clockevent_microblaze_timer,
};

static __init void microblaze_clockevent_init(void)
{
	clockevent_microblaze_timer.mult =
		div_sc(timer_clock_freq, NSEC_PER_SEC,
				clockevent_microblaze_timer.shift);
	clockevent_microblaze_timer.max_delta_ns =
		clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.min_delta_ns =
		clockevent_delta2ns(1, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_microblaze_timer);
}

static cycle_t microblaze_read(struct clocksource *cs)
{
	/* reading actual value of timer 1 */
	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
}

static struct timecounter microblaze_tc = {
	.cc = NULL,
};

static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
{
	return microblaze_read(NULL);
}

static struct cyclecounter microblaze_cc = {
	.read = microblaze_cc_read,
	.mask = CLOCKSOURCE_MASK(32),
	.shift = 8,
};

static int __init init_microblaze_timecounter(void)
{
	microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
				microblaze_cc.shift);

	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());

	return 0;
}

static struct clocksource clocksource_microblaze = {
	.name		= "microblaze_clocksource",
	.rating		= 300,
	.read		= microblaze_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init microblaze_clocksource_init(void)
{
	if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
		panic("failed to register clocksource");

	/* stop timer1 */
	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	/* start timer1 - up counting without interrupt */
	out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);

	/* register timecounter - for ftrace support */
	init_microblaze_timecounter();
	return 0;
}

/*
 * We have to protect accesses before timer initialization
 * and return 0 for sched_clock function below.
 */
static int timer_initialized;

void __init time_init(void)
{
	u32 irq;
	u32 timer_num = 1;
	struct device_node *timer = NULL;
	const void *prop;
#ifdef CONFIG_SELFMOD_TIMER
	unsigned int timer_baseaddr = 0;
	int arr_func[] = {
				(int)&microblaze_read,
				(int)&timer_interrupt,
				(int)&microblaze_clocksource_init,
				(int)&microblaze_timer_set_mode,
				(int)&microblaze_timer_set_next_event,
				0
			};
#endif
	timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
	BUG_ON(!timer);

	timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
	irq = irq_of_parse_and_map(timer, 0);
	timer_num = be32_to_cpup(of_get_property(timer,
						"xlnx,one-timer-only", NULL));
	if (timer_num) {
		printk(KERN_EMERG "Please enable two timers in HW\n");
		BUG();
	}

#ifdef CONFIG_SELFMOD_TIMER
	selfmod_function((int *) arr_func, timer_baseaddr);
#endif
	printk(KERN_INFO "XPS timer #0 at 0x%08x, irq=%d\n",
		timer_baseaddr, irq);

	/* If there is clock-frequency property than use it */
	prop = of_get_property(timer, "clock-frequency", NULL);
	if (prop)
		timer_clock_freq = be32_to_cpup(prop);
	else
		timer_clock_freq = cpuinfo.cpu_clock_freq;

	freq_div_hz = timer_clock_freq / HZ;

	setup_irq(irq, &timer_irqaction);
#ifdef CONFIG_HEART_BEAT
	setup_heartbeat();
#endif
	microblaze_clocksource_init();
	microblaze_clockevent_init();
	timer_initialized = 1;
}

unsigned long long notrace sched_clock(void)
{
	if (timer_initialized) {
		struct clocksource *cs = &clocksource_microblaze;

		cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX;
		return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	}
	return 0;
}
Commit	Line	Data
eedbdab9 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/param.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/profile.h>
	16	#include <linux/irq.h>
	17	#include <linux/delay.h>
	18	#include <linux/sched.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/err.h>
	21	#include <linux/clk.h>
	22	#include <linux/clocksource.h>
	23	#include <linux/clockchips.h>
	24	#include <linux/io.h>
892ee92b	25	#include <linux/bug.h>
eedbdab9 MS	26	#include <asm/cpuinfo.h>
	27	#include <asm/setup.h>
	28	#include <asm/prom.h>
	29	#include <asm/irq.h>
c8f77436	30	#include <linux/cnt32_to_63.h>
eedbdab9 MS	31
	32	#ifdef CONFIG_SELFMOD_TIMER
	33	#include <asm/selfmod.h>
	34	#define TIMER_BASE BARRIER_BASE_ADDR
	35	#else
	36	static unsigned int timer_baseaddr;
	37	#define TIMER_BASE timer_baseaddr
	38	#endif
	39
29e3dbb1 MS	40	static unsigned int freq_div_hz;
29e3dbb1 MS	41	static unsigned int timer_clock_freq;
ccea0e6e	42
eedbdab9 MS	43	#define TCSR0 (0x00)
	44	#define TLR0 (0x04)
	45	#define TCR0 (0x08)
	46	#define TCSR1 (0x10)
	47	#define TLR1 (0x14)
	48	#define TCR1 (0x18)
	49
	50	#define TCSR_MDT (1<<0)
	51	#define TCSR_UDT (1<<1)
	52	#define TCSR_GENT (1<<2)
	53	#define TCSR_CAPT (1<<3)
	54	#define TCSR_ARHT (1<<4)
	55	#define TCSR_LOAD (1<<5)
	56	#define TCSR_ENIT (1<<6)
	57	#define TCSR_ENT (1<<7)
	58	#define TCSR_TINT (1<<8)
	59	#define TCSR_PWMA (1<<9)
	60	#define TCSR_ENALL (1<<10)
	61
	62	static inline void microblaze_timer0_stop(void)
	63	{
	64	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
	65	}
	66
	67	static inline void microblaze_timer0_start_periodic(unsigned long load_val)
	68	{
	69	if (!load_val)
	70	load_val = 1;
	71	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
	72
	73	/* load the initial value */
	74	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
	75
	76	/* see timer data sheet for detail
	77	* !ENALL - don't enable 'em all
	78	* !PWMA - disable pwm
	79	* TINT - clear interrupt status
	80	* ENT- enable timer itself
	81	* EINT - enable interrupt
	82	* !LOAD - clear the bit to let go
	83	* ARHT - auto reload
	84	* !CAPT - no external trigger
	85	* !GENT - no external signal
	86	* UDT - set the timer as down counter
	87	* !MDT0 - generate mode
	88	*/
	89	out_be32(TIMER_BASE + TCSR0,
	90	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
	91	}
	92
	93	static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
	94	{
	95	if (!load_val)
	96	load_val = 1;
	97	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
	98
	99	/* load the initial value */
	100	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
	101
	102	out_be32(TIMER_BASE + TCSR0,
	103	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
	104	}
	105
	106	static int microblaze_timer_set_next_event(unsigned long delta,
107	struct clock_event_device *dev)
108	{
109	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
110	microblaze_timer0_start_oneshot(delta);
111	return 0;
112	}
113
114	static void microblaze_timer_set_mode(enum clock_event_mode mode,
115	struct clock_event_device *evt)
116	{
117	switch (mode) {
118	case CLOCK_EVT_MODE_PERIODIC:
119	printk(KERN_INFO "%s: periodic\n", __func__);
ccea0e6e	120	microblaze_timer0_start_periodic(freq_div_hz);
eedbdab9 MS	121	break;
	122	case CLOCK_EVT_MODE_ONESHOT:
	123	printk(KERN_INFO "%s: oneshot\n", __func__);
	124	break;
	125	case CLOCK_EVT_MODE_UNUSED:
	126	printk(KERN_INFO "%s: unused\n", __func__);
	127	break;
	128	case CLOCK_EVT_MODE_SHUTDOWN:
	129	printk(KERN_INFO "%s: shutdown\n", __func__);
	130	microblaze_timer0_stop();
	131	break;
	132	case CLOCK_EVT_MODE_RESUME:
	133	printk(KERN_INFO "%s: resume\n", __func__);
	134	break;
	135	}
	136	}
	137
	138	static struct clock_event_device clockevent_microblaze_timer = {
	139	.name = "microblaze_clockevent",
	140	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
c8f77436	141	.shift = 8,
eedbdab9 MS	142	.rating = 300,
	143	.set_next_event = microblaze_timer_set_next_event,
	144	.set_mode = microblaze_timer_set_mode,
	145	};
	146
	147	static inline void timer_ack(void)
	148	{
	149	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
	150	}
	151
	152	static irqreturn_t timer_interrupt(int irq, void *dev_id)
	153	{
	154	struct clock_event_device *evt = &clockevent_microblaze_timer;
	155	#ifdef CONFIG_HEART_BEAT
	156	heartbeat();
	157	#endif
	158	timer_ack();
	159	evt->event_handler(evt);
	160	return IRQ_HANDLED;
	161	}
	162
	163	static struct irqaction timer_irqaction = {
	164	.handler = timer_interrupt,
	165	.flags = IRQF_DISABLED \| IRQF_TIMER,
	166	.name = "timer",
	167	.dev_id = &clockevent_microblaze_timer,
	168	};
	169
	170	static __init void microblaze_clockevent_init(void)
	171	{
	172	clockevent_microblaze_timer.mult =
ccea0e6e	173	div_sc(timer_clock_freq, NSEC_PER_SEC,
eedbdab9 MS	174	clockevent_microblaze_timer.shift);
	175	clockevent_microblaze_timer.max_delta_ns =
	176	clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	177	clockevent_microblaze_timer.min_delta_ns =
	178	clockevent_delta2ns(1, &clockevent_microblaze_timer);
	179	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	180	clockevents_register_device(&clockevent_microblaze_timer);
	181	}
	182
f57f2fe2	183	static cycle_t microblaze_read(struct clocksource *cs)
eedbdab9 MS	184	{
	185	/* reading actual value of timer 1 */
	186	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
	187	}
	188
519e9f41 MS	189	static struct timecounter microblaze_tc = {
	190	.cc = NULL,
	191	};
	192
	193	static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
	194	{
	195	return microblaze_read(NULL);
	196	}
	197
	198	static struct cyclecounter microblaze_cc = {
	199	.read = microblaze_cc_read,
	200	.mask = CLOCKSOURCE_MASK(32),
c8f77436	201	.shift = 8,
519e9f41 MS	202	};
519e9f41 MS	203
29e3dbb1	204	static int __init init_microblaze_timecounter(void)
519e9f41	205	{
ccea0e6e	206	microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
519e9f41 MS	207	microblaze_cc.shift);
	208
	209	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
	210
	211	return 0;
	212	}
	213
eedbdab9 MS	214	static struct clocksource clocksource_microblaze = {
	215	.name = "microblaze_clocksource",
	216	.rating = 300,
	217	.read = microblaze_read,
	218	.mask = CLOCKSOURCE_MASK(32),
eedbdab9 MS	219	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	220	};
	221
	222	static int __init microblaze_clocksource_init(void)
	223	{
b8f39f7d	224	if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
eedbdab9 MS	225	panic("failed to register clocksource");
	226
	227	/* stop timer1 */
	228	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	229	/* start timer1 - up counting without interrupt */
	230	out_be32(TIMER_BASE + TCSR1, TCSR_TINT\|TCSR_ENT\|TCSR_ARHT);
519e9f41 MS	231
	232	/* register timecounter - for ftrace support */
	233	init_microblaze_timecounter();
eedbdab9 MS	234	return 0;
	235	}
	236
6f34b08f MS	237	/*
	238	* We have to protect accesses before timer initialization
	239	* and return 0 for sched_clock function below.
	240	*/
	241	static int timer_initialized;
	242
eedbdab9 MS	243	void __init time_init(void)
eedbdab9 MS	244	{
5a26cd69	245	u32 irq;
eedbdab9 MS	246	u32 timer_num = 1;
eedbdab9 MS	247	struct device_node *timer = NULL;
ccea0e6e	248	const void *prop;
eedbdab9 MS	249	#ifdef CONFIG_SELFMOD_TIMER
	250	unsigned int timer_baseaddr = 0;
	251	int arr_func[] = {
	252	(int)&microblaze_read,
	253	(int)&timer_interrupt,
	254	(int)&microblaze_clocksource_init,
	255	(int)&microblaze_timer_set_mode,
	256	(int)&microblaze_timer_set_next_event,
	257	0
	258	};
	259	#endif
5a26cd69	260	timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
892ee92b	261	BUG_ON(!timer);
eedbdab9	262
02b08045	263	timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
eedbdab9	264	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
9d0ced00	265	irq = irq_of_parse_and_map(timer, 0);
02b08045 MS	266	timer_num = be32_to_cpup(of_get_property(timer,
02b08045 MS	267	"xlnx,one-timer-only", NULL));
eedbdab9	268	if (timer_num) {
b6d5b28e	269	printk(KERN_EMERG "Please enable two timers in HW\n");
eedbdab9 MS	270	BUG();
	271	}
	272
	273	#ifdef CONFIG_SELFMOD_TIMER
	274	selfmod_function((int *) arr_func, timer_baseaddr);
	275	#endif
5a26cd69 MS	276	printk(KERN_INFO "XPS timer #0 at 0x%08x, irq=%d\n",
5a26cd69 MS	277	timer_baseaddr, irq);
eedbdab9	278
ccea0e6e MS	279	/* If there is clock-frequency property than use it */
	280	prop = of_get_property(timer, "clock-frequency", NULL);
	281	if (prop)
	282	timer_clock_freq = be32_to_cpup(prop);
	283	else
	284	timer_clock_freq = cpuinfo.cpu_clock_freq;
	285
	286	freq_div_hz = timer_clock_freq / HZ;
eedbdab9 MS	287
	288	setup_irq(irq, &timer_irqaction);
	289	#ifdef CONFIG_HEART_BEAT
	290	setup_heartbeat();
	291	#endif
	292	microblaze_clocksource_init();
	293	microblaze_clockevent_init();
6f34b08f MS	294	timer_initialized = 1;
	295	}
	296
	297	unsigned long long notrace sched_clock(void)
	298	{
	299	if (timer_initialized) {
	300	struct clocksource *cs = &clocksource_microblaze;
9c6f6f54 MS	301
9c6f6f54 MS	302	cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX;
6f34b08f MS	303	return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	304	}
	305	return 0;
eedbdab9	306	}