Commit | Line | Data |
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4e07dba7 MS |
1 | #include <linux/linkage.h> |
2 | ||
3 | /* | |
4 | * modulo operation for 32 bit integers. | |
5 | * Input : op1 in Reg r5 | |
6 | * op2 in Reg r6 | |
7 | * Output: op1 mod op2 in Reg r3 | |
8 | */ | |
9 | ||
10 | .text | |
11 | .globl __modsi3 | |
12 | .type __modsi3, @function | |
13 | .ent __modsi3 | |
14 | ||
15 | __modsi3: | |
16 | .frame r1, 0, r15 | |
17 | ||
18 | addik r1, r1, -16 | |
19 | swi r28, r1, 0 | |
20 | swi r29, r1, 4 | |
21 | swi r30, r1, 8 | |
22 | swi r31, r1, 12 | |
23 | ||
24 | beqi r6, div_by_zero /* div_by_zero division error */ | |
25 | beqi r5, result_is_zero /* result is zero */ | |
26 | bgeid r5, r5_pos | |
27 | /* get the sign of the result [ depends only on the first arg] */ | |
28 | add r28, r5, r0 | |
29 | rsubi r5, r5, 0 /* make r5 positive */ | |
30 | r5_pos: | |
31 | bgei r6, r6_pos | |
32 | rsubi r6, r6, 0 /* make r6 positive */ | |
33 | r6_pos: | |
34 | addik r3, r0, 0 /* clear mod */ | |
35 | addik r30, r0, 0 /* clear div */ | |
36 | addik r29, r0, 32 /* initialize the loop count */ | |
37 | /* first part try to find the first '1' in the r5 */ | |
38 | div1: | |
39 | add r5, r5, r5 /* left shift logical r5 */ | |
40 | bgeid r5, div1 | |
41 | addik r29, r29, -1 | |
42 | div2: | |
43 | /* left shift logical r5 get the '1' into the carry */ | |
44 | add r5, r5, r5 | |
45 | addc r3, r3, r3 /* move that bit into the mod register */ | |
46 | rsub r31, r6, r3 /* try to subtract (r30 a r6) */ | |
47 | blti r31, mod_too_small | |
48 | /* move the r31 to mod since the result was positive */ | |
49 | or r3, r0, r31 | |
50 | addik r30, r30, 1 | |
51 | mod_too_small: | |
52 | addik r29, r29, -1 | |
53 | beqi r29, loop_end | |
54 | add r30, r30, r30 /* shift in the '1' into div */ | |
55 | bri div2 /* div2 */ | |
56 | loop_end: | |
57 | bgei r28, return_here | |
58 | brid return_here | |
59 | rsubi r3, r3, 0 /* negate the result */ | |
60 | div_by_zero: | |
61 | result_is_zero: | |
62 | or r3, r0, r0 /* set result to 0 [both mod as well as div are 0] */ | |
63 | return_here: | |
64 | /* restore values of csrs and that of r3 and the divisor and the dividend */ | |
65 | lwi r28, r1, 0 | |
66 | lwi r29, r1, 4 | |
67 | lwi r30, r1, 8 | |
68 | lwi r31, r1, 12 | |
69 | rtsd r15, 8 | |
70 | addik r1, r1, 16 | |
71 | ||
72 | .size __modsi3, . - __modsi3 | |
73 | .end __modsi3 |