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MIPS: Whitespace cleanup.
[deliverable/linux.git] / arch / mips / alchemy / devboards / db1000.c
CommitLineData
27dd65ac 1/*
851d4f5d 2 * DBAu1000/1500/1100 PBAu1100/1500 board support
27dd65ac 3 *
7c4b24da
ML		 4 * Copyright 2000, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
27dd65ac
ML		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
7c4b24da
ML		 22#include <linux/dma-mapping.h>
23#include <linux/gpio.h>
27dd65ac 24#include <linux/init.h>
b2ce305d 25#include <linux/interrupt.h>
c9af5144
ML		 26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/module.h>
27dd65ac 29#include <linux/platform_device.h>
7c4b24da 30#include <linux/pm.h>
2a32daf1
ML		 31#include <linux/spi/spi.h>
32#include <linux/spi/spi_gpio.h>
33#include <linux/spi/ads7846.h>
b2ce305d
ML		 34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1000_dma.h>
c9af5144 36#include <asm/mach-au1x00/au1100_mmc.h>
206aa6cd 37#include <asm/mach-db1x00/bcsr.h>
7c4b24da
ML		 38#include <asm/reboot.h>
39#include <prom.h>
40#include "platform.h"
27dd65ac 41
f59c811f
ML		 42#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
43
7517de34
ML		 44struct pci_dev;
45
f59c811f
ML		 46static const char *board_type_str(void)
47{
48 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
49 case BCSR_WHOAMI_DB1000:
50 return "DB1000";
51 case BCSR_WHOAMI_DB1500:
52 return "DB1500";
53 case BCSR_WHOAMI_DB1100:
54 return "DB1100";
851d4f5d
ML		 55 case BCSR_WHOAMI_PB1500:
56 case BCSR_WHOAMI_PB1500R2:
57 return "PB1500";
58 case BCSR_WHOAMI_PB1100:
59 return "PB1100";
f59c811f
ML		 60 default:
61 return "(unknown)";
62 }
63}
64
7c4b24da
ML		 65const char *get_system_type(void)
66{
f59c811f 67 return board_type_str();
7c4b24da
ML		 68}
69
70void __init board_setup(void)
71{
7c4b24da
ML		 72 /* initialize board register space */
73 bcsr_init(DB1000_BCSR_PHYS_ADDR,
74 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
75
f59c811f 76 printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
7c4b24da
ML		 77}
78
27dd65ac 79
f869d42e 80static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
7517de34
ML		 81{
82 if ((slot < 12) || (slot > 13) || pin == 0)
83 return -1;
84 if (slot == 12)
85 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
86 if (slot == 13) {
87 switch (pin) {
88 case 1: return AU1500_PCI_INTA;
89 case 2: return AU1500_PCI_INTB;
90 case 3: return AU1500_PCI_INTC;
91 case 4: return AU1500_PCI_INTD;
92 }
93 }
94 return -1;
95}
7517de34 96
7517de34
ML		 97static struct resource alchemy_pci_host_res[] = {
98 [0] = {
99 .start = AU1500_PCI_PHYS_ADDR,
100 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
101 .flags = IORESOURCE_MEM,
102 },
103};
104
f869d42e
ML		 105static struct alchemy_pci_platdata db1500_pci_pd = {
106 .board_map_irq = db1500_map_pci_irq,
7517de34
ML		 107};
108
f869d42e
ML		 109static struct platform_device db1500_pci_host_dev = {
110 .dev.platform_data = &db1500_pci_pd,
7517de34
ML		 111 .name = "alchemy-pci",
112 .id = 0,
113 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
114 .resource = alchemy_pci_host_res,
115};
116
f869d42e 117static int __init db1500_pci_init(void)
7517de34 118{
851d4f5d
ML		 119 int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
120 if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
121 (id == BCSR_WHOAMI_PB1500R2))
f59c811f
ML		 122 return platform_device_register(&db1500_pci_host_dev);
123 return 0;
7517de34
ML		 124}
125/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
f869d42e 126arch_initcall(db1500_pci_init);
7517de34 127
f59c811f 128
37663860
ML		 129static struct resource au1100_lcd_resources[] = {
130 [0] = {
131 .start = AU1100_LCD_PHYS_ADDR,
132 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 [1] = {
136 .start = AU1100_LCD_INT,
137 .end = AU1100_LCD_INT,
138 .flags = IORESOURCE_IRQ,
139 }
140};
141
142static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
143
144static struct platform_device au1100_lcd_device = {
145 .name = "au1100-lcd",
146 .id = 0,
147 .dev = {
148 .dma_mask = &au1100_lcd_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 },
151 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
152 .resource = au1100_lcd_resources,
153};
37663860 154
b2ce305d
ML		 155static struct resource alchemy_ac97c_res[] = {
156 [0] = {
157 .start = AU1000_AC97_PHYS_ADDR,
158 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
159 .flags = IORESOURCE_MEM,
160 },
161 [1] = {
162 .start = DMA_ID_AC97C_TX,
163 .end = DMA_ID_AC97C_TX,
164 .flags = IORESOURCE_DMA,
165 },
166 [2] = {
167 .start = DMA_ID_AC97C_RX,
168 .end = DMA_ID_AC97C_RX,
169 .flags = IORESOURCE_DMA,
170 },
171};
172
173static struct platform_device alchemy_ac97c_dev = {
174 .name = "alchemy-ac97c",
175 .id = -1,
176 .resource = alchemy_ac97c_res,
177 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
178};
179
180static struct platform_device alchemy_ac97c_dma_dev = {
181 .name = "alchemy-pcm-dma",
182 .id = 0,
183};
184
185static struct platform_device db1x00_codec_dev = {
186 .name = "ac97-codec",
187 .id = -1,
188};
189
190static struct platform_device db1x00_audio_dev = {
191 .name = "db1000-audio",
192};
193
c9af5144
ML		 194/******************************************************************************/
195
196static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
197{
198 void (*mmc_cd)(struct mmc_host *, unsigned long);
199 /* link against CONFIG_MMC=m */
200 mmc_cd = symbol_get(mmc_detect_change);
201 mmc_cd(ptr, msecs_to_jiffies(500));
202 symbol_put(mmc_detect_change);
203
204 return IRQ_HANDLED;
205}
206
207static int db1100_mmc_cd_setup(void *mmc_host, int en)
208{
851d4f5d
ML		 209 int ret = 0, irq;
210
211 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
212 irq = AU1100_GPIO19_INT;
213 else
214 irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */
c9af5144
ML		 215
216 if (en) {
851d4f5d
ML		 217 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
218 ret = request_irq(irq, db1100_mmc_cd, 0,
c9af5144
ML		 219 "sd0_cd", mmc_host);
220 } else
851d4f5d 221 free_irq(irq, mmc_host);
c9af5144
ML		 222 return ret;
223}
224
225static int db1100_mmc1_cd_setup(void *mmc_host, int en)
226{
851d4f5d
ML		 227 int ret = 0, irq;
228
229 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
230 irq = AU1100_GPIO20_INT;
231 else
232 irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */
c9af5144
ML		 233
234 if (en) {
851d4f5d
ML		 235 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
236 ret = request_irq(irq, db1100_mmc_cd, 0,
c9af5144
ML		 237 "sd1_cd", mmc_host);
238 } else
851d4f5d 239 free_irq(irq, mmc_host);
c9af5144
ML		 240 return ret;
241}
242
243static int db1100_mmc_card_readonly(void *mmc_host)
244{
245 /* testing suggests that this bit is inverted */
246 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
247}
248
249static int db1100_mmc_card_inserted(void *mmc_host)
250{
251 return !alchemy_gpio_get_value(19);
252}
253
254static void db1100_mmc_set_power(void *mmc_host, int state)
255{
851d4f5d
ML		 256 int bit;
257
258 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
259 bit = BCSR_BOARD_SD0PWR;
260 else
261 bit = BCSR_BOARD_PB1100_SD0PWR;
262
c9af5144 263 if (state) {
851d4f5d 264 bcsr_mod(BCSR_BOARD, 0, bit);
c9af5144
ML		 265 msleep(400); /* stabilization time */
266 } else
851d4f5d 267 bcsr_mod(BCSR_BOARD, bit, 0);
c9af5144
ML		 268}
269
270static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
271{
272 if (b != LED_OFF)
273 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
274 else
275 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
276}
277
278static struct led_classdev db1100_mmc_led = {
70342287 279 .brightness_set = db1100_mmcled_set,
c9af5144
ML		 280};
281
282static int db1100_mmc1_card_readonly(void *mmc_host)
283{
284 return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
285}
286
287static int db1100_mmc1_card_inserted(void *mmc_host)
288{
289 return !alchemy_gpio_get_value(20);
290}
291
292static void db1100_mmc1_set_power(void *mmc_host, int state)
293{
851d4f5d
ML		 294 int bit;
295
296 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
297 bit = BCSR_BOARD_SD1PWR;
298 else
299 bit = BCSR_BOARD_PB1100_SD1PWR;
300
c9af5144 301 if (state) {
851d4f5d 302 bcsr_mod(BCSR_BOARD, 0, bit);
c9af5144
ML		 303 msleep(400); /* stabilization time */
304 } else
851d4f5d 305 bcsr_mod(BCSR_BOARD, bit, 0);
c9af5144
ML		 306}
307
308static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
309{
310 if (b != LED_OFF)
311 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
312 else
313 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
314}
315
316static struct led_classdev db1100_mmc1_led = {
70342287 317 .brightness_set = db1100_mmc1led_set,
c9af5144
ML		 318};
319
320static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
321 [0] = {
322 .cd_setup = db1100_mmc_cd_setup,
323 .set_power = db1100_mmc_set_power,
324 .card_inserted = db1100_mmc_card_inserted,
325 .card_readonly = db1100_mmc_card_readonly,
326 .led = &db1100_mmc_led,
327 },
328 [1] = {
329 .cd_setup = db1100_mmc1_cd_setup,
330 .set_power = db1100_mmc1_set_power,
331 .card_inserted = db1100_mmc1_card_inserted,
332 .card_readonly = db1100_mmc1_card_readonly,
333 .led = &db1100_mmc1_led,
334 },
335};
336
337static struct resource au1100_mmc0_resources[] = {
338 [0] = {
339 .start = AU1100_SD0_PHYS_ADDR,
340 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
341 .flags = IORESOURCE_MEM,
342 },
343 [1] = {
344 .start = AU1100_SD_INT,
345 .end = AU1100_SD_INT,
346 .flags = IORESOURCE_IRQ,
347 },
348 [2] = {
349 .start = DMA_ID_SD0_TX,
350 .end = DMA_ID_SD0_TX,
351 .flags = IORESOURCE_DMA,
352 },
353 [3] = {
354 .start = DMA_ID_SD0_RX,
355 .end = DMA_ID_SD0_RX,
356 .flags = IORESOURCE_DMA,
357 }
358};
359
70342287 360static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
c9af5144
ML		 361
362static struct platform_device db1100_mmc0_dev = {
363 .name = "au1xxx-mmc",
364 .id = 0,
365 .dev = {
366 .dma_mask = &au1xxx_mmc_dmamask,
367 .coherent_dma_mask = DMA_BIT_MASK(32),
368 .platform_data = &db1100_mmc_platdata[0],
369 },
370 .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
371 .resource = au1100_mmc0_resources,
372};
373
374static struct resource au1100_mmc1_res[] = {
375 [0] = {
376 .start = AU1100_SD1_PHYS_ADDR,
377 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = AU1100_SD_INT,
382 .end = AU1100_SD_INT,
383 .flags = IORESOURCE_IRQ,
384 },
385 [2] = {
386 .start = DMA_ID_SD1_TX,
387 .end = DMA_ID_SD1_TX,
388 .flags = IORESOURCE_DMA,
389 },
390 [3] = {
391 .start = DMA_ID_SD1_RX,
392 .end = DMA_ID_SD1_RX,
393 .flags = IORESOURCE_DMA,
394 }
395};
396
397static struct platform_device db1100_mmc1_dev = {
398 .name = "au1xxx-mmc",
399 .id = 1,
400 .dev = {
401 .dma_mask = &au1xxx_mmc_dmamask,
402 .coherent_dma_mask = DMA_BIT_MASK(32),
403 .platform_data = &db1100_mmc_platdata[1],
404 },
405 .num_resources = ARRAY_SIZE(au1100_mmc1_res),
406 .resource = au1100_mmc1_res,
407};
408
e734ae13
ML		 409/******************************************************************************/
410
411static void db1000_irda_set_phy_mode(int mode)
412{
413 unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
414
415 switch (mode) {
416 case AU1000_IRDA_PHY_MODE_OFF:
417 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
418 break;
419 case AU1000_IRDA_PHY_MODE_SIR:
420 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
421 break;
422 case AU1000_IRDA_PHY_MODE_FIR:
423 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
424 BCSR_RESETS_FIR_SEL);
425 break;
426 }
427}
428
429static struct au1k_irda_platform_data db1000_irda_platdata = {
430 .set_phy_mode = db1000_irda_set_phy_mode,
431};
432
433static struct resource au1000_irda_res[] = {
434 [0] = {
435 .start = AU1000_IRDA_PHYS_ADDR,
436 .end = AU1000_IRDA_PHYS_ADDR + 0x0fff,
437 .flags = IORESOURCE_MEM,
438 },
439 [1] = {
440 .start = AU1000_IRDA_TX_INT,
441 .end = AU1000_IRDA_TX_INT,
442 .flags = IORESOURCE_IRQ,
443 },
444 [2] = {
445 .start = AU1000_IRDA_RX_INT,
446 .end = AU1000_IRDA_RX_INT,
447 .flags = IORESOURCE_IRQ,
448 },
449};
450
451static struct platform_device db1000_irda_dev = {
452 .name = "au1000-irda",
453 .id = -1,
454 .dev = {
455 .platform_data = &db1000_irda_platdata,
456 },
457 .resource = au1000_irda_res,
458 .num_resources = ARRAY_SIZE(au1000_irda_res),
459};
c9af5144 460
2a32daf1
ML		 461/******************************************************************************/
462
463static struct ads7846_platform_data db1100_touch_pd = {
464 .model = 7846,
465 .vref_mv = 3300,
466 .gpio_pendown = 21,
467};
468
469static struct spi_gpio_platform_data db1100_spictl_pd = {
470 .sck = 209,
471 .mosi = 208,
472 .miso = 207,
473 .num_chipselect = 1,
474};
475
476static struct spi_board_info db1100_spi_info[] __initdata = {
477 [0] = {
478 .modalias = "ads7846",
479 .max_speed_hz = 3250000,
480 .bus_num = 0,
481 .chip_select = 0,
482 .mode = 0,
483 .irq = AU1100_GPIO21_INT,
484 .platform_data = &db1100_touch_pd,
70342287 485 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
2a32daf1
ML		 486 },
487};
488
489static struct platform_device db1100_spi_dev = {
490 .name = "spi_gpio",
491 .id = 0,
492 .dev = {
493 .platform_data = &db1100_spictl_pd,
494 },
495};
496
497
f59c811f
ML		 498static struct platform_device *db1x00_devs[] = {
499 &db1x00_codec_dev,
500 &alchemy_ac97c_dma_dev,
501 &alchemy_ac97c_dev,
502 &db1x00_audio_dev,
503};
504
e734ae13
ML		 505static struct platform_device *db1000_devs[] = {
506 &db1000_irda_dev,
507};
508
f59c811f
ML		 509static struct platform_device *db1100_devs[] = {
510 &au1100_lcd_device,
c9af5144
ML		 511 &db1100_mmc0_dev,
512 &db1100_mmc1_dev,
e734ae13 513 &db1000_irda_dev,
f59c811f
ML		 514};
515
516static int __init db1000_dev_init(void)
27dd65ac 517{
f59c811f 518 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
851d4f5d 519 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
2a32daf1 520 unsigned long pfc;
f59c811f
ML		 521
522 if (board == BCSR_WHOAMI_DB1500) {
523 c0 = AU1500_GPIO2_INT;
524 c1 = AU1500_GPIO5_INT;
525 d0 = AU1500_GPIO0_INT;
526 d1 = AU1500_GPIO3_INT;
527 s0 = AU1500_GPIO1_INT;
528 s1 = AU1500_GPIO4_INT;
529 } else if (board == BCSR_WHOAMI_DB1100) {
530 c0 = AU1100_GPIO2_INT;
531 c1 = AU1100_GPIO5_INT;
532 d0 = AU1100_GPIO0_INT;
533 d1 = AU1100_GPIO3_INT;
534 s0 = AU1100_GPIO1_INT;
535 s1 = AU1100_GPIO4_INT;
c9af5144
ML		 536
537 gpio_direction_input(19); /* sd0 cd# */
538 gpio_direction_input(20); /* sd1 cd# */
2a32daf1
ML		 539 gpio_direction_input(21); /* touch pendown# */
540 gpio_direction_input(207); /* SPI MISO */
541 gpio_direction_output(208, 0); /* SPI MOSI */
542 gpio_direction_output(209, 1); /* SPI SCK */
543 gpio_direction_output(210, 1); /* SPI CS# */
544
545 /* spi_gpio on SSI0 pins */
546 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
547 pfc |= (1 << 0); /* SSI0 pins as GPIOs */
548 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
549 wmb();
550
551 spi_register_board_info(db1100_spi_info,
552 ARRAY_SIZE(db1100_spi_info));
c9af5144 553
f59c811f 554 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
851d4f5d 555 platform_device_register(&db1100_spi_dev);
f59c811f
ML		 556 } else if (board == BCSR_WHOAMI_DB1000) {
557 c0 = AU1000_GPIO2_INT;
558 c1 = AU1000_GPIO5_INT;
559 d0 = AU1000_GPIO0_INT;
560 d1 = AU1000_GPIO3_INT;
561 s0 = AU1000_GPIO1_INT;
562 s1 = AU1000_GPIO4_INT;
e734ae13 563 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
851d4f5d
ML		 564 } else if ((board == BCSR_WHOAMI_PB1500) ||
565 (board == BCSR_WHOAMI_PB1500R2)) {
566 c0 = AU1500_GPIO203_INT;
567 d0 = AU1500_GPIO201_INT;
568 s0 = AU1500_GPIO202_INT;
569 twosocks = 0;
570 flashsize = 64;
571 /* RTC and daughtercard irqs */
572 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
573 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
574 /* EPSON S1D13806 0x1b000000
70342287 575 * SRAM 1MB/2MB 0x1a000000
851d4f5d
ML		 576 * DS1693 RTC 0x0c000000
577 */
578 } else if (board == BCSR_WHOAMI_PB1100) {
579 c0 = AU1100_GPIO11_INT;
580 d0 = AU1100_GPIO9_INT;
581 s0 = AU1100_GPIO10_INT;
582 twosocks = 0;
583 flashsize = 64;
584 /* pendown, rtc, daughtercard irqs */
585 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
586 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
587 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
588 /* EPSON S1D13806 0x1b000000
70342287 589 * SRAM 1MB/2MB 0x1a000000
851d4f5d
ML		 590 * DiskOnChip 0x0d000000
591 * DS1693 RTC 0x0c000000
592 */
593 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
f59c811f
ML		 594 } else
595 return 0; /* unknown board, no further dev setup to do */
596
597 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
f59c811f 598 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
f59c811f 599 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
7c4b24da 600
7cc2e272
ML		 601 db1x_register_pcmcia_socket(
602 AU1000_PCMCIA_ATTR_PHYS_ADDR,
603 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
604 AU1000_PCMCIA_MEM_PHYS_ADDR,
605 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
606 AU1000_PCMCIA_IO_PHYS_ADDR,
607 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
70342287 608 c0, d0, /*s0*/0, 0, 0);
27dd65ac 609
851d4f5d
ML		 610 if (twosocks) {
611 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
612 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
613 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
614
615 db1x_register_pcmcia_socket(
616 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
617 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
618 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
619 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
620 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
621 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
70342287 622 c1, d1, /*s1*/0, 0, 1);
851d4f5d 623 }
b2ce305d 624
f59c811f 625 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
851d4f5d 626 db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
27dd65ac
ML		 627 return 0;
628}
f59c811f 629device_initcall(db1000_dev_init);
Linux kernel - Deliverables
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