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e2dbdc43 GJ |
1 | /* |
2 | * Atheros AR71XX/AR724X specific PCI setup code | |
3 | * | |
4 | * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> | |
e9b62e8e GJ |
5 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
6 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
7 | * | |
8 | * Parts of this file are based on Atheros' 2.6.15 BSP | |
e2dbdc43 GJ |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | */ | |
14 | ||
d22ce25f | 15 | #include <linux/init.h> |
e2dbdc43 | 16 | #include <linux/pci.h> |
9fc1ca5b GJ |
17 | #include <linux/resource.h> |
18 | #include <linux/platform_device.h> | |
ec950259 | 19 | #include <asm/mach-ath79/ar71xx_regs.h> |
6335aef5 | 20 | #include <asm/mach-ath79/ath79.h> |
4c07c7df | 21 | #include <asm/mach-ath79/irq.h> |
3a6208df | 22 | #include "pci.h" |
e2dbdc43 | 23 | |
a68ad4d8 | 24 | static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); |
d22ce25f GJ |
25 | static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; |
26 | static unsigned ath79_pci_nr_irqs __initdata; | |
e2dbdc43 | 27 | |
d22ce25f GJ |
28 | static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { |
29 | { | |
30 | .slot = 17, | |
31 | .pin = 1, | |
32 | .irq = ATH79_PCI_IRQ(0), | |
33 | }, { | |
34 | .slot = 18, | |
35 | .pin = 1, | |
36 | .irq = ATH79_PCI_IRQ(1), | |
37 | }, { | |
38 | .slot = 19, | |
39 | .pin = 1, | |
40 | .irq = ATH79_PCI_IRQ(2), | |
41 | } | |
42 | }; | |
43 | ||
44 | static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { | |
45 | { | |
46 | .slot = 0, | |
47 | .pin = 1, | |
48 | .irq = ATH79_PCI_IRQ(0), | |
49 | } | |
50 | }; | |
51 | ||
0a5f3b1c GJ |
52 | static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { |
53 | { | |
54 | .bus = 0, | |
55 | .slot = 0, | |
56 | .pin = 1, | |
57 | .irq = ATH79_PCI_IRQ(0), | |
58 | }, | |
59 | { | |
60 | .bus = 1, | |
61 | .slot = 0, | |
62 | .pin = 1, | |
63 | .irq = ATH79_PCI_IRQ(1), | |
64 | }, | |
65 | }; | |
66 | ||
e2dbdc43 GJ |
67 | int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) |
68 | { | |
e2dbdc43 | 69 | int irq = -1; |
d22ce25f GJ |
70 | int i; |
71 | ||
72 | if (ath79_pci_nr_irqs == 0 || | |
73 | ath79_pci_irq_map == NULL) { | |
74 | if (soc_is_ar71xx()) { | |
75 | ath79_pci_irq_map = ar71xx_pci_irq_map; | |
76 | ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); | |
ec950259 GJ |
77 | } else if (soc_is_ar724x() || |
78 | soc_is_ar9342() || | |
79 | soc_is_ar9344()) { | |
d22ce25f GJ |
80 | ath79_pci_irq_map = ar724x_pci_irq_map; |
81 | ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); | |
0a5f3b1c GJ |
82 | } else if (soc_is_qca955x()) { |
83 | ath79_pci_irq_map = qca955x_pci_irq_map; | |
84 | ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); | |
d22ce25f GJ |
85 | } else { |
86 | pr_crit("pci %s: invalid irq map\n", | |
87 | pci_name((struct pci_dev *) dev)); | |
88 | return irq; | |
89 | } | |
90 | } | |
91 | ||
92 | for (i = 0; i < ath79_pci_nr_irqs; i++) { | |
93 | const struct ath79_pci_irq *entry; | |
e2dbdc43 | 94 | |
d22ce25f | 95 | entry = &ath79_pci_irq_map[i]; |
617fed41 GJ |
96 | if (entry->bus == dev->bus->number && |
97 | entry->slot == slot && | |
98 | entry->pin == pin) { | |
d22ce25f GJ |
99 | irq = entry->irq; |
100 | break; | |
101 | } | |
102 | } | |
e2dbdc43 | 103 | |
d22ce25f GJ |
104 | if (irq < 0) |
105 | pr_crit("pci %s: no irq found for pin %u\n", | |
106 | pci_name((struct pci_dev *) dev), pin); | |
107 | else | |
108 | pr_info("pci %s: using irq %d for pin %u\n", | |
109 | pci_name((struct pci_dev *) dev), irq, pin); | |
e2dbdc43 GJ |
110 | |
111 | return irq; | |
112 | } | |
113 | ||
114 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
115 | { | |
a68ad4d8 GJ |
116 | if (ath79_pci_plat_dev_init) |
117 | return ath79_pci_plat_dev_init(dev); | |
e2dbdc43 | 118 | |
a68ad4d8 GJ |
119 | return 0; |
120 | } | |
e2dbdc43 | 121 | |
d22ce25f GJ |
122 | void __init ath79_pci_set_irq_map(unsigned nr_irqs, |
123 | const struct ath79_pci_irq *map) | |
124 | { | |
125 | ath79_pci_nr_irqs = nr_irqs; | |
126 | ath79_pci_irq_map = map; | |
127 | } | |
128 | ||
a68ad4d8 GJ |
129 | void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) |
130 | { | |
131 | ath79_pci_plat_dev_init = func; | |
e2dbdc43 | 132 | } |
6335aef5 | 133 | |
9fc1ca5b GJ |
134 | static struct platform_device * |
135 | ath79_register_pci_ar71xx(void) | |
136 | { | |
137 | struct platform_device *pdev; | |
42cb60d1 | 138 | struct resource res[4]; |
9fc1ca5b GJ |
139 | |
140 | memset(res, 0, sizeof(res)); | |
141 | ||
142 | res[0].name = "cfg_base"; | |
143 | res[0].flags = IORESOURCE_MEM; | |
144 | res[0].start = AR71XX_PCI_CFG_BASE; | |
145 | res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; | |
146 | ||
147 | res[1].flags = IORESOURCE_IRQ; | |
7e69c10a GJ |
148 | res[1].start = ATH79_CPU_IRQ(2); |
149 | res[1].end = ATH79_CPU_IRQ(2); | |
9fc1ca5b | 150 | |
42cb60d1 GJ |
151 | res[2].name = "io_base"; |
152 | res[2].flags = IORESOURCE_IO; | |
153 | res[2].start = 0; | |
154 | res[2].end = 0; | |
155 | ||
156 | res[3].name = "mem_base"; | |
157 | res[3].flags = IORESOURCE_MEM; | |
158 | res[3].start = AR71XX_PCI_MEM_BASE; | |
159 | res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; | |
160 | ||
9fc1ca5b GJ |
161 | pdev = platform_device_register_simple("ar71xx-pci", -1, |
162 | res, ARRAY_SIZE(res)); | |
163 | return pdev; | |
164 | } | |
165 | ||
166 | static struct platform_device * | |
167 | ath79_register_pci_ar724x(int id, | |
168 | unsigned long cfg_base, | |
169 | unsigned long ctrl_base, | |
12401fc2 | 170 | unsigned long crp_base, |
34b134ae GJ |
171 | unsigned long mem_base, |
172 | unsigned long mem_size, | |
173 | unsigned long io_base, | |
9fc1ca5b | 174 | int irq) |
6335aef5 | 175 | { |
9fc1ca5b | 176 | struct platform_device *pdev; |
12401fc2 | 177 | struct resource res[6]; |
d22ce25f | 178 | |
9fc1ca5b | 179 | memset(res, 0, sizeof(res)); |
6335aef5 | 180 | |
9fc1ca5b GJ |
181 | res[0].name = "cfg_base"; |
182 | res[0].flags = IORESOURCE_MEM; | |
183 | res[0].start = cfg_base; | |
184 | res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; | |
185 | ||
186 | res[1].name = "ctrl_base"; | |
187 | res[1].flags = IORESOURCE_MEM; | |
188 | res[1].start = ctrl_base; | |
189 | res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; | |
190 | ||
191 | res[2].flags = IORESOURCE_IRQ; | |
192 | res[2].start = irq; | |
193 | res[2].end = irq; | |
194 | ||
34b134ae GJ |
195 | res[3].name = "mem_base"; |
196 | res[3].flags = IORESOURCE_MEM; | |
197 | res[3].start = mem_base; | |
198 | res[3].end = mem_base + mem_size - 1; | |
199 | ||
200 | res[4].name = "io_base"; | |
201 | res[4].flags = IORESOURCE_IO; | |
202 | res[4].start = io_base; | |
203 | res[4].end = io_base; | |
204 | ||
12401fc2 GJ |
205 | res[5].name = "crp_base"; |
206 | res[5].flags = IORESOURCE_MEM; | |
207 | res[5].start = crp_base; | |
208 | res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; | |
209 | ||
9fc1ca5b GJ |
210 | pdev = platform_device_register_simple("ar724x-pci", id, |
211 | res, ARRAY_SIZE(res)); | |
212 | return pdev; | |
213 | } | |
214 | ||
215 | int __init ath79_register_pci(void) | |
216 | { | |
217 | struct platform_device *pdev = NULL; | |
218 | ||
219 | if (soc_is_ar71xx()) { | |
220 | pdev = ath79_register_pci_ar71xx(); | |
221 | } else if (soc_is_ar724x()) { | |
222 | pdev = ath79_register_pci_ar724x(-1, | |
223 | AR724X_PCI_CFG_BASE, | |
224 | AR724X_PCI_CTRL_BASE, | |
12401fc2 | 225 | AR724X_PCI_CRP_BASE, |
34b134ae GJ |
226 | AR724X_PCI_MEM_BASE, |
227 | AR724X_PCI_MEM_SIZE, | |
228 | 0, | |
7e69c10a | 229 | ATH79_CPU_IRQ(2)); |
9fc1ca5b GJ |
230 | } else if (soc_is_ar9342() || |
231 | soc_is_ar9344()) { | |
ec950259 GJ |
232 | u32 bootstrap; |
233 | ||
234 | bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); | |
9fc1ca5b GJ |
235 | if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) |
236 | return -ENODEV; | |
237 | ||
238 | pdev = ath79_register_pci_ar724x(-1, | |
239 | AR724X_PCI_CFG_BASE, | |
240 | AR724X_PCI_CTRL_BASE, | |
12401fc2 | 241 | AR724X_PCI_CRP_BASE, |
34b134ae GJ |
242 | AR724X_PCI_MEM_BASE, |
243 | AR724X_PCI_MEM_SIZE, | |
244 | 0, | |
9fc1ca5b | 245 | ATH79_IP2_IRQ(0)); |
0a5f3b1c GJ |
246 | } else if (soc_is_qca9558()) { |
247 | pdev = ath79_register_pci_ar724x(0, | |
248 | QCA955X_PCI_CFG_BASE0, | |
249 | QCA955X_PCI_CTRL_BASE0, | |
250 | QCA955X_PCI_CRP_BASE0, | |
251 | QCA955X_PCI_MEM_BASE0, | |
252 | QCA955X_PCI_MEM_SIZE, | |
253 | 0, | |
254 | ATH79_IP2_IRQ(0)); | |
255 | ||
256 | pdev = ath79_register_pci_ar724x(1, | |
257 | QCA955X_PCI_CFG_BASE1, | |
258 | QCA955X_PCI_CTRL_BASE1, | |
259 | QCA955X_PCI_CRP_BASE1, | |
260 | QCA955X_PCI_MEM_BASE1, | |
261 | QCA955X_PCI_MEM_SIZE, | |
262 | 1, | |
263 | ATH79_IP3_IRQ(2)); | |
9fc1ca5b GJ |
264 | } else { |
265 | /* No PCI support */ | |
266 | return -ENODEV; | |
ec950259 GJ |
267 | } |
268 | ||
9fc1ca5b GJ |
269 | if (!pdev) |
270 | pr_err("unable to register PCI controller device\n"); | |
271 | ||
272 | return pdev ? 0 : -ENODEV; | |
6335aef5 | 273 | } |