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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * The Descriptor Based DMA channel manager that first appeared | |
5 | * on the Au1550. I started with dma.c, but I think all that is | |
6 | * left is this initial comment :-) | |
7 | * | |
8 | * Copyright 2004 Embedded Edge, LLC | |
9 | * dan@embeddededge.com | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | */ | |
32 | #include <linux/config.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/string.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <asm/mach-au1x00/au1000.h> | |
42 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
43 | #include <asm/system.h> | |
44 | ||
45 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | |
46 | ||
47 | /* | |
48 | * The Descriptor Based DMA supports up to 16 channels. | |
49 | * | |
50 | * There are 32 devices defined. We keep an internal structure | |
51 | * of devices using these channels, along with additional | |
52 | * information. | |
53 | * | |
54 | * We allocate the descriptors and allow access to them through various | |
55 | * functions. The drivers allocate the data buffers and assign them | |
56 | * to the descriptors. | |
57 | */ | |
58 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); | |
59 | ||
60 | /* I couldn't find a macro that did this...... | |
61 | */ | |
62 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) | |
63 | ||
64 | static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; | |
65 | static int dbdma_initialized; | |
66 | static void au1xxx_dbdma_init(void); | |
67 | ||
68 | typedef struct dbdma_device_table { | |
69 | u32 dev_id; | |
70 | u32 dev_flags; | |
71 | u32 dev_tsize; | |
72 | u32 dev_devwidth; | |
73 | u32 dev_physaddr; /* If FIFO */ | |
74 | u32 dev_intlevel; | |
75 | u32 dev_intpolarity; | |
76 | } dbdev_tab_t; | |
77 | ||
78 | typedef struct dbdma_chan_config { | |
79 | u32 chan_flags; | |
80 | u32 chan_index; | |
81 | dbdev_tab_t *chan_src; | |
82 | dbdev_tab_t *chan_dest; | |
83 | au1x_dma_chan_t *chan_ptr; | |
84 | au1x_ddma_desc_t *chan_desc_base; | |
85 | au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; | |
86 | void *chan_callparam; | |
87 | void (*chan_callback)(int, void *, struct pt_regs *); | |
88 | } chan_tab_t; | |
89 | ||
90 | #define DEV_FLAGS_INUSE (1 << 0) | |
91 | #define DEV_FLAGS_ANYUSE (1 << 1) | |
92 | #define DEV_FLAGS_OUT (1 << 2) | |
93 | #define DEV_FLAGS_IN (1 << 3) | |
94 | ||
95 | static dbdev_tab_t dbdev_tab[] = { | |
96 | #ifdef CONFIG_SOC_AU1550 | |
97 | /* UARTS */ | |
98 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
99 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
100 | { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, | |
101 | { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, | |
102 | ||
103 | /* EXT DMA */ | |
104 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
105 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
106 | { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, | |
107 | { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, | |
108 | ||
109 | /* USB DEV */ | |
110 | { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, | |
111 | { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, | |
112 | { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, | |
113 | { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, | |
114 | { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, | |
115 | { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, | |
116 | ||
117 | /* PSC 0 */ | |
118 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, | |
119 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, | |
120 | ||
121 | /* PSC 1 */ | |
122 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, | |
123 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, | |
124 | ||
125 | /* PSC 2 */ | |
126 | { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, | |
127 | { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, | |
128 | ||
129 | /* PSC 3 */ | |
130 | { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, | |
131 | { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, | |
132 | ||
133 | { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ | |
134 | { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ | |
135 | ||
136 | /* MAC 0 */ | |
137 | { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
138 | { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
139 | ||
140 | /* MAC 1 */ | |
141 | { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
142 | { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
143 | ||
144 | #endif /* CONFIG_SOC_AU1550 */ | |
145 | ||
146 | #ifdef CONFIG_SOC_AU1200 | |
147 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
148 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
149 | { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, | |
150 | { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, | |
151 | ||
152 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
153 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
154 | ||
155 | { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
156 | { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
157 | { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
158 | { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
159 | ||
160 | { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
161 | { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
162 | { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
163 | { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
164 | ||
165 | { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
166 | { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
167 | ||
168 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, | |
169 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, | |
170 | { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
171 | ||
172 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, | |
173 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, | |
174 | { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
175 | ||
176 | { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
177 | { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
178 | { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
179 | { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
180 | ||
181 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
182 | ||
183 | #endif // CONFIG_SOC_AU1200 | |
184 | ||
185 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
186 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
187 | }; | |
188 | ||
189 | #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) | |
190 | ||
191 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; | |
192 | ||
193 | static dbdev_tab_t * | |
194 | find_dbdev_id (u32 id) | |
195 | { | |
196 | int i; | |
197 | dbdev_tab_t *p; | |
198 | for (i = 0; i < DBDEV_TAB_SIZE; ++i) { | |
199 | p = &dbdev_tab[i]; | |
200 | if (p->dev_id == id) | |
201 | return p; | |
202 | } | |
203 | return NULL; | |
204 | } | |
205 | ||
206 | /* Allocate a channel and return a non-zero descriptor if successful. | |
207 | */ | |
208 | u32 | |
209 | au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |
210 | void (*callback)(int, void *, struct pt_regs *), void *callparam) | |
211 | { | |
212 | unsigned long flags; | |
213 | u32 used, chan, rv; | |
214 | u32 dcp; | |
215 | int i; | |
216 | dbdev_tab_t *stp, *dtp; | |
217 | chan_tab_t *ctp; | |
218 | volatile au1x_dma_chan_t *cp; | |
219 | ||
220 | /* We do the intialization on the first channel allocation. | |
221 | * We have to wait because of the interrupt handler initialization | |
222 | * which can't be done successfully during board set up. | |
223 | */ | |
224 | if (!dbdma_initialized) | |
225 | au1xxx_dbdma_init(); | |
226 | dbdma_initialized = 1; | |
227 | ||
228 | if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS)) | |
229 | return 0; | |
230 | ||
231 | if ((stp = find_dbdev_id(srcid)) == NULL) return 0; | |
232 | if ((dtp = find_dbdev_id(destid)) == NULL) return 0; | |
233 | ||
234 | used = 0; | |
235 | rv = 0; | |
236 | ||
237 | /* Check to see if we can get both channels. | |
238 | */ | |
239 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
240 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || | |
241 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
242 | /* Got source */ | |
243 | stp->dev_flags |= DEV_FLAGS_INUSE; | |
244 | if (!(dtp->dev_flags & DEV_FLAGS_INUSE) || | |
245 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
246 | /* Got destination */ | |
247 | dtp->dev_flags |= DEV_FLAGS_INUSE; | |
248 | } | |
249 | else { | |
250 | /* Can't get dest. Release src. | |
251 | */ | |
252 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
253 | used++; | |
254 | } | |
255 | } | |
256 | else { | |
257 | used++; | |
258 | } | |
259 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | |
260 | ||
261 | if (!used) { | |
262 | /* Let's see if we can allocate a channel for it. | |
263 | */ | |
264 | ctp = NULL; | |
265 | chan = 0; | |
266 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
267 | for (i=0; i<NUM_DBDMA_CHANS; i++) { | |
268 | if (chan_tab_ptr[i] == NULL) { | |
269 | /* If kmalloc fails, it is caught below same | |
270 | * as a channel not available. | |
271 | */ | |
272 | ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); | |
273 | chan_tab_ptr[i] = ctp; | |
274 | ctp->chan_index = chan = i; | |
275 | break; | |
276 | } | |
277 | } | |
278 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | |
279 | ||
280 | if (ctp != NULL) { | |
281 | memset(ctp, 0, sizeof(chan_tab_t)); | |
282 | dcp = DDMA_CHANNEL_BASE; | |
283 | dcp += (0x0100 * chan); | |
284 | ctp->chan_ptr = (au1x_dma_chan_t *)dcp; | |
285 | cp = (volatile au1x_dma_chan_t *)dcp; | |
286 | ctp->chan_src = stp; | |
287 | ctp->chan_dest = dtp; | |
288 | ctp->chan_callback = callback; | |
289 | ctp->chan_callparam = callparam; | |
290 | ||
291 | /* Initialize channel configuration. | |
292 | */ | |
293 | i = 0; | |
294 | if (stp->dev_intlevel) | |
295 | i |= DDMA_CFG_SED; | |
296 | if (stp->dev_intpolarity) | |
297 | i |= DDMA_CFG_SP; | |
298 | if (dtp->dev_intlevel) | |
299 | i |= DDMA_CFG_DED; | |
300 | if (dtp->dev_intpolarity) | |
301 | i |= DDMA_CFG_DP; | |
302 | cp->ddma_cfg = i; | |
303 | au_sync(); | |
304 | ||
305 | /* Return a non-zero value that can be used to | |
306 | * find the channel information in subsequent | |
307 | * operations. | |
308 | */ | |
309 | rv = (u32)(&chan_tab_ptr[chan]); | |
310 | } | |
311 | else { | |
312 | /* Release devices. | |
313 | */ | |
314 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
315 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
316 | } | |
317 | } | |
318 | return rv; | |
319 | } | |
320 | ||
321 | /* Set the device width if source or destination is a FIFO. | |
322 | * Should be 8, 16, or 32 bits. | |
323 | */ | |
324 | u32 | |
325 | au1xxx_dbdma_set_devwidth(u32 chanid, int bits) | |
326 | { | |
327 | u32 rv; | |
328 | chan_tab_t *ctp; | |
329 | dbdev_tab_t *stp, *dtp; | |
330 | ||
331 | ctp = *((chan_tab_t **)chanid); | |
332 | stp = ctp->chan_src; | |
333 | dtp = ctp->chan_dest; | |
334 | rv = 0; | |
335 | ||
336 | if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */ | |
337 | rv = stp->dev_devwidth; | |
338 | stp->dev_devwidth = bits; | |
339 | } | |
340 | if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */ | |
341 | rv = dtp->dev_devwidth; | |
342 | dtp->dev_devwidth = bits; | |
343 | } | |
344 | ||
345 | return rv; | |
346 | } | |
347 | ||
348 | /* Allocate a descriptor ring, initializing as much as possible. | |
349 | */ | |
350 | u32 | |
351 | au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |
352 | { | |
353 | int i; | |
354 | u32 desc_base, srcid, destid; | |
355 | u32 cmd0, cmd1, src1, dest1; | |
356 | u32 src0, dest0; | |
357 | chan_tab_t *ctp; | |
358 | dbdev_tab_t *stp, *dtp; | |
359 | au1x_ddma_desc_t *dp; | |
360 | ||
361 | /* I guess we could check this to be within the | |
362 | * range of the table...... | |
363 | */ | |
364 | ctp = *((chan_tab_t **)chanid); | |
365 | stp = ctp->chan_src; | |
366 | dtp = ctp->chan_dest; | |
367 | ||
368 | /* The descriptors must be 32-byte aligned. There is a | |
369 | * possibility the allocation will give us such an address, | |
370 | * and if we try that first we are likely to not waste larger | |
371 | * slabs of memory. | |
372 | */ | |
373 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); | |
374 | if (desc_base == 0) | |
375 | return 0; | |
376 | ||
377 | if (desc_base & 0x1f) { | |
378 | /* Lost....do it again, allocate extra, and round | |
379 | * the address base. | |
380 | */ | |
381 | kfree((const void *)desc_base); | |
382 | i = entries * sizeof(au1x_ddma_desc_t); | |
383 | i += (sizeof(au1x_ddma_desc_t) - 1); | |
384 | if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) | |
385 | return 0; | |
386 | ||
387 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); | |
388 | } | |
389 | dp = (au1x_ddma_desc_t *)desc_base; | |
390 | ||
391 | /* Keep track of the base descriptor. | |
392 | */ | |
393 | ctp->chan_desc_base = dp; | |
394 | ||
395 | /* Initialize the rings with as much information as we know. | |
396 | */ | |
397 | srcid = stp->dev_id; | |
398 | destid = dtp->dev_id; | |
399 | ||
400 | cmd0 = cmd1 = src1 = dest1 = 0; | |
401 | src0 = dest0 = 0; | |
402 | ||
403 | cmd0 |= DSCR_CMD0_SID(srcid); | |
404 | cmd0 |= DSCR_CMD0_DID(destid); | |
405 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; | |
406 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT); | |
407 | ||
408 | switch (stp->dev_devwidth) { | |
409 | case 8: | |
410 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE); | |
411 | break; | |
412 | case 16: | |
413 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD); | |
414 | break; | |
415 | case 32: | |
416 | default: | |
417 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD); | |
418 | break; | |
419 | } | |
420 | ||
421 | switch (dtp->dev_devwidth) { | |
422 | case 8: | |
423 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE); | |
424 | break; | |
425 | case 16: | |
426 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD); | |
427 | break; | |
428 | case 32: | |
429 | default: | |
430 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD); | |
431 | break; | |
432 | } | |
433 | ||
434 | /* If the device is marked as an in/out FIFO, ensure it is | |
435 | * set non-coherent. | |
436 | */ | |
437 | if (stp->dev_flags & DEV_FLAGS_IN) | |
438 | cmd0 |= DSCR_CMD0_SN; /* Source in fifo */ | |
439 | if (dtp->dev_flags & DEV_FLAGS_OUT) | |
440 | cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */ | |
441 | ||
442 | /* Set up source1. For now, assume no stride and increment. | |
443 | * A channel attribute update can change this later. | |
444 | */ | |
445 | switch (stp->dev_tsize) { | |
446 | case 1: | |
447 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1); | |
448 | break; | |
449 | case 2: | |
450 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2); | |
451 | break; | |
452 | case 4: | |
453 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4); | |
454 | break; | |
455 | case 8: | |
456 | default: | |
457 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8); | |
458 | break; | |
459 | } | |
460 | ||
461 | /* If source input is fifo, set static address. | |
462 | */ | |
463 | if (stp->dev_flags & DEV_FLAGS_IN) { | |
464 | src0 = stp->dev_physaddr; | |
465 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); | |
466 | } | |
467 | ||
468 | /* Set up dest1. For now, assume no stride and increment. | |
469 | * A channel attribute update can change this later. | |
470 | */ | |
471 | switch (dtp->dev_tsize) { | |
472 | case 1: | |
473 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1); | |
474 | break; | |
475 | case 2: | |
476 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2); | |
477 | break; | |
478 | case 4: | |
479 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4); | |
480 | break; | |
481 | case 8: | |
482 | default: | |
483 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8); | |
484 | break; | |
485 | } | |
486 | ||
487 | /* If destination output is fifo, set static address. | |
488 | */ | |
489 | if (dtp->dev_flags & DEV_FLAGS_OUT) { | |
490 | dest0 = dtp->dev_physaddr; | |
491 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); | |
492 | } | |
493 | ||
494 | for (i=0; i<entries; i++) { | |
495 | dp->dscr_cmd0 = cmd0; | |
496 | dp->dscr_cmd1 = cmd1; | |
497 | dp->dscr_source0 = src0; | |
498 | dp->dscr_source1 = src1; | |
499 | dp->dscr_dest0 = dest0; | |
500 | dp->dscr_dest1 = dest1; | |
501 | dp->dscr_stat = 0; | |
502 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); | |
503 | dp++; | |
504 | } | |
505 | ||
506 | /* Make last descrptor point to the first. | |
507 | */ | |
508 | dp--; | |
509 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); | |
510 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
511 | ||
512 | return (u32)(ctp->chan_desc_base); | |
513 | } | |
514 | ||
515 | /* Put a source buffer into the DMA ring. | |
516 | * This updates the source pointer and byte count. Normally used | |
517 | * for memory to fifo transfers. | |
518 | */ | |
519 | u32 | |
520 | au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) | |
521 | { | |
522 | chan_tab_t *ctp; | |
523 | au1x_ddma_desc_t *dp; | |
524 | ||
525 | /* I guess we could check this to be within the | |
526 | * range of the table...... | |
527 | */ | |
528 | ctp = *((chan_tab_t **)chanid); | |
529 | ||
530 | /* We should have multiple callers for a particular channel, | |
531 | * an interrupt doesn't affect this pointer nor the descriptor, | |
532 | * so no locking should be needed. | |
533 | */ | |
534 | dp = ctp->put_ptr; | |
535 | ||
536 | /* If the descriptor is valid, we are way ahead of the DMA | |
537 | * engine, so just return an error condition. | |
538 | */ | |
539 | if (dp->dscr_cmd0 & DSCR_CMD0_V) { | |
540 | return 0; | |
541 | } | |
542 | ||
543 | /* Load up buffer address and byte count. | |
544 | */ | |
545 | dp->dscr_source0 = virt_to_phys(buf); | |
546 | dp->dscr_cmd1 = nbytes; | |
547 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ | |
548 | ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ | |
549 | ||
550 | /* Get next descriptor pointer. | |
551 | */ | |
552 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
553 | ||
554 | /* return something not zero. | |
555 | */ | |
556 | return nbytes; | |
557 | } | |
558 | ||
559 | /* Put a destination buffer into the DMA ring. | |
560 | * This updates the destination pointer and byte count. Normally used | |
561 | * to place an empty buffer into the ring for fifo to memory transfers. | |
562 | */ | |
563 | u32 | |
564 | au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) | |
565 | { | |
566 | chan_tab_t *ctp; | |
567 | au1x_ddma_desc_t *dp; | |
568 | ||
569 | /* I guess we could check this to be within the | |
570 | * range of the table...... | |
571 | */ | |
572 | ctp = *((chan_tab_t **)chanid); | |
573 | ||
574 | /* We should have multiple callers for a particular channel, | |
575 | * an interrupt doesn't affect this pointer nor the descriptor, | |
576 | * so no locking should be needed. | |
577 | */ | |
578 | dp = ctp->put_ptr; | |
579 | ||
580 | /* If the descriptor is valid, we are way ahead of the DMA | |
581 | * engine, so just return an error condition. | |
582 | */ | |
583 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
584 | return 0; | |
585 | ||
586 | /* Load up buffer address and byte count. | |
587 | */ | |
588 | dp->dscr_dest0 = virt_to_phys(buf); | |
589 | dp->dscr_cmd1 = nbytes; | |
590 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ | |
591 | ||
592 | /* Get next descriptor pointer. | |
593 | */ | |
594 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
595 | ||
596 | /* return something not zero. | |
597 | */ | |
598 | return nbytes; | |
599 | } | |
600 | ||
601 | /* Get a destination buffer into the DMA ring. | |
602 | * Normally used to get a full buffer from the ring during fifo | |
603 | * to memory transfers. This does not set the valid bit, you will | |
604 | * have to put another destination buffer to keep the DMA going. | |
605 | */ | |
606 | u32 | |
607 | au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) | |
608 | { | |
609 | chan_tab_t *ctp; | |
610 | au1x_ddma_desc_t *dp; | |
611 | u32 rv; | |
612 | ||
613 | /* I guess we could check this to be within the | |
614 | * range of the table...... | |
615 | */ | |
616 | ctp = *((chan_tab_t **)chanid); | |
617 | ||
618 | /* We should have multiple callers for a particular channel, | |
619 | * an interrupt doesn't affect this pointer nor the descriptor, | |
620 | * so no locking should be needed. | |
621 | */ | |
622 | dp = ctp->get_ptr; | |
623 | ||
624 | /* If the descriptor is valid, we are way ahead of the DMA | |
625 | * engine, so just return an error condition. | |
626 | */ | |
627 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
628 | return 0; | |
629 | ||
630 | /* Return buffer address and byte count. | |
631 | */ | |
632 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); | |
633 | *nbytes = dp->dscr_cmd1; | |
634 | rv = dp->dscr_stat; | |
635 | ||
636 | /* Get next descriptor pointer. | |
637 | */ | |
638 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
639 | ||
640 | /* return something not zero. | |
641 | */ | |
642 | return rv; | |
643 | } | |
644 | ||
645 | void | |
646 | au1xxx_dbdma_stop(u32 chanid) | |
647 | { | |
648 | chan_tab_t *ctp; | |
649 | volatile au1x_dma_chan_t *cp; | |
650 | int halt_timeout = 0; | |
651 | ||
652 | ctp = *((chan_tab_t **)chanid); | |
653 | ||
654 | cp = ctp->chan_ptr; | |
655 | cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ | |
656 | au_sync(); | |
657 | while (!(cp->ddma_stat & DDMA_STAT_H)) { | |
658 | udelay(1); | |
659 | halt_timeout++; | |
660 | if (halt_timeout > 100) { | |
661 | printk("warning: DMA channel won't halt\n"); | |
662 | break; | |
663 | } | |
664 | } | |
665 | /* clear current desc valid and doorbell */ | |
666 | cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); | |
667 | au_sync(); | |
668 | } | |
669 | ||
670 | /* Start using the current descriptor pointer. If the dbdma encounters | |
671 | * a not valid descriptor, it will stop. In this case, we can just | |
672 | * continue by adding a buffer to the list and starting again. | |
673 | */ | |
674 | void | |
675 | au1xxx_dbdma_start(u32 chanid) | |
676 | { | |
677 | chan_tab_t *ctp; | |
678 | volatile au1x_dma_chan_t *cp; | |
679 | ||
680 | ctp = *((chan_tab_t **)chanid); | |
681 | ||
682 | cp = ctp->chan_ptr; | |
683 | cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); | |
684 | cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ | |
685 | au_sync(); | |
686 | cp->ddma_dbell = 0xffffffff; /* Make it go */ | |
687 | au_sync(); | |
688 | } | |
689 | ||
690 | void | |
691 | au1xxx_dbdma_reset(u32 chanid) | |
692 | { | |
693 | chan_tab_t *ctp; | |
694 | au1x_ddma_desc_t *dp; | |
695 | ||
696 | au1xxx_dbdma_stop(chanid); | |
697 | ||
698 | ctp = *((chan_tab_t **)chanid); | |
699 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
700 | ||
701 | /* Run through the descriptors and reset the valid indicator. | |
702 | */ | |
703 | dp = ctp->chan_desc_base; | |
704 | ||
705 | do { | |
706 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; | |
707 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
708 | } while (dp != ctp->chan_desc_base); | |
709 | } | |
710 | ||
711 | u32 | |
712 | au1xxx_get_dma_residue(u32 chanid) | |
713 | { | |
714 | chan_tab_t *ctp; | |
715 | volatile au1x_dma_chan_t *cp; | |
716 | u32 rv; | |
717 | ||
718 | ctp = *((chan_tab_t **)chanid); | |
719 | cp = ctp->chan_ptr; | |
720 | ||
721 | /* This is only valid if the channel is stopped. | |
722 | */ | |
723 | rv = cp->ddma_bytecnt; | |
724 | au_sync(); | |
725 | ||
726 | return rv; | |
727 | } | |
728 | ||
729 | void | |
730 | au1xxx_dbdma_chan_free(u32 chanid) | |
731 | { | |
732 | chan_tab_t *ctp; | |
733 | dbdev_tab_t *stp, *dtp; | |
734 | ||
735 | ctp = *((chan_tab_t **)chanid); | |
736 | stp = ctp->chan_src; | |
737 | dtp = ctp->chan_dest; | |
738 | ||
739 | au1xxx_dbdma_stop(chanid); | |
740 | ||
741 | if (ctp->chan_desc_base != NULL) | |
742 | kfree(ctp->chan_desc_base); | |
743 | ||
744 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
745 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
746 | chan_tab_ptr[ctp->chan_index] = NULL; | |
747 | ||
748 | kfree(ctp); | |
749 | } | |
750 | ||
751 | static irqreturn_t | |
752 | dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
753 | { | |
754 | u32 intstat; | |
755 | u32 chan_index; | |
756 | chan_tab_t *ctp; | |
757 | au1x_ddma_desc_t *dp; | |
758 | volatile au1x_dma_chan_t *cp; | |
759 | ||
760 | intstat = dbdma_gptr->ddma_intstat; | |
761 | au_sync(); | |
762 | chan_index = au_ffs(intstat) - 1; | |
763 | ||
764 | ctp = chan_tab_ptr[chan_index]; | |
765 | cp = ctp->chan_ptr; | |
766 | dp = ctp->cur_ptr; | |
767 | ||
768 | /* Reset interrupt. | |
769 | */ | |
770 | cp->ddma_irq = 0; | |
771 | au_sync(); | |
772 | ||
773 | if (ctp->chan_callback) | |
774 | (ctp->chan_callback)(irq, ctp->chan_callparam, regs); | |
775 | ||
776 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
777 | ||
778 | return IRQ_HANDLED; | |
779 | } | |
780 | ||
781 | static void | |
782 | au1xxx_dbdma_init(void) | |
783 | { | |
784 | dbdma_gptr->ddma_config = 0; | |
785 | dbdma_gptr->ddma_throttle = 0; | |
786 | dbdma_gptr->ddma_inten = 0xffff; | |
787 | au_sync(); | |
788 | ||
789 | if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, | |
790 | "Au1xxx dbdma", (void *)dbdma_gptr)) | |
791 | printk("Can't get 1550 dbdma irq"); | |
792 | } | |
793 | ||
794 | void | |
795 | au1xxx_dbdma_dump(u32 chanid) | |
796 | { | |
797 | chan_tab_t *ctp; | |
798 | au1x_ddma_desc_t *dp; | |
799 | dbdev_tab_t *stp, *dtp; | |
800 | volatile au1x_dma_chan_t *cp; | |
801 | ||
802 | ctp = *((chan_tab_t **)chanid); | |
803 | stp = ctp->chan_src; | |
804 | dtp = ctp->chan_dest; | |
805 | cp = ctp->chan_ptr; | |
806 | ||
807 | printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", | |
808 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab); | |
809 | printk("desc base %x, get %x, put %x, cur %x\n", | |
810 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), | |
811 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | |
812 | ||
813 | printk("dbdma chan %x\n", (u32)cp); | |
814 | printk("cfg %08x, desptr %08x, statptr %08x\n", | |
815 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); | |
816 | printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", | |
817 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt); | |
818 | ||
819 | ||
820 | /* Run through the descriptors | |
821 | */ | |
822 | dp = ctp->chan_desc_base; | |
823 | ||
824 | do { | |
825 | printk("dp %08x, cmd0 %08x, cmd1 %08x\n", | |
826 | (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); | |
827 | printk("src0 %08x, src1 %08x, dest0 %08x\n", | |
828 | dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); | |
829 | printk("dest1 %08x, stat %08x, nxtptr %08x\n", | |
830 | dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); | |
831 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
832 | } while (dp != ctp->chan_desc_base); | |
833 | } | |
834 | ||
835 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ | |
836 |