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e7300d04 MB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
7 | * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/cpu.h> | |
602977b0 | 13 | #include <asm/cpu.h> |
2b5b9b78 | 14 | #include <asm/cpu-info.h> |
602977b0 | 15 | #include <asm/mipsregs.h> |
e7300d04 MB |
16 | #include <bcm63xx_cpu.h> |
17 | #include <bcm63xx_regs.h> | |
18 | #include <bcm63xx_io.h> | |
19 | #include <bcm63xx_irq.h> | |
20 | ||
21 | const unsigned long *bcm63xx_regs_base; | |
22 | EXPORT_SYMBOL(bcm63xx_regs_base); | |
23 | ||
24 | const int *bcm63xx_irqs; | |
25 | EXPORT_SYMBOL(bcm63xx_irqs); | |
26 | ||
27 | static u16 bcm63xx_cpu_id; | |
28 | static u16 bcm63xx_cpu_rev; | |
29 | static unsigned int bcm63xx_cpu_freq; | |
30 | static unsigned int bcm63xx_memory_size; | |
31 | ||
e5766aea JG |
32 | static const unsigned long bcm6328_regs_base[] = { |
33 | __GEN_CPU_REGS_TABLE(6328) | |
34 | }; | |
35 | ||
36 | static const int bcm6328_irqs[] = { | |
37 | __GEN_CPU_IRQ_TABLE(6328) | |
38 | }; | |
39 | ||
ec68c520 MB |
40 | static const unsigned long bcm6338_regs_base[] = { |
41 | __GEN_CPU_REGS_TABLE(6338) | |
e7300d04 MB |
42 | }; |
43 | ||
ec68c520 MB |
44 | static const int bcm6338_irqs[] = { |
45 | __GEN_CPU_IRQ_TABLE(6338) | |
e7300d04 MB |
46 | }; |
47 | ||
ec68c520 MB |
48 | static const unsigned long bcm6345_regs_base[] = { |
49 | __GEN_CPU_REGS_TABLE(6345) | |
e7300d04 MB |
50 | }; |
51 | ||
ec68c520 MB |
52 | static const int bcm6345_irqs[] = { |
53 | __GEN_CPU_IRQ_TABLE(6345) | |
e7300d04 MB |
54 | }; |
55 | ||
ec68c520 MB |
56 | static const unsigned long bcm6348_regs_base[] = { |
57 | __GEN_CPU_REGS_TABLE(6348) | |
e7300d04 MB |
58 | }; |
59 | ||
ec68c520 MB |
60 | static const int bcm6348_irqs[] = { |
61 | __GEN_CPU_IRQ_TABLE(6348) | |
62 | ||
e7300d04 MB |
63 | }; |
64 | ||
ec68c520 MB |
65 | static const unsigned long bcm6358_regs_base[] = { |
66 | __GEN_CPU_REGS_TABLE(6358) | |
e7300d04 MB |
67 | }; |
68 | ||
ec68c520 MB |
69 | static const int bcm6358_irqs[] = { |
70 | __GEN_CPU_IRQ_TABLE(6358) | |
71 | ||
e7300d04 MB |
72 | }; |
73 | ||
04712f3f MB |
74 | static const unsigned long bcm6368_regs_base[] = { |
75 | __GEN_CPU_REGS_TABLE(6368) | |
76 | }; | |
77 | ||
78 | static const int bcm6368_irqs[] = { | |
79 | __GEN_CPU_IRQ_TABLE(6368) | |
80 | ||
81 | }; | |
82 | ||
e7300d04 MB |
83 | u16 __bcm63xx_get_cpu_id(void) |
84 | { | |
85 | return bcm63xx_cpu_id; | |
86 | } | |
87 | ||
88 | EXPORT_SYMBOL(__bcm63xx_get_cpu_id); | |
89 | ||
90 | u16 bcm63xx_get_cpu_rev(void) | |
91 | { | |
92 | return bcm63xx_cpu_rev; | |
93 | } | |
94 | ||
95 | EXPORT_SYMBOL(bcm63xx_get_cpu_rev); | |
96 | ||
97 | unsigned int bcm63xx_get_cpu_freq(void) | |
98 | { | |
99 | return bcm63xx_cpu_freq; | |
100 | } | |
101 | ||
102 | unsigned int bcm63xx_get_memory_size(void) | |
103 | { | |
104 | return bcm63xx_memory_size; | |
105 | } | |
106 | ||
107 | static unsigned int detect_cpu_clock(void) | |
108 | { | |
04712f3f | 109 | switch (bcm63xx_get_cpu_id()) { |
e5766aea JG |
110 | case BCM6328_CPU_ID: |
111 | { | |
112 | unsigned int tmp, mips_pll_fcvo; | |
113 | ||
114 | tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); | |
115 | mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) | |
116 | >> STRAPBUS_6328_FCVO_SHIFT; | |
117 | ||
118 | switch (mips_pll_fcvo) { | |
119 | case 0x12: | |
120 | case 0x14: | |
121 | case 0x19: | |
122 | return 160000000; | |
123 | case 0x1c: | |
124 | return 192000000; | |
125 | case 0x13: | |
126 | case 0x15: | |
127 | return 200000000; | |
128 | case 0x1a: | |
129 | return 384000000; | |
130 | case 0x16: | |
131 | return 400000000; | |
132 | default: | |
133 | return 320000000; | |
134 | } | |
135 | ||
136 | } | |
04712f3f MB |
137 | case BCM6338_CPU_ID: |
138 | /* BCM6338 has a fixed 240 Mhz frequency */ | |
e7300d04 MB |
139 | return 240000000; |
140 | ||
04712f3f MB |
141 | case BCM6345_CPU_ID: |
142 | /* BCM6345 has a fixed 140Mhz frequency */ | |
e7300d04 MB |
143 | return 140000000; |
144 | ||
04712f3f MB |
145 | case BCM6348_CPU_ID: |
146 | { | |
147 | unsigned int tmp, n1, n2, m1; | |
148 | ||
e7300d04 MB |
149 | /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ |
150 | tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); | |
151 | n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; | |
152 | n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; | |
153 | m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; | |
154 | n1 += 1; | |
155 | n2 += 2; | |
156 | m1 += 1; | |
04712f3f | 157 | return (16 * 1000000 * n1 * n2) / m1; |
e7300d04 MB |
158 | } |
159 | ||
04712f3f MB |
160 | case BCM6358_CPU_ID: |
161 | { | |
162 | unsigned int tmp, n1, n2, m1; | |
163 | ||
e7300d04 MB |
164 | /* 16MHz * N1 * N2 / M1_CPU */ |
165 | tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); | |
166 | n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; | |
167 | n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; | |
168 | m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; | |
04712f3f | 169 | return (16 * 1000000 * n1 * n2) / m1; |
e7300d04 MB |
170 | } |
171 | ||
04712f3f MB |
172 | case BCM6368_CPU_ID: |
173 | { | |
174 | unsigned int tmp, p1, p2, ndiv, m1; | |
175 | ||
176 | /* (64MHz / P1) * P2 * NDIV / M1_CPU */ | |
177 | tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG); | |
178 | ||
179 | p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> | |
180 | DMIPSPLLCFG_6368_P1_SHIFT; | |
181 | ||
182 | p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> | |
183 | DMIPSPLLCFG_6368_P2_SHIFT; | |
184 | ||
185 | ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> | |
186 | DMIPSPLLCFG_6368_NDIV_SHIFT; | |
187 | ||
188 | tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG); | |
189 | m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> | |
190 | DMIPSPLLDIV_6368_MDIV_SHIFT; | |
191 | ||
192 | return (((64 * 1000000) / p1) * p2 * ndiv) / m1; | |
193 | } | |
194 | ||
195 | default: | |
196 | BUG(); | |
197 | } | |
e7300d04 MB |
198 | } |
199 | ||
200 | /* | |
201 | * attempt to detect the amount of memory installed | |
202 | */ | |
203 | static unsigned int detect_memory_size(void) | |
204 | { | |
205 | unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; | |
206 | u32 val; | |
207 | ||
e5766aea JG |
208 | if (BCMCPU_IS_6328()) |
209 | return bcm_ddr_readl(DDR_CSEND_REG) << 24; | |
210 | ||
d61fcfe2 FF |
211 | if (BCMCPU_IS_6345()) { |
212 | val = bcm_sdram_readl(SDRAM_MBASE_REG); | |
213 | return (val * 8 * 1024 * 1024); | |
214 | } | |
e7300d04 MB |
215 | |
216 | if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { | |
217 | val = bcm_sdram_readl(SDRAM_CFG_REG); | |
218 | rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; | |
219 | cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; | |
220 | is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; | |
221 | banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; | |
222 | } | |
223 | ||
04712f3f | 224 | if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { |
e7300d04 MB |
225 | val = bcm_memc_readl(MEMC_CFG_REG); |
226 | rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; | |
227 | cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; | |
228 | is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; | |
229 | banks = 2; | |
230 | } | |
231 | ||
232 | /* 0 => 11 address bits ... 2 => 13 address bits */ | |
233 | rows += 11; | |
234 | ||
235 | /* 0 => 8 address bits ... 2 => 10 address bits */ | |
236 | cols += 8; | |
237 | ||
238 | return 1 << (cols + rows + (is_32bits + 1) + banks); | |
239 | } | |
240 | ||
241 | void __init bcm63xx_cpu_init(void) | |
242 | { | |
243 | unsigned int tmp, expected_cpu_id; | |
244 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
2b5b9b78 | 245 | unsigned int cpu = smp_processor_id(); |
e7300d04 MB |
246 | |
247 | /* soc registers location depends on cpu type */ | |
248 | expected_cpu_id = 0; | |
249 | ||
250 | switch (c->cputype) { | |
602977b0 KC |
251 | case CPU_BMIPS3300: |
252 | if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { | |
253 | expected_cpu_id = BCM6348_CPU_ID; | |
ec68c520 MB |
254 | bcm63xx_regs_base = bcm6348_regs_base; |
255 | bcm63xx_irqs = bcm6348_irqs; | |
602977b0 KC |
256 | } else { |
257 | __cpu_name[cpu] = "Broadcom BCM6338"; | |
258 | expected_cpu_id = BCM6338_CPU_ID; | |
ec68c520 MB |
259 | bcm63xx_regs_base = bcm6338_regs_base; |
260 | bcm63xx_irqs = bcm6338_irqs; | |
602977b0 | 261 | } |
e7300d04 | 262 | break; |
602977b0 | 263 | case CPU_BMIPS32: |
e7300d04 | 264 | expected_cpu_id = BCM6345_CPU_ID; |
ec68c520 MB |
265 | bcm63xx_regs_base = bcm6345_regs_base; |
266 | bcm63xx_irqs = bcm6345_irqs; | |
e7300d04 | 267 | break; |
602977b0 | 268 | case CPU_BMIPS4350: |
288752a8 | 269 | if ((read_c0_prid() & 0xf0) == 0x10) { |
04712f3f MB |
270 | expected_cpu_id = BCM6358_CPU_ID; |
271 | bcm63xx_regs_base = bcm6358_regs_base; | |
272 | bcm63xx_irqs = bcm6358_irqs; | |
288752a8 JG |
273 | } else { |
274 | /* all newer chips have the same chip id location */ | |
275 | u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); | |
276 | ||
277 | switch (chip_id) { | |
e5766aea JG |
278 | case BCM6328_CPU_ID: |
279 | expected_cpu_id = BCM6328_CPU_ID; | |
280 | bcm63xx_regs_base = bcm6328_regs_base; | |
281 | bcm63xx_irqs = bcm6328_irqs; | |
282 | break; | |
288752a8 JG |
283 | case BCM6368_CPU_ID: |
284 | expected_cpu_id = BCM6368_CPU_ID; | |
285 | bcm63xx_regs_base = bcm6368_regs_base; | |
286 | bcm63xx_irqs = bcm6368_irqs; | |
287 | break; | |
288 | } | |
04712f3f | 289 | } |
e7300d04 MB |
290 | break; |
291 | } | |
292 | ||
293 | /* | |
294 | * really early to panic, but delaying panic would not help since we | |
295 | * will never get any working console | |
296 | */ | |
297 | if (!expected_cpu_id) | |
298 | panic("unsupported Broadcom CPU"); | |
299 | ||
300 | /* | |
301 | * bcm63xx_regs_base is set, we can access soc registers | |
302 | */ | |
303 | ||
304 | /* double check CPU type */ | |
305 | tmp = bcm_perf_readl(PERF_REV_REG); | |
306 | bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; | |
307 | bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; | |
308 | ||
309 | if (bcm63xx_cpu_id != expected_cpu_id) | |
310 | panic("bcm63xx CPU id mismatch"); | |
311 | ||
312 | bcm63xx_cpu_freq = detect_cpu_clock(); | |
313 | bcm63xx_memory_size = detect_memory_size(); | |
314 | ||
315 | printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", | |
316 | bcm63xx_cpu_id, bcm63xx_cpu_rev); | |
317 | printk(KERN_INFO "CPU frequency is %u MHz\n", | |
318 | bcm63xx_cpu_freq / 1000000); | |
319 | printk(KERN_INFO "%uMB of RAM installed\n", | |
320 | bcm63xx_memory_size >> 20); | |
321 | } |