Commit | Line | Data |
---|---|---|
8945e37e KC |
1 | / { |
2 | #address-cells = <1>; | |
3 | #size-cells = <1>; | |
4 | compatible = "brcm,bcm7362"; | |
5 | ||
6 | cpus { | |
7 | #address-cells = <1>; | |
8 | #size-cells = <0>; | |
9 | ||
10 | mips-hpt-frequency = <375000000>; | |
11 | ||
12 | cpu@0 { | |
13 | compatible = "brcm,bmips4380"; | |
14 | device_type = "cpu"; | |
15 | reg = <0>; | |
16 | }; | |
17 | ||
18 | cpu@1 { | |
19 | compatible = "brcm,bmips4380"; | |
20 | device_type = "cpu"; | |
21 | reg = <1>; | |
22 | }; | |
23 | }; | |
24 | ||
25 | aliases { | |
26 | uart0 = &uart0; | |
27 | }; | |
28 | ||
29 | cpu_intc: cpu_intc { | |
30 | #address-cells = <0>; | |
31 | compatible = "mti,cpu-interrupt-controller"; | |
32 | ||
33 | interrupt-controller; | |
34 | #interrupt-cells = <1>; | |
35 | }; | |
36 | ||
37 | clocks { | |
38 | uart_clk: uart_clk { | |
39 | compatible = "fixed-clock"; | |
40 | #clock-cells = <0>; | |
41 | clock-frequency = <81000000>; | |
42 | }; | |
43 | }; | |
44 | ||
45 | rdb { | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | ||
49 | compatible = "simple-bus"; | |
50 | ranges = <0 0x10000000 0x01000000>; | |
51 | ||
52 | periph_intc: periph_intc@411400 { | |
53 | compatible = "brcm,bcm7038-l1-intc"; | |
54 | reg = <0x411400 0x30>, <0x411600 0x30>; | |
55 | ||
56 | interrupt-controller; | |
57 | #interrupt-cells = <1>; | |
58 | ||
59 | interrupt-parent = <&cpu_intc>; | |
60 | interrupts = <2>, <3>; | |
61 | }; | |
62 | ||
63 | sun_l2_intc: sun_l2_intc@403000 { | |
64 | compatible = "brcm,l2-intc"; | |
65 | reg = <0x403000 0x30>; | |
66 | interrupt-controller; | |
67 | #interrupt-cells = <1>; | |
68 | interrupt-parent = <&periph_intc>; | |
69 | interrupts = <48>; | |
70 | }; | |
71 | ||
72 | gisb-arb@400000 { | |
73 | compatible = "brcm,bcm7400-gisb-arb"; | |
74 | reg = <0x400000 0xdc>; | |
75 | native-endian; | |
76 | interrupt-parent = <&sun_l2_intc>; | |
77 | interrupts = <0>, <2>; | |
78 | brcm,gisb-arb-master-mask = <0x2f3>; | |
79 | brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", | |
80 | "rdc_0", "raaga_0", | |
81 | "avd_0", "jtag_0"; | |
82 | }; | |
83 | ||
84 | upg_irq0_intc: upg_irq0_intc@406600 { | |
85 | compatible = "brcm,bcm7120-l2-intc"; | |
86 | reg = <0x406600 0x8>; | |
87 | ||
f50cbf53 | 88 | brcm,int-map-mask = <0x44>, <0x7000000>; |
8945e37e KC |
89 | brcm,int-fwd-mask = <0x70000>; |
90 | ||
91 | interrupt-controller; | |
92 | #interrupt-cells = <1>; | |
93 | ||
94 | interrupt-parent = <&periph_intc>; | |
f50cbf53 JS |
95 | interrupts = <56>, <54>; |
96 | interrupt-names = "upg_main", "upg_bsc"; | |
97 | }; | |
98 | ||
99 | upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { | |
100 | compatible = "brcm,bcm7120-l2-intc"; | |
101 | reg = <0x408b80 0x8>; | |
102 | ||
103 | brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; | |
104 | brcm,int-fwd-mask = <0>; | |
105 | brcm,irq-can-wake; | |
106 | ||
107 | interrupt-controller; | |
108 | #interrupt-cells = <1>; | |
109 | ||
110 | interrupt-parent = <&periph_intc>; | |
111 | interrupts = <57>, <55>, <59>; | |
112 | interrupt-names = "upg_main_aon", "upg_bsc_aon", | |
113 | "upg_spi"; | |
8945e37e KC |
114 | }; |
115 | ||
116 | sun_top_ctrl: syscon@404000 { | |
117 | compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; | |
118 | reg = <0x404000 0x51c>; | |
25d6463e | 119 | native-endian; |
8945e37e KC |
120 | }; |
121 | ||
122 | reboot { | |
123 | compatible = "brcm,brcmstb-reboot"; | |
124 | syscon = <&sun_top_ctrl 0x304 0x308>; | |
125 | }; | |
126 | ||
127 | uart0: serial@406800 { | |
128 | compatible = "ns16550a"; | |
129 | reg = <0x406800 0x20>; | |
130 | reg-io-width = <0x4>; | |
131 | reg-shift = <0x2>; | |
132 | native-endian; | |
133 | interrupt-parent = <&periph_intc>; | |
134 | interrupts = <61>; | |
135 | clocks = <&uart_clk>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | ||
8bac078c JS |
139 | uart1: serial@406840 { |
140 | compatible = "ns16550a"; | |
141 | reg = <0x406840 0x20>; | |
142 | reg-io-width = <0x4>; | |
143 | reg-shift = <0x2>; | |
144 | native-endian; | |
145 | interrupt-parent = <&periph_intc>; | |
146 | interrupts = <62>; | |
147 | clocks = <&uart_clk>; | |
148 | status = "disabled"; | |
149 | }; | |
150 | ||
151 | uart2: serial@406880 { | |
152 | compatible = "ns16550a"; | |
153 | reg = <0x406880 0x20>; | |
154 | reg-io-width = <0x4>; | |
155 | reg-shift = <0x2>; | |
156 | native-endian; | |
157 | interrupt-parent = <&periph_intc>; | |
158 | interrupts = <63>; | |
159 | clocks = <&uart_clk>; | |
160 | status = "disabled"; | |
161 | }; | |
162 | ||
f50cbf53 JS |
163 | bsca: i2c@406200 { |
164 | clock-frequency = <390000>; | |
165 | compatible = "brcm,brcmstb-i2c"; | |
166 | interrupt-parent = <&upg_irq0_intc>; | |
167 | reg = <0x406200 0x58>; | |
168 | interrupts = <24>; | |
169 | interrupt-names = "upg_bsca"; | |
170 | status = "disabled"; | |
171 | }; | |
172 | ||
173 | bscb: i2c@406280 { | |
174 | clock-frequency = <390000>; | |
175 | compatible = "brcm,brcmstb-i2c"; | |
176 | interrupt-parent = <&upg_irq0_intc>; | |
177 | reg = <0x406280 0x58>; | |
178 | interrupts = <25>; | |
179 | interrupt-names = "upg_bscb"; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
183 | bscd: i2c@408980 { | |
184 | clock-frequency = <390000>; | |
185 | compatible = "brcm,brcmstb-i2c"; | |
186 | interrupt-parent = <&upg_aon_irq0_intc>; | |
187 | reg = <0x408980 0x58>; | |
188 | interrupts = <27>; | |
189 | interrupt-names = "upg_bscd"; | |
190 | status = "disabled"; | |
191 | }; | |
192 | ||
8945e37e KC |
193 | enet0: ethernet@430000 { |
194 | phy-mode = "internal"; | |
195 | phy-handle = <&phy1>; | |
196 | mac-address = [ 00 10 18 36 23 1a ]; | |
197 | compatible = "brcm,genet-v2"; | |
198 | #address-cells = <0x1>; | |
199 | #size-cells = <0x1>; | |
200 | reg = <0x430000 0x4c8c>; | |
201 | interrupts = <24>, <25>; | |
202 | interrupt-parent = <&periph_intc>; | |
203 | status = "disabled"; | |
204 | ||
205 | mdio@e14 { | |
206 | compatible = "brcm,genet-mdio-v2"; | |
207 | #address-cells = <0x1>; | |
208 | #size-cells = <0x0>; | |
209 | reg = <0xe14 0x8>; | |
210 | ||
211 | phy1: ethernet-phy@1 { | |
212 | max-speed = <100>; | |
213 | reg = <0x1>; | |
214 | compatible = "brcm,40nm-ephy", | |
215 | "ethernet-phy-ieee802.3-c22"; | |
216 | }; | |
217 | }; | |
218 | }; | |
219 | ||
220 | ehci0: usb@480300 { | |
221 | compatible = "brcm,bcm7362-ehci", "generic-ehci"; | |
222 | reg = <0x480300 0x100>; | |
223 | native-endian; | |
224 | interrupt-parent = <&periph_intc>; | |
225 | interrupts = <65>; | |
226 | status = "disabled"; | |
227 | }; | |
228 | ||
229 | ohci0: usb@480400 { | |
230 | compatible = "brcm,bcm7362-ohci", "generic-ohci"; | |
231 | reg = <0x480400 0x100>; | |
232 | native-endian; | |
233 | no-big-frame-no; | |
234 | interrupt-parent = <&periph_intc>; | |
235 | interrupts = <66>; | |
236 | status = "disabled"; | |
237 | }; | |
1b04be20 JS |
238 | |
239 | sata: sata@181000 { | |
240 | compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; | |
241 | reg-names = "ahci", "top-ctrl"; | |
242 | reg = <0x181000 0xa9c>, <0x180020 0x1c>; | |
243 | interrupt-parent = <&periph_intc>; | |
244 | interrupts = <86>; | |
245 | #address-cells = <1>; | |
246 | #size-cells = <0>; | |
1b04be20 JS |
247 | status = "disabled"; |
248 | ||
249 | sata0: sata-port@0 { | |
250 | reg = <0>; | |
251 | phys = <&sata_phy0>; | |
252 | }; | |
253 | ||
254 | sata1: sata-port@1 { | |
255 | reg = <1>; | |
256 | phys = <&sata_phy1>; | |
257 | }; | |
258 | }; | |
259 | ||
69ca2b81 | 260 | sata_phy: sata-phy@180100 { |
1b04be20 JS |
261 | compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; |
262 | reg = <0x180100 0x0eff>; | |
263 | reg-names = "phy"; | |
264 | #address-cells = <1>; | |
265 | #size-cells = <0>; | |
266 | status = "disabled"; | |
267 | ||
268 | sata_phy0: sata-phy@0 { | |
269 | reg = <0>; | |
270 | #phy-cells = <0>; | |
271 | }; | |
272 | ||
273 | sata_phy1: sata-phy@1 { | |
274 | reg = <1>; | |
275 | #phy-cells = <0>; | |
276 | }; | |
277 | }; | |
8945e37e KC |
278 | }; |
279 | }; |