[deliverable/linux.git] / arch / mips / cavium-octeon / smp.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
 */
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/module.h>

#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>

#include <asm/octeon/octeon.h>

#include "octeon_boot.h"

volatile unsigned long octeon_processor_boot = 0xff;
volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;

#ifdef CONFIG_HOTPLUG_CPU
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif

static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
{
	const int coreid = cvmx_get_core_num();
	uint64_t action;

	/* Load the mailbox register to figure out what we're supposed to do */
	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;

	/* Clear the mailbox to clear the interrupt */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);

	if (action & SMP_CALL_FUNCTION)
		smp_call_function_interrupt();
	if (action & SMP_RESCHEDULE_YOURSELF)
		scheduler_ipi();

	/* Check if we've been told to flush the icache */
	if (action & SMP_ICACHE_FLUSH)
		asm volatile ("synci 0($0)\n");
	return IRQ_HANDLED;
}

/**
 * Cause the function described by call_data to be executed on the passed
 * cpu.	 When the function has finished, increment the finished field of
 * call_data.
 */
void octeon_send_ipi_single(int cpu, unsigned int action)
{
	int coreid = cpu_logical_map(cpu);
	/*
	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	       coreid, action);
	*/
	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}

static inline void octeon_send_ipi_mask(const struct cpumask *mask,
					unsigned int action)
{
	unsigned int i;

	for_each_cpu_mask(i, *mask)
		octeon_send_ipi_single(i, action);
}

/**
 * Detect available CPUs, populate cpu_possible_mask
 */
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
	struct linux_app_boot_info *labi;

	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	if (labi->labi_signature != LABI_SIGNATURE)
		panic("The bootloader version on this board is incorrect.");

	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}

static void octeon_smp_setup(void)
{
	const int coreid = cvmx_get_core_num();
	int cpus;
	int id;
	int core_mask = octeon_get_boot_coremask();
#ifdef CONFIG_HOTPLUG_CPU
	unsigned int num_cores = cvmx_octeon_num_cores();
#endif

	/* The present CPUs are initially just the boot cpu (CPU 0). */
	for (id = 0; id < NR_CPUS; id++) {
		set_cpu_possible(id, id == 0);
		set_cpu_present(id, id == 0);
	}

	__cpu_number_map[coreid] = 0;
	__cpu_logical_map[0] = coreid;

	/* The present CPUs get the lowest CPU numbers. */
	cpus = 1;
	for (id = 0; id < NR_CPUS; id++) {
		if ((id != coreid) && (core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			set_cpu_present(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}

#ifdef CONFIG_HOTPLUG_CPU
	/*
	 * The possible CPUs are all those present on the chip.	 We
	 * will assign CPU numbers for possible cores as well.	Cores
	 * are always consecutively numberd from 0.
	 */
	for (id = 0; id < num_cores && id < NR_CPUS; id++) {
		if (!(core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}
#endif

	octeon_smp_hotplug_setup();
}

/**
 * Firmware CPU startup hook
 *
 */
static void octeon_boot_secondary(int cpu, struct task_struct *idle)
{
	int count;

	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
		cpu_logical_map(cpu));

	octeon_processor_sp = __KSTK_TOS(idle);
	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	octeon_processor_boot = cpu_logical_map(cpu);
	mb();

	count = 10000;
	while (octeon_processor_sp && count) {
		/* Waiting for processor to get the SP and GP */
		udelay(1);
		count--;
	}
	if (count == 0)
		pr_err("Secondary boot timeout\n");
}

/**
 * After we've done initial boot, this function is called to allow the
 * board code to clean up state, if needed
 */
static void octeon_init_secondary(void)
{
	unsigned int sr;

	sr = set_c0_status(ST0_BEV);
	write_c0_ebase((u32)ebase);
	write_c0_status(sr);

	octeon_check_cpu_bist();
	octeon_init_cvmcount();

	octeon_irq_setup_secondary();
}

/**
 * Callout to firmware before smp_init
 *
 */
void octeon_prepare_cpus(unsigned int max_cpus)
{
	/*
	 * Only the low order mailbox bits are used for IPIs, leave
	 * the other bits alone.
	 */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
			mailbox_interrupt)) {
		panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
	}
}

/**
 * Last chance for the board code to finish SMP initialization before
 * the CPU is "online".
 */
static void octeon_smp_finish(void)
{
	octeon_user_io_init();

	/* to generate the first CPU timer interrupt */
	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
	local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU

/* State of each CPU. */
DEFINE_PER_CPU(int, cpu_state);

static int octeon_cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	set_cpu_online(cpu, false);
	cpu_clear(cpu, cpu_callin_map);
	local_irq_disable();
	octeon_fixup_irqs();
	local_irq_enable();

	flush_cache_all();
	local_flush_tlb_all();

	return 0;
}

static void octeon_cpu_die(unsigned int cpu)
{
	int coreid = cpu_logical_map(cpu);
	uint32_t mask, new_mask;
	const struct cvmx_bootmem_named_block_desc *block_desc;

	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
		cpu_relax();

	/*
	 * This is a bit complicated strategics of getting/settig available
	 * cores mask, copied from bootloader
	 */

	mask = 1 << coreid;
	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		labi->avail_coremask |= mask;
		new_mask = labi->avail_coremask;
	} else {		       /* alternative, already initialized */
		uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
							       AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
		*p |= mask;
		new_mask = *p;
	}

	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
	mb();
	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}

void play_dead(void)
{
	int cpu = cpu_number_map(cvmx_get_core_num());

	idle_task_exit();
	octeon_processor_boot = 0xff;
	per_cpu(cpu_state, cpu) = CPU_DEAD;

	mb();

	while (1)	/* core will be reset here */
		;
}

extern void kernel_entry(unsigned long arg1, ...);

static void start_after_reset(void)
{
	kernel_entry(0, 0, 0);	/* set a2 = 0 for secondary core */
}

static int octeon_update_boot_vector(unsigned int cpu)
{

	int coreid = cpu_logical_map(cpu);
	uint32_t avail_coremask;
	const struct cvmx_bootmem_named_block_desc *block_desc;
	struct boot_init_vector *boot_vect =
		(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);

	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		avail_coremask = labi->avail_coremask;
		labi->avail_coremask &= ~(1 << coreid);
	} else {		       /* alternative, already initialized */
		avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
			block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	}

	if (!(avail_coremask & (1 << coreid))) {
		/* core not available, assume, that catched by simple-executive */
		cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
		cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	}

	boot_vect[coreid].app_start_func_addr =
		(uint32_t) (unsigned long) start_after_reset;
	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;

	mb();

	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);

	return 0;
}

static int octeon_cpu_callback(struct notifier_block *nfb,
	unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned long)hcpu;

	switch (action) {
	case CPU_UP_PREPARE:
		octeon_update_boot_vector(cpu);
		break;
	case CPU_ONLINE:
		pr_info("Cpu %d online\n", cpu);
		break;
	case CPU_DEAD:
		break;
	}

	return NOTIFY_OK;
}

static int register_cavium_notifier(void)
{
	hotcpu_notifier(octeon_cpu_callback, 0);
	return 0;
}
late_initcall(register_cavium_notifier);

#endif	/* CONFIG_HOTPLUG_CPU */

struct plat_smp_ops octeon_smp_ops = {
	.send_ipi_single	= octeon_send_ipi_single,
	.send_ipi_mask		= octeon_send_ipi_mask,
	.init_secondary		= octeon_init_secondary,
	.smp_finish		= octeon_smp_finish,
	.boot_secondary		= octeon_boot_secondary,
	.smp_setup		= octeon_smp_setup,
	.prepare_cpus		= octeon_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= octeon_cpu_disable,
	.cpu_die		= octeon_cpu_die,
#endif
};
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
edfcbb8c	6	* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
5b3b1688	7	*/
773cb77d	8	#include <linux/cpu.h>
5b3b1688 DD	9	#include <linux/delay.h>
	10	#include <linux/smp.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/sched.h>
	14	#include <linux/module.h>
	15
	16	#include <asm/mmu_context.h>
5b3b1688	17	#include <asm/time.h>
b81947c6	18	#include <asm/setup.h>
5b3b1688 DD	19
	20	#include <asm/octeon/octeon.h>
	21
773cb77d RB	22	#include "octeon_boot.h"
773cb77d RB	23
5b3b1688 DD	24	volatile unsigned long octeon_processor_boot = 0xff;
	25	volatile unsigned long octeon_processor_sp;
	26	volatile unsigned long octeon_processor_gp;
	27
773cb77d	28	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	29	uint64_t octeon_bootloader_entry_addr;
babba4f1 DD	30	EXPORT_SYMBOL(octeon_bootloader_entry_addr);
773cb77d RB	31	#endif
773cb77d RB	32
5b3b1688 DD	33	static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
	34	{
	35	const int coreid = cvmx_get_core_num();
	36	uint64_t action;
	37
	38	/* Load the mailbox register to figure out what we're supposed to do */
e650ce0f	39	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
5b3b1688 DD	40
	41	/* Clear the mailbox to clear the interrupt */
	42	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
	43
	44	if (action & SMP_CALL_FUNCTION)
	45	smp_call_function_interrupt();
184748cc PZ	46	if (action & SMP_RESCHEDULE_YOURSELF)
184748cc PZ	47	scheduler_ipi();
5b3b1688 DD	48
	49	/* Check if we've been told to flush the icache */
	50	if (action & SMP_ICACHE_FLUSH)
	51	asm volatile ("synci 0($0)\n");
	52	return IRQ_HANDLED;
	53	}
	54
	55	/**
	56	* Cause the function described by call_data to be executed on the passed
70342287	57	* cpu. When the function has finished, increment the finished field of
5b3b1688 DD	58	* call_data.
	59	*/
	60	void octeon_send_ipi_single(int cpu, unsigned int action)
	61	{
	62	int coreid = cpu_logical_map(cpu);
	63	/*
	64	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	65	coreid, action);
	66	*/
	67	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
	68	}
	69
067f3290 DD	70	static inline void octeon_send_ipi_mask(const struct cpumask *mask,
067f3290 DD	71	unsigned int action)
5b3b1688 DD	72	{
	73	unsigned int i;
	74
067f3290	75	for_each_cpu_mask(i, *mask)
5b3b1688 DD	76	octeon_send_ipi_single(i, action);
	77	}
	78
	79	/**
5f054e31	80	* Detect available CPUs, populate cpu_possible_mask
5b3b1688	81	*/
773cb77d RB	82	static void octeon_smp_hotplug_setup(void)
	83	{
	84	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	85	struct linux_app_boot_info *labi;
	86
	87	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	88	if (labi->labi_signature != LABI_SIGNATURE)
	89	panic("The bootloader version on this board is incorrect.");
	90
	91	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
773cb77d RB	92	#endif
	93	}
	94
5b3b1688 DD	95	static void octeon_smp_setup(void)
	96	{
	97	const int coreid = cvmx_get_core_num();
	98	int cpus;
	99	int id;
5b3b1688	100	int core_mask = octeon_get_boot_coremask();
edfcbb8c DD	101	#ifdef CONFIG_HOTPLUG_CPU
	102	unsigned int num_cores = cvmx_octeon_num_cores();
	103	#endif
	104
	105	/* The present CPUs are initially just the boot cpu (CPU 0). */
	106	for (id = 0; id < NR_CPUS; id++) {
	107	set_cpu_possible(id, id == 0);
	108	set_cpu_present(id, id == 0);
	109	}
5b3b1688	110
5b3b1688 DD	111	__cpu_number_map[coreid] = 0;
5b3b1688 DD	112	__cpu_logical_map[0] = coreid;
5b3b1688	113
edfcbb8c	114	/* The present CPUs get the lowest CPU numbers. */
5b3b1688	115	cpus = 1;
edfcbb8c	116	for (id = 0; id < NR_CPUS; id++) {
5b3b1688	117	if ((id != coreid) && (core_mask & (1 << id))) {
edfcbb8c DD	118	set_cpu_possible(cpus, true);
	119	set_cpu_present(cpus, true);
	120	__cpu_number_map[id] = cpus;
	121	__cpu_logical_map[cpus] = id;
	122	cpus++;
	123	}
	124	}
	125
	126	#ifdef CONFIG_HOTPLUG_CPU
	127	/*
70342287 RB	128	* The possible CPUs are all those present on the chip. We
70342287 RB	129	* will assign CPU numbers for possible cores as well. Cores
edfcbb8c DD	130	* are always consecutively numberd from 0.
	131	*/
	132	for (id = 0; id < num_cores && id < NR_CPUS; id++) {
	133	if (!(core_mask & (1 << id))) {
	134	set_cpu_possible(cpus, true);
5b3b1688 DD	135	__cpu_number_map[id] = cpus;
	136	__cpu_logical_map[cpus] = id;
	137	cpus++;
	138	}
	139	}
edfcbb8c	140	#endif
773cb77d RB	141
773cb77d RB	142	octeon_smp_hotplug_setup();
5b3b1688 DD	143	}
	144
	145	/**
	146	* Firmware CPU startup hook
	147	*
	148	*/
	149	static void octeon_boot_secondary(int cpu, struct task_struct *idle)
	150	{
	151	int count;
	152
	153	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
	154	cpu_logical_map(cpu));
	155
	156	octeon_processor_sp = __KSTK_TOS(idle);
	157	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	158	octeon_processor_boot = cpu_logical_map(cpu);
	159	mb();
	160
	161	count = 10000;
	162	while (octeon_processor_sp && count) {
	163	/* Waiting for processor to get the SP and GP */
	164	udelay(1);
	165	count--;
	166	}
	167	if (count == 0)
	168	pr_err("Secondary boot timeout\n");
	169	}
	170
	171	/**
	172	* After we've done initial boot, this function is called to allow the
	173	* board code to clean up state, if needed
	174	*/
078a55fc	175	static void octeon_init_secondary(void)
5b3b1688	176	{
babba4f1	177	unsigned int sr;
5b3b1688	178
babba4f1 DD	179	sr = set_c0_status(ST0_BEV);
	180	write_c0_ebase((u32)ebase);
	181	write_c0_status(sr);
	182
5b3b1688 DD	183	octeon_check_cpu_bist();
5b3b1688 DD	184	octeon_init_cvmcount();
0c326387 DD	185
0c326387 DD	186	octeon_irq_setup_secondary();
5b3b1688 DD	187	}
	188
	189	/**
	190	* Callout to firmware before smp_init
	191	*
	192	*/
	193	void octeon_prepare_cpus(unsigned int max_cpus)
	194	{
e650ce0f DD	195	/*
	196	* Only the low order mailbox bits are used for IPIs, leave
	197	* the other bits alone.
	198	*/
	199	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
e63fb7a9 VS	200	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
	201	IRQF_PERCPU \| IRQF_NO_THREAD, "SMP-IPI",
	202	mailbox_interrupt)) {
ab75dc02	203	panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
5b3b1688	204	}
5b3b1688 DD	205	}
	206
	207	/**
	208	* Last chance for the board code to finish SMP initialization before
	209	* the CPU is "online".
	210	*/
	211	static void octeon_smp_finish(void)
	212	{
5b3b1688 DD	213	octeon_user_io_init();
	214
	215	/* to generate the first CPU timer interrupt */
	216	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
1bcfecc0	217	local_irq_enable();
5b3b1688 DD	218	}
5b3b1688 DD	219
773cb77d RB	220	#ifdef CONFIG_HOTPLUG_CPU
	221
	222	/* State of each CPU. */
	223	DEFINE_PER_CPU(int, cpu_state);
	224
773cb77d RB	225	static int octeon_cpu_disable(void)
	226	{
	227	unsigned int cpu = smp_processor_id();
	228
	229	if (cpu == 0)
	230	return -EBUSY;
	231
0b5f9c00	232	set_cpu_online(cpu, false);
773cb77d RB	233	cpu_clear(cpu, cpu_callin_map);
773cb77d RB	234	local_irq_disable();
17efb59a	235	octeon_fixup_irqs();
773cb77d RB	236	local_irq_enable();
	237
	238	flush_cache_all();
	239	local_flush_tlb_all();
	240
773cb77d RB	241	return 0;
	242	}
	243
	244	static void octeon_cpu_die(unsigned int cpu)
	245	{
	246	int coreid = cpu_logical_map(cpu);
babba4f1 DD	247	uint32_t mask, new_mask;
babba4f1 DD	248	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	249
773cb77d RB	250	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
	251	cpu_relax();
	252
	253	/*
	254	* This is a bit complicated strategics of getting/settig available
	255	* cores mask, copied from bootloader
	256	*/
babba4f1 DD	257
babba4f1 DD	258	mask = 1 << coreid;
773cb77d RB	259	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	260	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	261
	262	if (!block_desc) {
babba4f1	263	struct linux_app_boot_info *labi;
773cb77d	264
babba4f1	265	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
773cb77d	266
babba4f1 DD	267	labi->avail_coremask \|= mask;
	268	new_mask = labi->avail_coremask;
	269	} else { /* alternative, already initialized */
	270	uint32_t p = (uint32_t )PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
	271	AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	272	*p \|= mask;
	273	new_mask = *p;
773cb77d RB	274	}
773cb77d RB	275
babba4f1 DD	276	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
babba4f1 DD	277	mb();
773cb77d RB	278	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	279	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	280	}
	281
	282	void play_dead(void)
	283	{
babba4f1	284	int cpu = cpu_number_map(cvmx_get_core_num());
773cb77d RB	285
	286	idle_task_exit();
	287	octeon_processor_boot = 0xff;
babba4f1 DD	288	per_cpu(cpu_state, cpu) = CPU_DEAD;
	289
	290	mb();
773cb77d RB	291
	292	while (1) /* core will be reset here */
	293	;
	294	}
	295
	296	extern void kernel_entry(unsigned long arg1, ...);
	297
	298	static void start_after_reset(void)
	299	{
70342287	300	kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
773cb77d RB	301	}
773cb77d RB	302
babba4f1	303	static int octeon_update_boot_vector(unsigned int cpu)
773cb77d RB	304	{
	305
	306	int coreid = cpu_logical_map(cpu);
babba4f1 DD	307	uint32_t avail_coremask;
babba4f1 DD	308	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	309	struct boot_init_vector *boot_vect =
babba4f1	310	(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
773cb77d RB	311
	312	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	313
	314	if (!block_desc) {
babba4f1 DD	315	struct linux_app_boot_info *labi;
	316
	317	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	318
	319	avail_coremask = labi->avail_coremask;
	320	labi->avail_coremask &= ~(1 << coreid);
773cb77d	321	} else { /* alternative, already initialized */
babba4f1 DD	322	avail_coremask = (uint32_t )PHYS_TO_XKSEG_CACHED(
babba4f1 DD	323	block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
773cb77d RB	324	}
	325
	326	if (!(avail_coremask & (1 << coreid))) {
	327	/* core not available, assume, that catched by simple-executive */
	328	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	329	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	330	}
	331
	332	boot_vect[coreid].app_start_func_addr =
	333	(uint32_t) (unsigned long) start_after_reset;
babba4f1	334	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
773cb77d	335
babba4f1	336	mb();
773cb77d RB	337
	338	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
	339
	340	return 0;
	341	}
	342
078a55fc	343	static int octeon_cpu_callback(struct notifier_block *nfb,
773cb77d RB	344	unsigned long action, void *hcpu)
	345	{
	346	unsigned int cpu = (unsigned long)hcpu;
	347
	348	switch (action) {
	349	case CPU_UP_PREPARE:
	350	octeon_update_boot_vector(cpu);
	351	break;
	352	case CPU_ONLINE:
	353	pr_info("Cpu %d online\n", cpu);
	354	break;
	355	case CPU_DEAD:
	356	break;
	357	}
	358
	359	return NOTIFY_OK;
	360	}
	361
078a55fc	362	static int register_cavium_notifier(void)
773cb77d	363	{
442f2012	364	hotcpu_notifier(octeon_cpu_callback, 0);
773cb77d RB	365	return 0;
773cb77d RB	366	}
773cb77d RB	367	late_initcall(register_cavium_notifier);
773cb77d RB	368
70342287	369	#endif /* CONFIG_HOTPLUG_CPU */
773cb77d	370
5b3b1688 DD	371	struct plat_smp_ops octeon_smp_ops = {
	372	.send_ipi_single = octeon_send_ipi_single,
	373	.send_ipi_mask = octeon_send_ipi_mask,
	374	.init_secondary = octeon_init_secondary,
	375	.smp_finish = octeon_smp_finish,
5b3b1688 DD	376	.boot_secondary = octeon_boot_secondary,
	377	.smp_setup = octeon_smp_setup,
	378	.prepare_cpus = octeon_prepare_cpus,
773cb77d RB	379	#ifdef CONFIG_HOTPLUG_CPU
	380	.cpu_disable = octeon_cpu_disable,
	381	.cpu_die = octeon_cpu_die,
	382	#endif
5b3b1688	383	};