[deliverable/linux.git] / arch / mips / dec / ecc-berr.c

/*
 *	Bus error event handling code for systems equipped with ECC
 *	handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
 *	5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
 *	5900/260 (KN05) systems.
 *
 *	Copyright (c) 2003, 2005  Maciej W. Rozycki
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>

#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/traps.h>

#include <asm/dec/ecc.h>
#include <asm/dec/kn02.h>
#include <asm/dec/kn03.h>
#include <asm/dec/kn05.h>

static volatile u32 *kn0x_erraddr;
static volatile u32 *kn0x_chksyn;

static inline void dec_ecc_be_ack(void)
{
	*kn0x_erraddr = 0;			/* any write clears the IRQ */
	iob();
}

static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
{
	static const char excstr[] = "exception";
	static const char intstr[] = "interrupt";
	static const char cpustr[] = "CPU";
	static const char dmastr[] = "DMA";
	static const char readstr[] = "read";
	static const char mreadstr[] = "memory read";
	static const char writestr[] = "write";
	static const char mwritstr[] = "partial memory write";
	static const char timestr[] = "timeout";
	static const char overstr[] = "overrun";
	static const char eccstr[] = "ECC error";

	const char *kind, *agent, *cycle, *event;
	const char *status = "", *xbit = "", *fmt = "";
	unsigned long address;
	u16 syn = 0, sngl;

	int i = 0;

	u32 erraddr = *kn0x_erraddr;
	u32 chksyn = *kn0x_chksyn;
	int action = MIPS_BE_FATAL;

	/* For non-ECC ack ASAP, so that any subsequent errors get caught. */
	if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
		dec_ecc_be_ack();

	kind = invoker ? intstr : excstr;

	if (!(erraddr & KN0X_EAR_VALID)) {
		/* No idea what happened. */
		printk(KERN_ALERT "Unidentified bus error %s\n", kind);
		return action;
	}

	agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;

	if (erraddr & KN0X_EAR_ECCERR) {
		/* An ECC error on a CPU or DMA transaction. */
		cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
		event = eccstr;
	} else {
		/* A CPU timeout or a DMA overrun. */
		cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
		event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
	}

	address = erraddr & KN0X_EAR_ADDRESS;
	/* For ECC errors on reads adjust for MT pipelining. */
	if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
		address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL);
	address <<= 2;

	/* Only CPU errors are fixable. */
	if (erraddr & KN0X_EAR_CPU && is_fixup)
		action = MIPS_BE_FIXUP;

	if (erraddr & KN0X_EAR_ECCERR) {
		static const u8 data_sbit[32] = {
			0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
			0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
			0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
			0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
		};
		static const u8 data_mbit[25] = {
			0x07, 0x0d, 0x1f,
			0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
			0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
			0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
		};
		static const char sbestr[] = "corrected single";
		static const char dbestr[] = "uncorrectable double";
		static const char mbestr[] = "uncorrectable multiple";

		if (!(address & 0x4))
			syn = chksyn;			/* Low bank. */
		else
			syn = chksyn >> 16;		/* High bank. */

		if (!(syn & KN0X_ESR_VLDLO)) {
			/* Ack now, no rewrite will happen. */
			dec_ecc_be_ack();

			fmt = KERN_ALERT "%s" "invalid\n";
		} else {
			sngl = syn & KN0X_ESR_SNGLO;
			syn &= KN0X_ESR_SYNLO;

			/*
			 * Multibit errors may be tagged incorrectly;
			 * check the syndrome explicitly.
			 */
			for (i = 0; i < 25; i++)
				if (syn == data_mbit[i])
					break;

			if (i < 25) {
				status = mbestr;
			} else if (!sngl) {
				status = dbestr;
			} else {
				volatile u32 *ptr =
					(void *)CKSEG1ADDR(address);

				*ptr = *ptr;		/* Rewrite. */
				iob();

				status = sbestr;
				action = MIPS_BE_DISCARD;
			}

			/* Ack now, now we've rewritten (or not). */
			dec_ecc_be_ack();

			if (syn && syn == (syn & -syn)) {
				if (syn == 0x01) {
					fmt = KERN_ALERT "%s"
					      "%#04x -- %s bit error "
					      "at check bit C%s\n";
					xbit = "X";
				} else {
					fmt = KERN_ALERT "%s"
					      "%#04x -- %s bit error "
					      "at check bit C%s%u\n";
				}
				i = syn >> 2;
			} else {
				for (i = 0; i < 32; i++)
					if (syn == data_sbit[i])
						break;
				if (i < 32)
					fmt = KERN_ALERT "%s"
					      "%#04x -- %s bit error "
					      "at data bit D%s%u\n";
				else
					fmt = KERN_ALERT "%s"
					      "%#04x -- %s bit error\n";
			}
		}
	}

	if (action != MIPS_BE_FIXUP)
		printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
			kind, agent, cycle, event, address);

	if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
		printk(fmt, "  ECC syndrome ", syn, status, xbit, i);

	return action;
}

int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
{
	return dec_ecc_be_backend(regs, is_fixup, 0);
}

irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
{
	struct pt_regs *regs = get_irq_regs();

	int action = dec_ecc_be_backend(regs, 0, 1);

	if (action == MIPS_BE_DISCARD)
		return IRQ_HANDLED;

	/*
	 * FIXME: Find the affected processes and kill them, otherwise
	 * we must die.
	 *
	 * The interrupt is asynchronously delivered thus EPC and RA
	 * may be irrelevant, but are printed for a reference.
	 */
	printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
	       regs->cp0_epc, regs->regs[31]);
	die("Unrecoverable bus error", regs);
}


/*
 * Initialization differs a bit between KN02 and KN03/KN05, so we
 * need two variants.  Once set up, all systems can be handled the
 * same way.
 */
static inline void dec_kn02_be_init(void)
{
	volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

	kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
	kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);

	/* Preset write-only bits of the Control Register cache. */
	cached_kn02_csr = *csr | KN02_CSR_LEDS;

	/* Set normal ECC detection and generation. */
	cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
	/* Enable ECC correction. */
	cached_kn02_csr |= KN02_CSR_CORRECT;
	*csr = cached_kn02_csr;
	iob();
}

static inline void dec_kn03_be_init(void)
{
	volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
	volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);

	kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
	kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);

	/*
	 * Set normal ECC detection and generation, enable ECC correction.
	 * For KN05 we also need to make sure EE (?) is enabled in the MB.
	 * Otherwise DBE/IBE exceptions would be masked but bus error
	 * interrupts would still arrive, resulting in an inevitable crash
	 * if get_dbe() triggers one.
	 */
	*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
	       KN03_MCR_CORRECT;
	if (current_cpu_type() == CPU_R4400SC)
		*mbcs |= KN4K_MB_CSR_EE;
	fast_iob();
}

void __init dec_ecc_be_init(void)
{
	if (mips_machtype == MACH_DS5000_200)
		dec_kn02_be_init();
	else
		dec_kn03_be_init();

	/* Clear any leftover errors from the firmware. */
	dec_ecc_be_ack();
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Bus error event handling code for systems equipped with ECC
	3	* handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
	4	* 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
	5	* 5900/260 (KN05) systems.
	6	*
64dac503	7	* Copyright (c) 2003, 2005 Maciej W. Rozycki
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#include <linux/init.h>
64dac503	16	#include <linux/interrupt.h>
1da177e4 LT	17	#include <linux/kernel.h>
1da177e4 LT	18	#include <linux/sched.h>
1da177e4 LT	19	#include <linux/types.h>
	20
	21	#include <asm/addrspace.h>
	22	#include <asm/bootinfo.h>
	23	#include <asm/cpu.h>
6dab2f45	24	#include <asm/irq_regs.h>
1da177e4	25	#include <asm/processor.h>
49afb1f6	26	#include <asm/ptrace.h>
1da177e4 LT	27	#include <asm/traps.h>
	28
	29	#include <asm/dec/ecc.h>
	30	#include <asm/dec/kn02.h>
	31	#include <asm/dec/kn03.h>
	32	#include <asm/dec/kn05.h>
	33
	34	static volatile u32 *kn0x_erraddr;
	35	static volatile u32 *kn0x_chksyn;
	36
	37	static inline void dec_ecc_be_ack(void)
	38	{
	39	kn0x_erraddr = 0; / any write clears the IRQ */
	40	iob();
	41	}
	42
	43	static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
	44	{
	45	static const char excstr[] = "exception";
	46	static const char intstr[] = "interrupt";
	47	static const char cpustr[] = "CPU";
	48	static const char dmastr[] = "DMA";
	49	static const char readstr[] = "read";
	50	static const char mreadstr[] = "memory read";
	51	static const char writestr[] = "write";
	52	static const char mwritstr[] = "partial memory write";
	53	static const char timestr[] = "timeout";
	54	static const char overstr[] = "overrun";
	55	static const char eccstr[] = "ECC error";
	56
	57	const char kind, agent, cycle, event;
	58	const char status = "", xbit = "", *fmt = "";
64dac503	59	unsigned long address;
1da177e4 LT	60	u16 syn = 0, sngl;
	61
	62	int i = 0;
	63
	64	u32 erraddr = *kn0x_erraddr;
	65	u32 chksyn = *kn0x_chksyn;
	66	int action = MIPS_BE_FATAL;
	67
64dac503	68	/* For non-ECC ack ASAP, so that any subsequent errors get caught. */
1da177e4 LT	69	if ((erraddr & (KN0X_EAR_VALID \| KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
	70	dec_ecc_be_ack();
	71
	72	kind = invoker ? intstr : excstr;
	73
	74	if (!(erraddr & KN0X_EAR_VALID)) {
	75	/* No idea what happened. */
64dac503	76	printk(KERN_ALERT "Unidentified bus error %s\n", kind);
1da177e4 LT	77	return action;
	78	}
	79
	80	agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;
	81
	82	if (erraddr & KN0X_EAR_ECCERR) {
	83	/* An ECC error on a CPU or DMA transaction. */
	84	cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
	85	event = eccstr;
	86	} else {
	87	/* A CPU timeout or a DMA overrun. */
	88	cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
	89	event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
	90	}
	91
	92	address = erraddr & KN0X_EAR_ADDRESS;
	93	/* For ECC errors on reads adjust for MT pipelining. */
	94	if ((erraddr & (KN0X_EAR_WRITE \| KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
	95	address = (address & ~0xfffLL) \| ((address - 5) & 0xfffLL);
	96	address <<= 2;
	97
	98	/* Only CPU errors are fixable. */
	99	if (erraddr & KN0X_EAR_CPU && is_fixup)
	100	action = MIPS_BE_FIXUP;
	101
	102	if (erraddr & KN0X_EAR_ECCERR) {
	103	static const u8 data_sbit[32] = {
	104	0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
	105	0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
	106	0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
	107	0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
	108	};
	109	static const u8 data_mbit[25] = {
	110	0x07, 0x0d, 0x1f,
	111	0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
	112	0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
	113	0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
	114	};
	115	static const char sbestr[] = "corrected single";
	116	static const char dbestr[] = "uncorrectable double";
	117	static const char mbestr[] = "uncorrectable multiple";
	118
	119	if (!(address & 0x4))
	120	syn = chksyn; /* Low bank. */
	121	else
	122	syn = chksyn >> 16; /* High bank. */
	123
	124	if (!(syn & KN0X_ESR_VLDLO)) {
	125	/* Ack now, no rewrite will happen. */
	126	dec_ecc_be_ack();
	127
64dac503	128	fmt = KERN_ALERT "%s" "invalid\n";
1da177e4 LT	129	} else {
	130	sngl = syn & KN0X_ESR_SNGLO;
	131	syn &= KN0X_ESR_SYNLO;
	132
	133	/*
	134	* Multibit errors may be tagged incorrectly;
	135	* check the syndrome explicitly.
	136	*/
	137	for (i = 0; i < 25; i++)
	138	if (syn == data_mbit[i])
	139	break;
	140
	141	if (i < 25) {
	142	status = mbestr;
	143	} else if (!sngl) {
	144	status = dbestr;
	145	} else {
3bd4c902 MR	146	volatile u32 *ptr =
3bd4c902 MR	147	(void *)CKSEG1ADDR(address);
1da177e4 LT	148
	149	ptr = ptr; /* Rewrite. */
	150	iob();
	151
	152	status = sbestr;
	153	action = MIPS_BE_DISCARD;
	154	}
	155
	156	/* Ack now, now we've rewritten (or not). */
	157	dec_ecc_be_ack();
	158
	159	if (syn && syn == (syn & -syn)) {
	160	if (syn == 0x01) {
	161	fmt = KERN_ALERT "%s"
	162	"%#04x -- %s bit error "
64dac503	163	"at check bit C%s\n";
1da177e4 LT	164	xbit = "X";
	165	} else {
	166	fmt = KERN_ALERT "%s"
	167	"%#04x -- %s bit error "
64dac503	168	"at check bit C%s%u\n";
1da177e4 LT	169	}
	170	i = syn >> 2;
	171	} else {
	172	for (i = 0; i < 32; i++)
	173	if (syn == data_sbit[i])
	174	break;
	175	if (i < 32)
	176	fmt = KERN_ALERT "%s"
	177	"%#04x -- %s bit error "
64dac503	178	"at data bit D%s%u\n";
1da177e4 LT	179	else
1da177e4 LT	180	fmt = KERN_ALERT "%s"
64dac503	181	"%#04x -- %s bit error\n";
1da177e4 LT	182	}
	183	}
	184	}
	185
	186	if (action != MIPS_BE_FIXUP)
64dac503	187	printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
1da177e4 LT	188	kind, agent, cycle, event, address);
	189
	190	if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
	191	printk(fmt, " ECC syndrome ", syn, status, xbit, i);
	192
	193	return action;
	194	}
	195
	196	int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
	197	{
	198	return dec_ecc_be_backend(regs, is_fixup, 0);
	199	}
	200
6dab2f45	201	irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
1da177e4	202	{
6dab2f45 RB	203	struct pt_regs *regs = get_irq_regs();
6dab2f45 RB	204
1da177e4 LT	205	int action = dec_ecc_be_backend(regs, 0, 1);
	206
	207	if (action == MIPS_BE_DISCARD)
68e4a86c	208	return IRQ_HANDLED;
1da177e4 LT	209
1da177e4 LT	210	/*
64dac503 MR	211	* FIXME: Find the affected processes and kill them, otherwise
64dac503 MR	212	* we must die.
1da177e4 LT	213	*
	214	* The interrupt is asynchronously delivered thus EPC and RA
	215	* may be irrelevant, but are printed for a reference.
	216	*/
	217	printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
	218	regs->cp0_epc, regs->regs[31]);
	219	die("Unrecoverable bus error", regs);
	220	}
	221
	222
	223	/*
	224	* Initialization differs a bit between KN02 and KN03/KN05, so we
	225	* need two variants. Once set up, all systems can be handled the
	226	* same way.
	227	*/
	228	static inline void dec_kn02_be_init(void)
	229	{
a5fc9c0b	230	volatile u32 csr = (void )CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
1da177e4	231
a5fc9c0b MR	232	kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
a5fc9c0b MR	233	kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
1da177e4	234
1da177e4	235	/* Preset write-only bits of the Control Register cache. */
64dac503	236	cached_kn02_csr = *csr \| KN02_CSR_LEDS;
1da177e4 LT	237
	238	/* Set normal ECC detection and generation. */
	239	cached_kn02_csr &= ~(KN02_CSR_DIAGCHK \| KN02_CSR_DIAGGEN);
	240	/* Enable ECC correction. */
	241	cached_kn02_csr \|= KN02_CSR_CORRECT;
	242	*csr = cached_kn02_csr;
	243	iob();
1da177e4 LT	244	}
	245
	246	static inline void dec_kn03_be_init(void)
	247	{
a5fc9c0b MR	248	volatile u32 mcr = (void )CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
a5fc9c0b MR	249	volatile u32 mbcs = (void )CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
1da177e4	250
a5fc9c0b MR	251	kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
a5fc9c0b MR	252	kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
42a3b4f2	253
1da177e4 LT	254	/*
	255	* Set normal ECC detection and generation, enable ECC correction.
	256	* For KN05 we also need to make sure EE (?) is enabled in the MB.
	257	* Otherwise DBE/IBE exceptions would be masked but bus error
	258	* interrupts would still arrive, resulting in an inevitable crash
	259	* if get_dbe() triggers one.
	260	*/
	261	mcr = (mcr & ~(KN03_MCR_DIAGCHK \| KN03_MCR_DIAGGEN)) \|
	262	KN03_MCR_CORRECT;
10cc3529	263	if (current_cpu_type() == CPU_R4400SC)
64dac503	264	*mbcs \|= KN4K_MB_CSR_EE;
1da177e4 LT	265	fast_iob();
	266	}
	267
	268	void __init dec_ecc_be_init(void)
	269	{
	270	if (mips_machtype == MACH_DS5000_200)
	271	dec_kn02_be_init();
	272	else
	273	dec_kn03_be_init();
	274
	275	/* Clear any leftover errors from the firmware. */
	276	dec_ecc_be_ack();
	277	}