projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle | |
| 7 | */ | |
| 8 | #ifndef _ASM_BRANCH_H | |
| 9 | #define _ASM_BRANCH_H | |
| 10 | ||
| 5160d45d RB |
11 | #include <asm/cpu-features.h> |
| 12 | #include <asm/mipsregs.h> | |
| 1da177e4 | 13 | #include <asm/ptrace.h> |
| d8d4e3ae | 14 | #include <asm/inst.h> |
| 1da177e4 | 15 | |
| fb6883e5 LY |
16 | extern int __isa_exception_epc(struct pt_regs *regs); |
| 17 | extern int __compute_return_epc(struct pt_regs *regs); | |
| 18 | extern int __compute_return_epc_for_insn(struct pt_regs *regs, | |
| 19 | union mips_instruction insn); | |
| 20 | extern int __microMIPS_compute_return_epc(struct pt_regs *regs); | |
| 8508488f | 21 | extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); |
| fb6883e5 LY |
22 | |
| 23 | ||
| 1da177e4 LT |
24 | static inline int delay_slot(struct pt_regs *regs) |
| 25 | { | |
| 26 | return regs->cp0_cause & CAUSEF_BD; | |
| 27 | } | |
| 28 | ||
| 5a7ebbf8 RB |
29 | static inline void clear_delay_slot(struct pt_regs *regs) |
| 30 | { | |
| 31 | regs->cp0_cause &= ~CAUSEF_BD; | |
| 32 | } | |
| 33 | ||
| 34 | static inline void set_delay_slot(struct pt_regs *regs) | |
| 35 | { | |
| 36 | regs->cp0_cause |= CAUSEF_BD; | |
| 37 | } | |
| 38 | ||
| 1da177e4 LT |
39 | static inline unsigned long exception_epc(struct pt_regs *regs) |
| 40 | { | |
| fb6883e5 | 41 | if (likely(!delay_slot(regs))) |
| 1da177e4 LT |
42 | return regs->cp0_epc; |
| 43 | ||
| fb6883e5 LY |
44 | if (get_isa16_mode(regs->cp0_epc)) |
| 45 | return __isa_exception_epc(regs); | |
| 46 | ||
| 1da177e4 LT |
47 | return regs->cp0_epc + 4; |
| 48 | } | |
| 49 | ||
| d8d4e3ae MS |
50 | #define BRANCH_LIKELY_TAKEN 0x0001 |
| 51 | ||
| 1da177e4 LT |
52 | static inline int compute_return_epc(struct pt_regs *regs) |
| 53 | { | |
| fb6883e5 LY |
54 | if (get_isa16_mode(regs->cp0_epc)) { |
| 55 | if (cpu_has_mmips) | |
| 56 | return __microMIPS_compute_return_epc(regs); | |
| 8508488f SH |
57 | if (cpu_has_mips16) |
| 58 | return __MIPS16e_compute_return_epc(regs); | |
| fb6883e5 LY |
59 | return regs->cp0_epc; |
| 60 | } | |
| 61 | ||
| 1da177e4 LT |
62 | if (!delay_slot(regs)) { |
| 63 | regs->cp0_epc += 4; | |
| 64 | return 0; | |
| 65 | } | |
| 66 | ||
| 67 | return __compute_return_epc(regs); | |
| 68 | } | |
| 69 | ||
| 8508488f SH |
70 | static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, |
| 71 | union mips16e_instruction *inst) | |
| 72 | { | |
| 73 | if (likely(!delay_slot(regs))) { | |
| 74 | if (inst->ri.opcode == MIPS16e_extend_op) { | |
| 75 | regs->cp0_epc += 4; | |
| 76 | return 0; | |
| 77 | } | |
| 78 | regs->cp0_epc += 2; | |
| 79 | return 0; | |
| 80 | } | |
| 81 | ||
| 82 | return __MIPS16e_compute_return_epc(regs); | |
| 83 | } | |
| 84 | ||
| 1da177e4 | 85 | #endif /* _ASM_BRANCH_H */ |