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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle | |
7 | */ | |
8 | #ifndef _ASM_BRANCH_H | |
9 | #define _ASM_BRANCH_H | |
10 | ||
11 | #include <asm/ptrace.h> | |
d8d4e3ae | 12 | #include <asm/inst.h> |
1da177e4 | 13 | |
fb6883e5 LY |
14 | extern int __isa_exception_epc(struct pt_regs *regs); |
15 | extern int __compute_return_epc(struct pt_regs *regs); | |
16 | extern int __compute_return_epc_for_insn(struct pt_regs *regs, | |
17 | union mips_instruction insn); | |
18 | extern int __microMIPS_compute_return_epc(struct pt_regs *regs); | |
8508488f | 19 | extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); |
fb6883e5 LY |
20 | |
21 | ||
1da177e4 LT |
22 | static inline int delay_slot(struct pt_regs *regs) |
23 | { | |
24 | return regs->cp0_cause & CAUSEF_BD; | |
25 | } | |
26 | ||
5a7ebbf8 RB |
27 | static inline void clear_delay_slot(struct pt_regs *regs) |
28 | { | |
29 | regs->cp0_cause &= ~CAUSEF_BD; | |
30 | } | |
31 | ||
32 | static inline void set_delay_slot(struct pt_regs *regs) | |
33 | { | |
34 | regs->cp0_cause |= CAUSEF_BD; | |
35 | } | |
36 | ||
1da177e4 LT |
37 | static inline unsigned long exception_epc(struct pt_regs *regs) |
38 | { | |
fb6883e5 | 39 | if (likely(!delay_slot(regs))) |
1da177e4 LT |
40 | return regs->cp0_epc; |
41 | ||
fb6883e5 LY |
42 | if (get_isa16_mode(regs->cp0_epc)) |
43 | return __isa_exception_epc(regs); | |
44 | ||
1da177e4 LT |
45 | return regs->cp0_epc + 4; |
46 | } | |
47 | ||
d8d4e3ae MS |
48 | #define BRANCH_LIKELY_TAKEN 0x0001 |
49 | ||
1da177e4 LT |
50 | static inline int compute_return_epc(struct pt_regs *regs) |
51 | { | |
fb6883e5 LY |
52 | if (get_isa16_mode(regs->cp0_epc)) { |
53 | if (cpu_has_mmips) | |
54 | return __microMIPS_compute_return_epc(regs); | |
8508488f SH |
55 | if (cpu_has_mips16) |
56 | return __MIPS16e_compute_return_epc(regs); | |
fb6883e5 LY |
57 | return regs->cp0_epc; |
58 | } | |
59 | ||
1da177e4 LT |
60 | if (!delay_slot(regs)) { |
61 | regs->cp0_epc += 4; | |
62 | return 0; | |
63 | } | |
64 | ||
65 | return __compute_return_epc(regs); | |
66 | } | |
67 | ||
8508488f SH |
68 | static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, |
69 | union mips16e_instruction *inst) | |
70 | { | |
71 | if (likely(!delay_slot(regs))) { | |
72 | if (inst->ri.opcode == MIPS16e_extend_op) { | |
73 | regs->cp0_epc += 4; | |
74 | return 0; | |
75 | } | |
76 | regs->cp0_epc += 2; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | return __MIPS16e_compute_return_epc(regs); | |
81 | } | |
82 | ||
1da177e4 | 83 | #endif /* _ASM_BRANCH_H */ |