[deliverable/linux.git] / arch / mips / include / asm / cpu-info.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H

#include <linux/types.h>

#include <asm/cache.h>

/*
 * Descriptor for a cache
 */
struct cache_desc {
	unsigned int waysize;	/* Bytes per way */
	unsigned short sets;	/* Number of lines per set */
	unsigned char ways;	/* Number of ways */
	unsigned char linesz;	/* Size of line in bytes */
	unsigned char waybit;	/* Bits to select in a cache set */
	unsigned char flags;	/* Flags describing cache properties */
};

/*
 * Flag definitions
 */
#define MIPS_CACHE_NOT_PRESENT	0x00000001
#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */
#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */

struct cpuinfo_mips {
	unsigned long		asid_cache;

	/*
	 * Capability and feature descriptor structure for MIPS CPU
	 */
	unsigned long		ases;
	unsigned long long	options;
	unsigned int		udelay_val;
	unsigned int		processor_id;
	unsigned int		fpu_id;
	unsigned int		fpu_csr31;
	unsigned int		fpu_msk31;
	unsigned int		msa_id;
	unsigned int		cputype;
	int			isa_level;
	int			tlbsize;
	int			tlbsizevtlb;
	int			tlbsizeftlbsets;
	int			tlbsizeftlbways;
	struct cache_desc	icache; /* Primary I-cache */
	struct cache_desc	dcache; /* Primary D or combined I/D cache */
	struct cache_desc	vcache; /* Victim cache, between pcache and scache */
	struct cache_desc	scache; /* Secondary cache */
	struct cache_desc	tcache; /* Tertiary/split secondary cache */
	int			srsets; /* Shadow register sets */
	int			package;/* physical package number */
	int			core;	/* physical core number */
#ifdef CONFIG_64BIT
	int			vmbits; /* Virtual memory size in bits */
#endif
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
	/*
	 * There is not necessarily a 1:1 mapping of VPE num to CPU number
	 * in particular on multi-core systems.
	 */
	int			vpe_id;	 /* Virtual Processor number */
#endif
	void			*data;	/* Additional data */
	unsigned int		watch_reg_count;   /* Number that exist */
	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */
#define NUM_WATCH_REGS 4
	u16			watch_reg_masks[NUM_WATCH_REGS];
	unsigned int		kscratch_mask; /* Usable KScratch mask. */
	/*
	 * Cache Coherency attribute for write-combine memory writes.
	 * (shifted by _CACHE_SHIFT)
	 */
	unsigned int		writecombine;
	/*
	 * Simple counter to prevent enabling HTW in nested
	 * htw_start/htw_stop calls
	 */
	unsigned int		htw_seq;
} __attribute__((aligned(SMP_CACHE_BYTES)));

extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
#define boot_cpu_data cpu_data[0]

extern void cpu_probe(void);
extern void cpu_report(void);

extern const char *__cpu_name[];
#define cpu_name_string()	__cpu_name[raw_smp_processor_id()]

struct seq_file;
struct notifier_block;

extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);

#define proc_cpuinfo_notifier(fn, pri)					\
({									\
	static struct notifier_block fn##_nb = {			\
		.notifier_call = fn,					\
		.priority = pri						\
	};								\
									\
	register_proc_cpuinfo_notifier(&fn##_nb);			\
})

struct proc_cpuinfo_notifier_args {
	struct seq_file *m;
	unsigned long n;
};

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
# define cpu_vpe_id(cpuinfo)	((cpuinfo)->vpe_id)
#else
# define cpu_vpe_id(cpuinfo)	({ (void)cpuinfo; 0; })
#endif

#endif /* __ASM_CPU_INFO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 Waldorf GMBH
	7	* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
	8	* Copyright (C) 1996 Paul M. Antoine
	9	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
4194318c	10	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	11	*/
	12	#ifndef __ASM_CPU_INFO_H
	13	#define __ASM_CPU_INFO_H
	14
6aa3524c DD	15	#include <linux/types.h>
6aa3524c DD	16
1da177e4 LT	17	#include <asm/cache.h>
1da177e4 LT	18
1da177e4 LT	19	/*
	20	* Descriptor for a cache
	21	*/
	22	struct cache_desc {
1da177e4	23	unsigned int waysize; /* Bytes per way */
6f2c3fa0 RB	24	unsigned short sets; /* Number of lines per set */
	25	unsigned char ways; /* Number of ways */
	26	unsigned char linesz; /* Size of line in bytes */
	27	unsigned char waybit; /* Bits to select in a cache set */
	28	unsigned char flags; /* Flags describing cache properties */
1da177e4 LT	29	};
	30
	31	/*
	32	* Flag definitions
	33	*/
	34	#define MIPS_CACHE_NOT_PRESENT 0x00000001
	35	#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
	36	#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
	37	#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
	38	#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
de62893b	39	#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
1da177e4 LT	40
1da177e4 LT	41	struct cpuinfo_mips {
e5eb925a	42	unsigned long asid_cache;
1da177e4 LT	43
	44	/*
	45	* Capability and feature descriptor structure for MIPS CPU
	46	*/
4194318c	47	unsigned long ases;
03a58777	48	unsigned long long options;
e5eb925a	49	unsigned int udelay_val;
1da177e4 LT	50	unsigned int processor_id;
1da177e4 LT	51	unsigned int fpu_id;
9b26616c MR	52	unsigned int fpu_csr31;
9b26616c MR	53	unsigned int fpu_msk31;
a5e9a69e	54	unsigned int msa_id;
1da177e4 LT	55	unsigned int cputype;
	56	int isa_level;
	57	int tlbsize;
75b5b5e0 LY	58	int tlbsizevtlb;
	59	int tlbsizeftlbsets;
	60	int tlbsizeftlbways;
70342287 RB	61	struct cache_desc icache; /* Primary I-cache */
70342287 RB	62	struct cache_desc dcache; /* Primary D or combined I/D cache */
b2edcfc8	63	struct cache_desc vcache; /* Victim cache, between pcache and scache */
70342287 RB	64	struct cache_desc scache; /* Secondary cache */
	65	struct cache_desc tcache; /* Tertiary/split secondary cache */
	66	int srsets; /* Shadow register sets */
bda4584c	67	int package;/* physical package number */
0ab7aefc	68	int core; /* physical core number */
91dfc423	69	#ifdef CONFIG_64BIT
70342287	70	int vmbits; /* Virtual memory size in bits */
91dfc423	71	#endif
5a3e7c02	72	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_CPU_MIPSR6)
41c594ab	73	/*
b633648c RB	74	* There is not necessarily a 1:1 mapping of VPE num to CPU number
b633648c RB	75	* in particular on multi-core systems.
41c594ab	76	*/
70342287	77	int vpe_id; /* Virtual Processor number */
0ab7aefc	78	#endif
70342287	79	void data; / Additional data */
6aa3524c DD	80	unsigned int watch_reg_count; /* Number that exist */
	81	unsigned int watch_reg_use_cnt; /* Usable by ptrace */
	82	#define NUM_WATCH_REGS 4
	83	u16 watch_reg_masks[NUM_WATCH_REGS];
e77c32fe	84	unsigned int kscratch_mask; /* Usable KScratch mask. */
4f12b91d MC	85	/*
	86	* Cache Coherency attribute for write-combine memory writes.
	87	* (shifted by _CACHE_SHIFT)
	88	*/
	89	unsigned int writecombine;
ed4cbc81 MC	90	/*
	91	* Simple counter to prevent enabling HTW in nested
	92	* htw_start/htw_stop calls
	93	*/
	94	unsigned int htw_seq;
1da177e4 LT	95	} __attribute__((aligned(SMP_CACHE_BYTES)));
	96
	97	extern struct cpuinfo_mips cpu_data[];
	98	#define current_cpu_data cpu_data[smp_processor_id()]
53dc8028	99	#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
c5f66596	100	#define boot_cpu_data cpu_data[0]
1da177e4 LT	101
	102	extern void cpu_probe(void);
	103	extern void cpu_report(void);
	104
9966db25	105	extern const char *__cpu_name[];
e95008a1	106	#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
9966db25	107
d6d3c9af RB	108	struct seq_file;
	109	struct notifier_block;
	110
	111	extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
	112	extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
	113
	114	#define proc_cpuinfo_notifier(fn, pri) \
	115	({ \
	116	static struct notifier_block fn##_nb = { \
	117	.notifier_call = fn, \
	118	.priority = pri \
	119	}; \
	120	\
	121	register_proc_cpuinfo_notifier(&fn##_nb); \
	122	})
	123
	124	struct proc_cpuinfo_notifier_args {
	125	struct seq_file *m;
	126	unsigned long n;
	127	};
	128
5a3e7c02	129	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_CPU_MIPSR6)
b86c2247 PB	130	# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
b86c2247 PB	131	#else
34bd3e6b	132	# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
b86c2247 PB	133	#endif
b86c2247 PB	134
1da177e4	135	#endif /* __ASM_CPU_INFO_H */