projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Definitions for the interrupt related bits in the I/O ASIC | |
| 7 | * interrupt status register (and the interrupt mask register, of course) | |
| 8 | * | |
| 9 | * Created with Information from: | |
| 10 | * | |
| 11 | * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" | |
| 12 | * | |
| 13 | * and the Mach Sources | |
| 14 | * | |
| 15 | * Copyright (C) 199x the Anonymous | |
| 16 | * Copyright (C) 2002 Maciej W. Rozycki | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef __ASM_DEC_IOASIC_INTS_H | |
| 20 | #define __ASM_DEC_IOASIC_INTS_H | |
| 21 | ||
| 22 | /* | |
| 23 | * The upper 16 bits are a part of the I/O ASIC's internal DMA engine | |
| 24 | * and thus are common to all I/O ASIC machines. The exception is | |
| 25 | * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise | |
| 26 | * unused) and has a different SCC wiring. | |
| 27 | */ | |
| 28 | /* all systems */ | |
| 29 | #define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */ | |
| 30 | #define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */ | |
| 31 | #define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */ | |
| 32 | #define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */ | |
| 33 | #define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */ | |
| 34 | #define IO_INR_ASC_ERR 18 /* ASC page overrun */ | |
| 35 | #define IO_INR_ASC_MERR 17 /* ASC memory read error */ | |
| 36 | #define IO_INR_LANCE_MERR 16 /* LANCE memory read error */ | |
| 37 | ||
| 38 | /* except Maxine */ | |
| 39 | #define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */ | |
| 40 | #define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */ | |
| 41 | #define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */ | |
| 42 | #define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */ | |
| 43 | #define IO_INR_RES_23 23 /* unused */ | |
| 44 | #define IO_INR_RES_22 22 /* unused */ | |
| 45 | #define IO_INR_RES_21 21 /* unused */ | |
| 46 | #define IO_INR_RES_20 20 /* unused */ | |
| 47 | ||
| 48 | /* Maxine */ | |
| 49 | #define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */ | |
| 50 | #define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */ | |
| 51 | #define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */ | |
| 52 | #define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */ | |
| 53 | #define IO_INR_FLOPPY_ERR 23 /* FDC error */ | |
| 54 | #define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */ | |
| 55 | #define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */ | |
| 56 | #define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */ | |
| 57 | ||
| 58 | #define IO_INR_DMA 16 /* first DMA IRQ */ | |
| 59 | ||
| 60 | /* | |
| 61 | * The lower 16 bits are system-specific and thus defined in | |
| 62 | * system-specific headers. | |
| 63 | */ | |
| 64 | ||
| 65 | ||
| 66 | #define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ | |
| 67 | #define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */ | |
| 68 | ||
| 69 | #define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE) | |
| 70 | #define IO_IRQ_MASK(n) (1 << (n)) | |
| 71 | #define IO_IRQ_ALL 0x0000ffff | |
| 72 | #define IO_IRQ_DMA 0xffff0000 | |
| 73 | ||
| 74 | #endif /* __ASM_DEC_IOASIC_INTS_H */ |