[deliverable/linux.git] / arch / mips / include / asm / gic.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 *
 * GIC Register Definitions
 *
 */
#ifndef _ASM_GICREGS_H
#define _ASM_GICREGS_H

#include <linux/bitmap.h>
#include <linux/threads.h>

#include <irq.h>

#undef	GICISBYTELITTLEENDIAN

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0

#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr)		(*(volatile unsigned int *) (addr))
#define REG(base, offs)		REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys)	REG32((unsigned long)(base) + (phys))

/* Accessors */
#define GIC_REG(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ADDR(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset)

#define GIC_ABS_REG(segment, offset) \
	(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ABS_ADDR(segment, offset) \
	(_gic_base + segment##_##SECTION_OFS + offset)

#ifdef GICISBYTELITTLEENDIAN
#define GICREAD(reg, data)	((data) = (reg), (data) = le32_to_cpu(data))
#define GICWRITE(reg, data)	((reg) = cpu_to_le32(data))
#else
#define GICREAD(reg, data)	((data) = (reg))
#define GICWRITE(reg, data)	((reg) = (data))
#endif
#define GICBIS(reg, mask, bits)			\
	do { u32 data;				\
		GICREAD(reg, data);		\
		data &= ~(mask);		\
		data |= ((bits) & (mask));	\
		GICWRITE((reg), data);		\
	} while (0)


/* GIC Address Space */
#define SHARED_SECTION_OFS		0x0000
#define SHARED_SECTION_SIZE		0x8000
#define VPE_LOCAL_SECTION_OFS		0x8000
#define VPE_LOCAL_SECTION_SIZE		0x4000
#define VPE_OTHER_SECTION_OFS		0xc000
#define VPE_OTHER_SECTION_SIZE		0x4000
#define USM_VISIBLE_SECTION_OFS		0x10000
#define USM_VISIBLE_SECTION_SIZE	0x10000

/* Register Map for Shared Section */

#define GIC_SH_CONFIG_OFS		0x0000

/* Shared Global Counter */
#define GIC_SH_COUNTER_31_00_OFS	0x0010
#define GIC_SH_COUNTER_63_32_OFS	0x0014
#define GIC_SH_REVISIONID_OFS		0x0020

/* Interrupt Polarity */
#define GIC_SH_POL_31_0_OFS		0x0100
#define GIC_SH_POL_63_32_OFS		0x0104
#define GIC_SH_POL_95_64_OFS		0x0108
#define GIC_SH_POL_127_96_OFS		0x010c
#define GIC_SH_POL_159_128_OFS		0x0110
#define GIC_SH_POL_191_160_OFS		0x0114
#define GIC_SH_POL_223_192_OFS		0x0118
#define GIC_SH_POL_255_224_OFS		0x011c

/* Edge/Level Triggering */
#define GIC_SH_TRIG_31_0_OFS		0x0180
#define GIC_SH_TRIG_63_32_OFS		0x0184
#define GIC_SH_TRIG_95_64_OFS		0x0188
#define GIC_SH_TRIG_127_96_OFS		0x018c
#define GIC_SH_TRIG_159_128_OFS		0x0190
#define GIC_SH_TRIG_191_160_OFS		0x0194
#define GIC_SH_TRIG_223_192_OFS		0x0198
#define GIC_SH_TRIG_255_224_OFS		0x019c

/* Dual Edge Triggering */
#define GIC_SH_DUAL_31_0_OFS		0x0200
#define GIC_SH_DUAL_63_32_OFS		0x0204
#define GIC_SH_DUAL_95_64_OFS		0x0208
#define GIC_SH_DUAL_127_96_OFS		0x020c
#define GIC_SH_DUAL_159_128_OFS		0x0210
#define GIC_SH_DUAL_191_160_OFS		0x0214
#define GIC_SH_DUAL_223_192_OFS		0x0218
#define GIC_SH_DUAL_255_224_OFS		0x021c

/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS		0x0280

/* Reset Mask - Disables Interrupt */
#define GIC_SH_RMASK_31_0_OFS		0x0300
#define GIC_SH_RMASK_63_32_OFS		0x0304
#define GIC_SH_RMASK_95_64_OFS		0x0308
#define GIC_SH_RMASK_127_96_OFS		0x030c
#define GIC_SH_RMASK_159_128_OFS	0x0310
#define GIC_SH_RMASK_191_160_OFS	0x0314
#define GIC_SH_RMASK_223_192_OFS	0x0318
#define GIC_SH_RMASK_255_224_OFS	0x031c

/* Set Mask (WO) - Enables Interrupt */
#define GIC_SH_SMASK_31_0_OFS		0x0380
#define GIC_SH_SMASK_63_32_OFS		0x0384
#define GIC_SH_SMASK_95_64_OFS		0x0388
#define GIC_SH_SMASK_127_96_OFS		0x038c
#define GIC_SH_SMASK_159_128_OFS	0x0390
#define GIC_SH_SMASK_191_160_OFS	0x0394
#define GIC_SH_SMASK_223_192_OFS	0x0398
#define GIC_SH_SMASK_255_224_OFS	0x039c

/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
#define GIC_SH_MASK_31_0_OFS		0x0400
#define GIC_SH_MASK_63_32_OFS		0x0404
#define GIC_SH_MASK_95_64_OFS		0x0408
#define GIC_SH_MASK_127_96_OFS		0x040c
#define GIC_SH_MASK_159_128_OFS		0x0410
#define GIC_SH_MASK_191_160_OFS		0x0414
#define GIC_SH_MASK_223_192_OFS		0x0418
#define GIC_SH_MASK_255_224_OFS		0x041c

/* Pending Global Interrupts (RO) */
#define GIC_SH_PEND_31_0_OFS		0x0480
#define GIC_SH_PEND_63_32_OFS		0x0484
#define GIC_SH_PEND_95_64_OFS		0x0488
#define GIC_SH_PEND_127_96_OFS		0x048c
#define GIC_SH_PEND_159_128_OFS		0x0490
#define GIC_SH_PEND_191_160_OFS		0x0494
#define GIC_SH_PEND_223_192_OFS		0x0498
#define GIC_SH_PEND_255_224_OFS		0x049c

#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500

/* Maps Interrupt X to a Pin */
#define GIC_SH_MAP_TO_PIN(intr) \
	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))

#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000

/* Maps Interrupt X to a VPE */
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))

/* Convert an interrupt number to a byte offset/bit for multi-word registers */
#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
#define GIC_INTR_BIT(intr) ((intr) % 32)

/* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS		0x0100
#define GIC_SET_POLARITY(intr, pol) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
		GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
		(pol) << GIC_INTR_BIT(intr))

/* Triggering : Reset Value is always 0 */
#define GIC_SH_SET_TRIGGER_OFS		0x0180
#define GIC_SET_TRIGGER(intr, trig) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
		GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
		(trig) << GIC_INTR_BIT(intr))

/* Mask manipulation */
#define GIC_SH_SMASK_OFS		0x0380
#define GIC_SET_INTR_MASK(intr) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
#define GIC_SH_RMASK_OFS		0x0300
#define GIC_CLR_INTR_MASK(intr) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))

/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS			0x0000
#define GIC_VPE_PEND_OFS		0x0004
#define GIC_VPE_MASK_OFS		0x0008
#define GIC_VPE_RMASK_OFS		0x000c
#define GIC_VPE_SMASK_OFS		0x0010
#define GIC_VPE_WD_MAP_OFS		0x0040
#define GIC_VPE_COMPARE_MAP_OFS		0x0044
#define GIC_VPE_TIMER_MAP_OFS		0x0048
#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
#define GIC_VPE_SWINT0_MAP_OFS		0x0054
#define GIC_VPE_SWINT1_MAP_OFS		0x0058
#define GIC_VPE_OTHER_ADDR_OFS		0x0080
#define GIC_VPE_WD_CONFIG0_OFS		0x0090
#define GIC_VPE_WD_COUNT0_OFS		0x0094
#define GIC_VPE_WD_INITIAL0_OFS		0x0098
#define GIC_VPE_COMPARE_LO_OFS		0x00a0
#define GIC_VPE_COMPARE_HI_OFS		0x00a4

#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
#define GIC_VPE_EIC_SS(intr) \
	(GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))

#define GIC_VPE_EIC_VEC_BASE		0x0800
#define GIC_VPE_EIC_VEC(intr) \
	(GIC_VPE_EIC_VEC_BASE + (4 * intr))

#define GIC_VPE_TENABLE_NMI_OFS		0x1000
#define GIC_VPE_TENABLE_YQ_OFS		0x1004
#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084

/* User Mode Visible Section Register Map */
#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004

/* Masks */
#define GIC_SH_CONFIG_COUNTSTOP_SHF	28
#define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)

#define GIC_SH_CONFIG_COUNTBITS_SHF	24
#define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)

#define GIC_SH_CONFIG_NUMINTRS_SHF	16
#define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)

#define GIC_SH_CONFIG_NUMVPES_SHF	0
#define GIC_SH_CONFIG_NUMVPES_MSK	(MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)

#define GIC_SH_WEDGE_SET(intr)		(intr | (0x1 << 31))
#define GIC_SH_WEDGE_CLR(intr)		(intr & ~(0x1 << 31))

#define GIC_MAP_TO_PIN_SHF		31
#define GIC_MAP_TO_PIN_MSK		(MSK(1) << GIC_MAP_TO_PIN_SHF)
#define GIC_MAP_TO_NMI_SHF		30
#define GIC_MAP_TO_NMI_MSK		(MSK(1) << GIC_MAP_TO_NMI_SHF)
#define GIC_MAP_TO_YQ_SHF		29
#define GIC_MAP_TO_YQ_MSK		(MSK(1) << GIC_MAP_TO_YQ_SHF)
#define GIC_MAP_SHF			0
#define GIC_MAP_MSK			(MSK(6) << GIC_MAP_SHF)

/* GIC_VPE_CTL Masks */
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF	2
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
#define GIC_VPE_CTL_TIMER_RTBL_SHF	1
#define GIC_VPE_CTL_TIMER_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
#define GIC_VPE_CTL_EIC_MODE_SHF	0
#define GIC_VPE_CTL_EIC_MODE_MSK	(MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)

/* GIC_VPE_PEND Masks */
#define GIC_VPE_PEND_WD_SHF		0
#define GIC_VPE_PEND_WD_MSK		(MSK(1) << GIC_VPE_PEND_WD_SHF)
#define GIC_VPE_PEND_CMP_SHF		1
#define GIC_VPE_PEND_CMP_MSK		(MSK(1) << GIC_VPE_PEND_CMP_SHF)
#define GIC_VPE_PEND_TIMER_SHF		2
#define GIC_VPE_PEND_TIMER_MSK		(MSK(1) << GIC_VPE_PEND_TIMER_SHF)
#define GIC_VPE_PEND_PERFCOUNT_SHF	3
#define GIC_VPE_PEND_PERFCOUNT_MSK	(MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
#define GIC_VPE_PEND_SWINT0_SHF		4
#define GIC_VPE_PEND_SWINT0_MSK		(MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
#define GIC_VPE_PEND_SWINT1_SHF		5
#define GIC_VPE_PEND_SWINT1_MSK		(MSK(1) << GIC_VPE_PEND_SWINT1_SHF)

/* GIC_VPE_RMASK Masks */
#define GIC_VPE_RMASK_WD_SHF		0
#define GIC_VPE_RMASK_WD_MSK		(MSK(1) << GIC_VPE_RMASK_WD_SHF)
#define GIC_VPE_RMASK_CMP_SHF		1
#define GIC_VPE_RMASK_CMP_MSK		(MSK(1) << GIC_VPE_RMASK_CMP_SHF)
#define GIC_VPE_RMASK_TIMER_SHF		2
#define GIC_VPE_RMASK_TIMER_MSK		(MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
#define GIC_VPE_RMASK_PERFCNT_SHF	3
#define GIC_VPE_RMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
#define GIC_VPE_RMASK_SWINT0_SHF	4
#define GIC_VPE_RMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
#define GIC_VPE_RMASK_SWINT1_SHF	5
#define GIC_VPE_RMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)

/* GIC_VPE_SMASK Masks */
#define GIC_VPE_SMASK_WD_SHF		0
#define GIC_VPE_SMASK_WD_MSK		(MSK(1) << GIC_VPE_SMASK_WD_SHF)
#define GIC_VPE_SMASK_CMP_SHF		1
#define GIC_VPE_SMASK_CMP_MSK		(MSK(1) << GIC_VPE_SMASK_CMP_SHF)
#define GIC_VPE_SMASK_TIMER_SHF		2
#define GIC_VPE_SMASK_TIMER_MSK		(MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
#define GIC_VPE_SMASK_PERFCNT_SHF	3
#define GIC_VPE_SMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
#define GIC_VPE_SMASK_SWINT0_SHF	4
#define GIC_VPE_SMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
#define GIC_VPE_SMASK_SWINT1_SHF	5
#define GIC_VPE_SMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)

/*
 * Set the Mapping of Interrupt X to a VPE.
 */
#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
		 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))

/*
 * Interrupt Meta-data specification. The ipiflag helps
 * in building ipi_map.
 */
struct gic_intr_map {
	unsigned int cpunum;	/* Directed to this CPU */
#define GIC_UNUSED		0xdead			/* Dummy data */
	unsigned int pin;	/* Directed to this Pin */
	unsigned int polarity;	/* Polarity : +/-	*/
	unsigned int trigtype;	/* Trigger  : Edge/Levl */
	unsigned int flags;	/* Misc flags	*/
#define GIC_FLAG_TRANSPARENT   0x01
};

/*
 * This is only used in EIC mode. This helps to figure out which
 * shared interrupts we need to process when we get a vector interrupt.
 */
#define GIC_MAX_SHARED_INTR  0x5
struct gic_shared_intr_map {
	unsigned int num_shared_intr;
	unsigned int intr_list[GIC_MAX_SHARED_INTR];
	unsigned int local_intr_mask;
};

/* GIC nomenclature for Core Interrupt Pins. */
#define GIC_CPU_INT0		0 /* Core Interrupt 2 */
#define GIC_CPU_INT1		1 /* .		      */
#define GIC_CPU_INT2		2 /* .		      */
#define GIC_CPU_INT3		3 /* .		      */
#define GIC_CPU_INT4		4 /* .		      */
#define GIC_CPU_INT5		5 /* Core Interrupt 7 */

/* Local GIC interrupts. */
#define GIC_INT_TMR		(GIC_CPU_INT5)
#define GIC_INT_PERFCTR		(GIC_CPU_INT5)

/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
#define GIC_CPU_TO_VEC_OFFSET	(2)

/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET	(1)

#include <linux/clocksource.h>
#include <linux/irq.h>

extern unsigned int gic_present;
extern unsigned int gic_frequency;
extern unsigned long _gic_base;
extern unsigned int gic_irq_base;
extern unsigned int gic_irq_flags[];
extern struct gic_shared_intr_map gic_shared_intr_map[];

extern void gic_init(unsigned long gic_base_addr,
	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
	unsigned int intrmap_size, unsigned int irqbase);
extern void gic_clocksource_init(unsigned int);
extern unsigned int gic_compare_int (void);
extern cycle_t gic_read_count(void);
extern cycle_t gic_read_compare(void);
extern void gic_write_compare(cycle_t cnt);
extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
extern void gic_bind_eic_interrupt(int irq, int set);
extern unsigned int gic_get_timer_pending(void);
extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src);
extern unsigned int gic_get_int(void);
extern void gic_enable_interrupt(int irq_vec);
extern void gic_disable_interrupt(int irq_vec);
extern void gic_irq_ack(struct irq_data *d);
extern void gic_finish_irq(struct irq_data *d);
extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
#endif /* _ASM_GICREGS_H */
Commit	Line	Data
39b8d525 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000, 07 MIPS Technologies, Inc.
	7	*
	8	* GIC Register Definitions
	9	*
	10	*/
	11	#ifndef _ASM_GICREGS_H
	12	#define _ASM_GICREGS_H
	13
6d9727a7 PB	14	#include <linux/bitmap.h>
	15	#include <linux/threads.h>
	16
c9750481 JD	17	#include <irq.h>
c9750481 JD	18
39b8d525	19	#undef GICISBYTELITTLEENDIAN
39b8d525 RB	20
	21	/* Constants */
	22	#define GIC_POL_POS 1
	23	#define GIC_POL_NEG 0
	24	#define GIC_TRIG_EDGE 1
	25	#define GIC_TRIG_LEVEL 0
	26
39b8d525 RB	27	#define MSK(n) ((1 << (n)) - 1)
39b8d525 RB	28	#define REG32(addr) ((volatile unsigned int ) (addr))
938b2b14 TB	29	#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
938b2b14 TB	30	#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
39b8d525 RB	31
	32	/* Accessors */
	33	#define GIC_REG(segment, offset) \
	34	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
	35	#define GIC_REG_ADDR(segment, offset) \
	36	REG32(_gic_base + segment##_##SECTION_OFS + offset)
	37
	38	#define GIC_ABS_REG(segment, offset) \
2299c49d	39	(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
39b8d525	40	#define GIC_REG_ABS_ADDR(segment, offset) \
2299c49d	41	(_gic_base + segment##_##SECTION_OFS + offset)
39b8d525 RB	42
39b8d525 RB	43	#ifdef GICISBYTELITTLEENDIAN
2299c49d SH	44	#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
2299c49d SH	45	#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
39b8d525	46	#else
2299c49d SH	47	#define GICREAD(reg, data) ((data) = (reg))
2299c49d SH	48	#define GICWRITE(reg, data) ((reg) = (data))
39b8d525	49	#endif
c55b2851 JD	50	#define GICBIS(reg, mask, bits) \
c55b2851 JD	51	do { u32 data; \
f28ff3d1	52	GICREAD(reg, data); \
c55b2851 JD	53	data &= ~(mask); \
	54	data \|= ((bits) & (mask)); \
	55	GICWRITE((reg), data); \
	56	} while (0)
39b8d525 RB	57
	58
	59	/* GIC Address Space */
	60	#define SHARED_SECTION_OFS 0x0000
	61	#define SHARED_SECTION_SIZE 0x8000
	62	#define VPE_LOCAL_SECTION_OFS 0x8000
	63	#define VPE_LOCAL_SECTION_SIZE 0x4000
	64	#define VPE_OTHER_SECTION_OFS 0xc000
	65	#define VPE_OTHER_SECTION_SIZE 0x4000
	66	#define USM_VISIBLE_SECTION_OFS 0x10000
	67	#define USM_VISIBLE_SECTION_SIZE 0x10000
	68
	69	/* Register Map for Shared Section */
39b8d525	70
70342287	71	#define GIC_SH_CONFIG_OFS 0x0000
39b8d525 RB	72
	73	/* Shared Global Counter */
	74	#define GIC_SH_COUNTER_31_00_OFS 0x0010
	75	#define GIC_SH_COUNTER_63_32_OFS 0x0014
7098f748	76	#define GIC_SH_REVISIONID_OFS 0x0020
39b8d525 RB	77
	78	/* Interrupt Polarity */
	79	#define GIC_SH_POL_31_0_OFS 0x0100
	80	#define GIC_SH_POL_63_32_OFS 0x0104
	81	#define GIC_SH_POL_95_64_OFS 0x0108
	82	#define GIC_SH_POL_127_96_OFS 0x010c
	83	#define GIC_SH_POL_159_128_OFS 0x0110
	84	#define GIC_SH_POL_191_160_OFS 0x0114
	85	#define GIC_SH_POL_223_192_OFS 0x0118
	86	#define GIC_SH_POL_255_224_OFS 0x011c
	87
	88	/* Edge/Level Triggering */
	89	#define GIC_SH_TRIG_31_0_OFS 0x0180
	90	#define GIC_SH_TRIG_63_32_OFS 0x0184
	91	#define GIC_SH_TRIG_95_64_OFS 0x0188
	92	#define GIC_SH_TRIG_127_96_OFS 0x018c
	93	#define GIC_SH_TRIG_159_128_OFS 0x0190
	94	#define GIC_SH_TRIG_191_160_OFS 0x0194
	95	#define GIC_SH_TRIG_223_192_OFS 0x0198
	96	#define GIC_SH_TRIG_255_224_OFS 0x019c
	97
	98	/* Dual Edge Triggering */
	99	#define GIC_SH_DUAL_31_0_OFS 0x0200
	100	#define GIC_SH_DUAL_63_32_OFS 0x0204
	101	#define GIC_SH_DUAL_95_64_OFS 0x0208
	102	#define GIC_SH_DUAL_127_96_OFS 0x020c
	103	#define GIC_SH_DUAL_159_128_OFS 0x0210
	104	#define GIC_SH_DUAL_191_160_OFS 0x0214
	105	#define GIC_SH_DUAL_223_192_OFS 0x0218
	106	#define GIC_SH_DUAL_255_224_OFS 0x021c
	107
	108	/* Set/Clear corresponding bit in Edge Detect Register */
	109	#define GIC_SH_WEDGE_OFS 0x0280
	110
	111	/* Reset Mask - Disables Interrupt */
	112	#define GIC_SH_RMASK_31_0_OFS 0x0300
	113	#define GIC_SH_RMASK_63_32_OFS 0x0304
	114	#define GIC_SH_RMASK_95_64_OFS 0x0308
	115	#define GIC_SH_RMASK_127_96_OFS 0x030c
	116	#define GIC_SH_RMASK_159_128_OFS 0x0310
	117	#define GIC_SH_RMASK_191_160_OFS 0x0314
	118	#define GIC_SH_RMASK_223_192_OFS 0x0318
	119	#define GIC_SH_RMASK_255_224_OFS 0x031c
	120
	121	/* Set Mask (WO) - Enables Interrupt */
	122	#define GIC_SH_SMASK_31_0_OFS 0x0380
	123	#define GIC_SH_SMASK_63_32_OFS 0x0384
	124	#define GIC_SH_SMASK_95_64_OFS 0x0388
	125	#define GIC_SH_SMASK_127_96_OFS 0x038c
	126	#define GIC_SH_SMASK_159_128_OFS 0x0390
	127	#define GIC_SH_SMASK_191_160_OFS 0x0394
	128	#define GIC_SH_SMASK_223_192_OFS 0x0398
	129	#define GIC_SH_SMASK_255_224_OFS 0x039c
	130
	131	/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
	132	#define GIC_SH_MASK_31_0_OFS 0x0400
	133	#define GIC_SH_MASK_63_32_OFS 0x0404
	134	#define GIC_SH_MASK_95_64_OFS 0x0408
	135	#define GIC_SH_MASK_127_96_OFS 0x040c
	136	#define GIC_SH_MASK_159_128_OFS 0x0410
	137	#define GIC_SH_MASK_191_160_OFS 0x0414
	138	#define GIC_SH_MASK_223_192_OFS 0x0418
	139	#define GIC_SH_MASK_255_224_OFS 0x041c
	140
141	/* Pending Global Interrupts (RO) */
142	#define GIC_SH_PEND_31_0_OFS 0x0480
143	#define GIC_SH_PEND_63_32_OFS 0x0484
144	#define GIC_SH_PEND_95_64_OFS 0x0488
145	#define GIC_SH_PEND_127_96_OFS 0x048c
146	#define GIC_SH_PEND_159_128_OFS 0x0490
147	#define GIC_SH_PEND_191_160_OFS 0x0494
148	#define GIC_SH_PEND_223_192_OFS 0x0498
149	#define GIC_SH_PEND_255_224_OFS 0x049c
150
70342287	151	#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
39b8d525 RB	152
	153	/* Maps Interrupt X to a Pin */
	154	#define GIC_SH_MAP_TO_PIN(intr) \
	155	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
	156
70342287	157	#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
39b8d525 RB	158
	159	/* Maps Interrupt X to a VPE */
	160	#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	161	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
	162	#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
	163
7098f748 CD	164	/* Convert an interrupt number to a byte offset/bit for multi-word registers */
	165	#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
	166	#define GIC_INTR_BIT(intr) ((intr) % 32)
	167
39b8d525 RB	168	/* Polarity : Reset Value is always 0 */
	169	#define GIC_SH_SET_POLARITY_OFS 0x0100
	170	#define GIC_SET_POLARITY(intr, pol) \
7098f748	171	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
c55b2851 JD	172	GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
c55b2851 JD	173	(pol) << GIC_INTR_BIT(intr))
39b8d525 RB	174
	175	/* Triggering : Reset Value is always 0 */
	176	#define GIC_SH_SET_TRIGGER_OFS 0x0180
	177	#define GIC_SET_TRIGGER(intr, trig) \
7098f748	178	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
c55b2851 JD	179	GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
c55b2851 JD	180	(trig) << GIC_INTR_BIT(intr))
39b8d525 RB	181
	182	/* Mask manipulation */
	183	#define GIC_SH_SMASK_OFS 0x0380
7098f748 CD	184	#define GIC_SET_INTR_MASK(intr) \
	185	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
	186	GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
39b8d525	187	#define GIC_SH_RMASK_OFS 0x0300
7098f748 CD	188	#define GIC_CLR_INTR_MASK(intr) \
	189	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
	190	GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
39b8d525 RB	191
	192	/* Register Map for Local Section */
	193	#define GIC_VPE_CTL_OFS 0x0000
	194	#define GIC_VPE_PEND_OFS 0x0004
	195	#define GIC_VPE_MASK_OFS 0x0008
	196	#define GIC_VPE_RMASK_OFS 0x000c
	197	#define GIC_VPE_SMASK_OFS 0x0010
	198	#define GIC_VPE_WD_MAP_OFS 0x0040
	199	#define GIC_VPE_COMPARE_MAP_OFS 0x0044
	200	#define GIC_VPE_TIMER_MAP_OFS 0x0048
	201	#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
	202	#define GIC_VPE_SWINT0_MAP_OFS 0x0054
	203	#define GIC_VPE_SWINT1_MAP_OFS 0x0058
	204	#define GIC_VPE_OTHER_ADDR_OFS 0x0080
	205	#define GIC_VPE_WD_CONFIG0_OFS 0x0090
	206	#define GIC_VPE_WD_COUNT0_OFS 0x0094
	207	#define GIC_VPE_WD_INITIAL0_OFS 0x0098
	208	#define GIC_VPE_COMPARE_LO_OFS 0x00a0
0ab2b7d0	209	#define GIC_VPE_COMPARE_HI_OFS 0x00a4
39b8d525 RB	210
	211	#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
	212	#define GIC_VPE_EIC_SS(intr) \
f0b77f2c	213	(GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
39b8d525 RB	214
	215	#define GIC_VPE_EIC_VEC_BASE 0x0800
	216	#define GIC_VPE_EIC_VEC(intr) \
	217	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
	218
	219	#define GIC_VPE_TENABLE_NMI_OFS 0x1000
	220	#define GIC_VPE_TENABLE_YQ_OFS 0x1004
	221	#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
	222	#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
	223
	224	/* User Mode Visible Section Register Map */
	225	#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
	226	#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
	227
39b8d525 RB	228	/* Masks */
	229	#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
	230	#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
	231
	232	#define GIC_SH_CONFIG_COUNTBITS_SHF 24
	233	#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
	234
	235	#define GIC_SH_CONFIG_NUMINTRS_SHF 16
	236	#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
	237
	238	#define GIC_SH_CONFIG_NUMVPES_SHF 0
	239	#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
	240
	241	#define GIC_SH_WEDGE_SET(intr) (intr \| (0x1 << 31))
	242	#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
	243
	244	#define GIC_MAP_TO_PIN_SHF 31
	245	#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
	246	#define GIC_MAP_TO_NMI_SHF 30
	247	#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
	248	#define GIC_MAP_TO_YQ_SHF 29
	249	#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
	250	#define GIC_MAP_SHF 0
	251	#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
	252
	253	/* GIC_VPE_CTL Masks */
	254	#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
	255	#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
	256	#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
	257	#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
	258	#define GIC_VPE_CTL_EIC_MODE_SHF 0
	259	#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
	260
	261	/* GIC_VPE_PEND Masks */
	262	#define GIC_VPE_PEND_WD_SHF 0
	263	#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
	264	#define GIC_VPE_PEND_CMP_SHF 1
	265	#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
	266	#define GIC_VPE_PEND_TIMER_SHF 2
	267	#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
	268	#define GIC_VPE_PEND_PERFCOUNT_SHF 3
	269	#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
	270	#define GIC_VPE_PEND_SWINT0_SHF 4
	271	#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
	272	#define GIC_VPE_PEND_SWINT1_SHF 5
	273	#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
	274
	275	/* GIC_VPE_RMASK Masks */
	276	#define GIC_VPE_RMASK_WD_SHF 0
	277	#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
	278	#define GIC_VPE_RMASK_CMP_SHF 1
	279	#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
	280	#define GIC_VPE_RMASK_TIMER_SHF 2
	281	#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
	282	#define GIC_VPE_RMASK_PERFCNT_SHF 3
	283	#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
	284	#define GIC_VPE_RMASK_SWINT0_SHF 4
	285	#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
	286	#define GIC_VPE_RMASK_SWINT1_SHF 5
	287	#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
	288
	289	/* GIC_VPE_SMASK Masks */
	290	#define GIC_VPE_SMASK_WD_SHF 0
	291	#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
292	#define GIC_VPE_SMASK_CMP_SHF 1
293	#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
294	#define GIC_VPE_SMASK_TIMER_SHF 2
295	#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
296	#define GIC_VPE_SMASK_PERFCNT_SHF 3
297	#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
298	#define GIC_VPE_SMASK_SWINT0_SHF 4
299	#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
300	#define GIC_VPE_SMASK_SWINT1_SHF 5
301	#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
302
303	/*
304	* Set the Mapping of Interrupt X to a VPE.
305	*/
306	#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
307	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
308	GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
309
39b8d525 RB	310	/*
	311	* Interrupt Meta-data specification. The ipiflag helps
	312	* in building ipi_map.
	313	*/
	314	struct gic_intr_map {
39b8d525	315	unsigned int cpunum; /* Directed to this CPU */
863cb9ba	316	#define GIC_UNUSED 0xdead /* Dummy data */
39b8d525 RB	317	unsigned int pin; /* Directed to this Pin */
	318	unsigned int polarity; /* Polarity : +/- */
	319	unsigned int trigtype; /* Trigger : Edge/Levl */
7098f748	320	unsigned int flags; /* Misc flags */
b0a88ae5	321	#define GIC_FLAG_TRANSPARENT 0x01
39b8d525 RB	322	};
39b8d525 RB	323
f0b77f2c SH	324	/*
	325	* This is only used in EIC mode. This helps to figure out which
	326	* shared interrupts we need to process when we get a vector interrupt.
	327	*/
	328	#define GIC_MAX_SHARED_INTR 0x5
	329	struct gic_shared_intr_map {
	330	unsigned int num_shared_intr;
	331	unsigned int intr_list[GIC_MAX_SHARED_INTR];
	332	unsigned int local_intr_mask;
	333	};
	334
0b271f56 SH	335	/* GIC nomenclature for Core Interrupt Pins. */
0b271f56 SH	336	#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
70342287 RB	337	#define GIC_CPU_INT1 1 /* . */
	338	#define GIC_CPU_INT2 2 /* . */
	339	#define GIC_CPU_INT3 3 /* . */
	340	#define GIC_CPU_INT4 4 /* . */
42a11179	341	#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
0b271f56 SH	342
	343	/* Local GIC interrupts. */
	344	#define GIC_INT_TMR (GIC_CPU_INT5)
	345	#define GIC_INT_PERFCTR (GIC_CPU_INT5)
	346
	347	/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
	348	#define GIC_CPU_TO_VEC_OFFSET (2)
	349
	350	/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
	351	#define GIC_PIN_TO_VEC_OFFSET (1)
	352
dfa762e1 SH	353	#include <linux/clocksource.h>
	354	#include <linux/irq.h>
	355
ff86714f	356	extern unsigned int gic_present;
28ea2151	357	extern unsigned int gic_frequency;
0b271f56 SH	358	extern unsigned long _gic_base;
	359	extern unsigned int gic_irq_base;
	360	extern unsigned int gic_irq_flags[];
	361	extern struct gic_shared_intr_map gic_shared_intr_map[];
	362
39b8d525 RB	363	extern void gic_init(unsigned long gic_base_addr,
	364	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
	365	unsigned int intrmap_size, unsigned int irqbase);
0b271f56	366	extern void gic_clocksource_init(unsigned int);
0ab2b7d0	367	extern unsigned int gic_compare_int (void);
dfa762e1	368	extern cycle_t gic_read_count(void);
0ab2b7d0 RG	369	extern cycle_t gic_read_compare(void);
0ab2b7d0 RG	370	extern void gic_write_compare(cycle_t cnt);
414408d0	371	extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
39b8d525	372	extern void gic_send_ipi(unsigned int intr);
0365070f TA	373	extern unsigned int plat_ipi_call_int_xlate(unsigned int);
0365070f TA	374	extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
f0b77f2c SH	375	extern void gic_bind_eic_interrupt(int irq, int set);
f0b77f2c SH	376	extern unsigned int gic_get_timer_pending(void);
31521a7a	377	extern void gic_get_int_mask(unsigned long dst, const unsigned long src);
2675fa7c	378	extern unsigned int gic_get_int(void);
0b271f56 SH	379	extern void gic_enable_interrupt(int irq_vec);
	380	extern void gic_disable_interrupt(int irq_vec);
	381	extern void gic_irq_ack(struct irq_data *d);
	382	extern void gic_finish_irq(struct irq_data *d);
	383	extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
39b8d525	384	#endif /* _ASM_GICREGS_H */