projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * | |
| 3 | * BRIEF MODULE DESCRIPTION | |
| 4 | * Include file for Alchemy Semiconductor's Au1k CPU. | |
| 5 | * | |
| 01675095 SS |
6 | * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. |
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
| 1da177e4 LT |
8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it | |
| 10 | * under the terms of the GNU General Public License as published by the | |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 12 | * option) any later version. | |
| 13 | * | |
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 24 | * | |
| 25 | * You should have received a copy of the GNU General Public License along | |
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 28 | */ | |
| 29 | ||
| 30 | /* | |
| 31 | * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp | |
| 32 | */ | |
| 33 | ||
| 34 | #ifndef _AU1000_H_ | |
| 35 | #define _AU1000_H_ | |
| 36 | ||
| 2ef1bb99 ML |
37 | /* SOC Interrupt numbers */ |
| 38 | /* Au1000-style (IC0/1): 2 controllers with 32 sources each */ | |
| 39 | #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | |
| 40 | #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) | |
| 41 | #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) | |
| 42 | #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) | |
| 43 | #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST | |
| 1da177e4 | 44 | |
| 2ef1bb99 ML |
45 | /* Au1300-style (GPIC): 1 controller with up to 128 sources */ |
| 46 | #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) | |
| 47 | #define ALCHEMY_GPIC_INT_NUM 128 | |
| 48 | #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) | |
| 1da177e4 | 49 | |
| 9d360ab4 | 50 | |
| 2ef1bb99 ML |
51 | /* Au1300 peripheral interrupt numbers */ |
| 52 | #define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) | |
| 53 | #define AU1300_UART1_INT (AU1300_FIRST_INT + 17) | |
| 54 | #define AU1300_UART2_INT (AU1300_FIRST_INT + 25) | |
| 55 | #define AU1300_UART3_INT (AU1300_FIRST_INT + 27) | |
| 56 | #define AU1300_SD1_INT (AU1300_FIRST_INT + 32) | |
| 57 | #define AU1300_SD2_INT (AU1300_FIRST_INT + 38) | |
| 58 | #define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) | |
| 59 | #define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) | |
| 60 | #define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) | |
| 61 | #define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) | |
| 62 | #define AU1300_NAND_INT (AU1300_FIRST_INT + 62) | |
| 63 | #define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) | |
| 64 | #define AU1300_MMU_INT (AU1300_FIRST_INT + 76) | |
| 65 | #define AU1300_MPU_INT (AU1300_FIRST_INT + 77) | |
| 66 | #define AU1300_GPU_INT (AU1300_FIRST_INT + 78) | |
| 67 | #define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) | |
| 68 | #define AU1300_TOY_INT (AU1300_FIRST_INT + 80) | |
| 69 | #define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) | |
| 70 | #define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) | |
| 71 | #define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) | |
| 72 | #define AU1300_RTC_INT (AU1300_FIRST_INT + 84) | |
| 73 | #define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) | |
| 74 | #define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) | |
| 75 | #define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) | |
| 76 | #define AU1300_UART0_INT (AU1300_FIRST_INT + 88) | |
| 77 | #define AU1300_SD0_INT (AU1300_FIRST_INT + 89) | |
| 78 | #define AU1300_USB_INT (AU1300_FIRST_INT + 90) | |
| 79 | #define AU1300_LCD_INT (AU1300_FIRST_INT + 91) | |
| 80 | #define AU1300_BSA_INT (AU1300_FIRST_INT + 92) | |
| 81 | #define AU1300_MPE_INT (AU1300_FIRST_INT + 93) | |
| 82 | #define AU1300_ITE_INT (AU1300_FIRST_INT + 94) | |
| 83 | #define AU1300_AES_INT (AU1300_FIRST_INT + 95) | |
| 84 | #define AU1300_CIM_INT (AU1300_FIRST_INT + 96) | |
| 1da177e4 | 85 | |
| 2ef1bb99 | 86 | /**********************************************************************/ |
| 8ff374b9 | 87 | |
| 2ef1bb99 ML |
88 | /* |
| 89 | * Physical base addresses for integrated peripherals | |
| 90 | * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 | |
| 91 | */ | |
| 1da177e4 | 92 | |
| 2ef1bb99 ML |
93 | #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ |
| 94 | #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ | |
| 95 | #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ | |
| 96 | #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ | |
| 97 | #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ | |
| 98 | #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ | |
| 99 | #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ | |
| 100 | #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ | |
| 101 | #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ | |
| 102 | #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ | |
| 103 | #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ | |
| 104 | #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ | |
| 105 | #define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ | |
| 106 | #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ | |
| 107 | #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ | |
| 108 | #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ | |
| 109 | #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ | |
| 110 | #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ | |
| 111 | #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ | |
| 112 | #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ | |
| 113 | #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ | |
| 114 | #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ | |
| 115 | #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ | |
| 116 | #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ | |
| 117 | #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ | |
| 118 | #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ | |
| 119 | #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ | |
| 120 | #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ | |
| 121 | #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ | |
| 122 | #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ | |
| 123 | #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ | |
| 124 | #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ | |
| 125 | #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ | |
| 126 | #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ | |
| 127 | #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ | |
| 128 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | |
| 129 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | |
| 130 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | |
| 131 | #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ | |
| 132 | #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ | |
| 133 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | |
| 134 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | |
| 135 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ | |
| 136 | #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ | |
| 137 | #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ | |
| 138 | #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ | |
| 139 | #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ | |
| 140 | #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ | |
| 141 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | |
| 142 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ | |
| 143 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ | |
| 144 | #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ | |
| 145 | #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ | |
| 146 | #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ | |
| 147 | #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ | |
| 148 | #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ | |
| 149 | #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ | |
| 150 | #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ | |
| 151 | #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ | |
| 152 | #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ | |
| 153 | #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ | |
| 154 | #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ | |
| 155 | #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ | |
| 156 | #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ | |
| 157 | #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ | |
| 158 | #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ | |
| 159 | #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ | |
| 160 | #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ | |
| 161 | #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ | |
| 162 | #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ | |
| 163 | #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ | |
| 164 | #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ | |
| 165 | #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ | |
| 166 | #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ | |
| 167 | #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ | |
| 168 | #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ | |
| 169 | #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ | |
| 170 | #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ | |
| 171 | #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ | |
| 172 | #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ | |
| 173 | #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ | |
| 1da177e4 | 174 | |
| 2ef1bb99 | 175 | /**********************************************************************/ |
| 1da177e4 | 176 | |
| 1da177e4 | 177 | |
| 2ef1bb99 ML |
178 | /* |
| 179 | * Au1300 GPIO+INT controller (GPIC) register offsets and bits | |
| 180 | * Registers are 128bits (0x10 bytes), divided into 4 "banks". | |
| 181 | */ | |
| 182 | #define AU1300_GPIC_PINVAL 0x0000 | |
| 183 | #define AU1300_GPIC_PINVALCLR 0x0010 | |
| 184 | #define AU1300_GPIC_IPEND 0x0020 | |
| 185 | #define AU1300_GPIC_PRIENC 0x0030 | |
| 186 | #define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ | |
| 187 | #define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ | |
| 188 | #define AU1300_GPIC_DMASEL 0x0060 | |
| 189 | #define AU1300_GPIC_DEVSEL 0x0080 | |
| 190 | #define AU1300_GPIC_DEVCLR 0x0090 | |
| 191 | #define AU1300_GPIC_RSTVAL 0x00a0 | |
| 192 | /* pin configuration space. one 32bit register for up to 128 IRQs */ | |
| 193 | #define AU1300_GPIC_PINCFG 0x1000 | |
| 1da177e4 | 194 | |
| 2ef1bb99 ML |
195 | #define GPIC_GPIO_TO_BIT(gpio) \ |
| 196 | (1 << ((gpio) & 0x1f)) | |
| 1da177e4 | 197 | |
| 2ef1bb99 ML |
198 | #define GPIC_GPIO_BANKOFF(gpio) \ |
| 199 | (((gpio) >> 5) * 4) | |
| 1da177e4 | 200 | |
| 2ef1bb99 ML |
201 | /* Pin Control bits: who owns the pin, what does it do */ |
| 202 | #define GPIC_CFG_PC_GPIN 0 | |
| 203 | #define GPIC_CFG_PC_DEV 1 | |
| 204 | #define GPIC_CFG_PC_GPOLOW 2 | |
| 205 | #define GPIC_CFG_PC_GPOHIGH 3 | |
| 206 | #define GPIC_CFG_PC_MASK 3 | |
| 1da177e4 | 207 | |
| 2ef1bb99 ML |
208 | /* assign pin to MIPS IRQ line */ |
| 209 | #define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) | |
| 210 | #define GPIC_CFG_IL_MASK (3 << 2) | |
| 1da177e4 | 211 | |
| 2ef1bb99 ML |
212 | /* pin interrupt type setup */ |
| 213 | #define GPIC_CFG_IC_OFF (0 << 4) | |
| 214 | #define GPIC_CFG_IC_LEVEL_LOW (1 << 4) | |
| 215 | #define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) | |
| 216 | #define GPIC_CFG_IC_EDGE_FALL (5 << 4) | |
| 217 | #define GPIC_CFG_IC_EDGE_RISE (6 << 4) | |
| 218 | #define GPIC_CFG_IC_EDGE_BOTH (7 << 4) | |
| 219 | #define GPIC_CFG_IC_MASK (7 << 4) | |
| 074cf656 | 220 | |
| 2ef1bb99 ML |
221 | /* allow interrupt to wake cpu from 'wait' */ |
| 222 | #define GPIC_CFG_IDLEWAKE (1 << 7) | |
| 1da177e4 | 223 | |
| 2ef1bb99 | 224 | /***********************************************************************/ |
| 93e9cd84 | 225 | |
| 2ef1bb99 ML |
226 | /* Au1000 SDRAM memory controller register offsets */ |
| 227 | #define AU1000_MEM_SDMODE0 0x0000 | |
| 228 | #define AU1000_MEM_SDMODE1 0x0004 | |
| 229 | #define AU1000_MEM_SDMODE2 0x0008 | |
| 230 | #define AU1000_MEM_SDADDR0 0x000C | |
| 231 | #define AU1000_MEM_SDADDR1 0x0010 | |
| 232 | #define AU1000_MEM_SDADDR2 0x0014 | |
| 233 | #define AU1000_MEM_SDREFCFG 0x0018 | |
| 234 | #define AU1000_MEM_SDPRECMD 0x001C | |
| 235 | #define AU1000_MEM_SDAUTOREF 0x0020 | |
| 236 | #define AU1000_MEM_SDWRMD0 0x0024 | |
| 237 | #define AU1000_MEM_SDWRMD1 0x0028 | |
| 238 | #define AU1000_MEM_SDWRMD2 0x002C | |
| 239 | #define AU1000_MEM_SDSLEEP 0x0030 | |
| 240 | #define AU1000_MEM_SDSMCKE 0x0034 | |
| 93e9cd84 | 241 | |
| 2ef1bb99 ML |
242 | /* MEM_SDMODE register content definitions */ |
| 243 | #define MEM_SDMODE_F (1 << 22) | |
| 244 | #define MEM_SDMODE_SR (1 << 21) | |
| 245 | #define MEM_SDMODE_BS (1 << 20) | |
| 246 | #define MEM_SDMODE_RS (3 << 18) | |
| 247 | #define MEM_SDMODE_CS (7 << 15) | |
| 248 | #define MEM_SDMODE_TRAS (15 << 11) | |
| 249 | #define MEM_SDMODE_TMRD (3 << 9) | |
| 250 | #define MEM_SDMODE_TWR (3 << 7) | |
| 251 | #define MEM_SDMODE_TRP (3 << 5) | |
| 252 | #define MEM_SDMODE_TRCD (3 << 3) | |
| 253 | #define MEM_SDMODE_TCL (7 << 0) | |
| 93e9cd84 | 254 | |
| 2ef1bb99 ML |
255 | #define MEM_SDMODE_BS_2Bank (0 << 20) |
| 256 | #define MEM_SDMODE_BS_4Bank (1 << 20) | |
| 257 | #define MEM_SDMODE_RS_11Row (0 << 18) | |
| 258 | #define MEM_SDMODE_RS_12Row (1 << 18) | |
| 259 | #define MEM_SDMODE_RS_13Row (2 << 18) | |
| 260 | #define MEM_SDMODE_RS_N(N) ((N) << 18) | |
| 261 | #define MEM_SDMODE_CS_7Col (0 << 15) | |
| 262 | #define MEM_SDMODE_CS_8Col (1 << 15) | |
| 263 | #define MEM_SDMODE_CS_9Col (2 << 15) | |
| 264 | #define MEM_SDMODE_CS_10Col (3 << 15) | |
| 265 | #define MEM_SDMODE_CS_11Col (4 << 15) | |
| 266 | #define MEM_SDMODE_CS_N(N) ((N) << 15) | |
| 267 | #define MEM_SDMODE_TRAS_N(N) ((N) << 11) | |
| 268 | #define MEM_SDMODE_TMRD_N(N) ((N) << 9) | |
| 269 | #define MEM_SDMODE_TWR_N(N) ((N) << 7) | |
| 270 | #define MEM_SDMODE_TRP_N(N) ((N) << 5) | |
| 271 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) | |
| 272 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) | |
| 80130204 | 273 | |
| 2ef1bb99 ML |
274 | /* MEM_SDADDR register contents definitions */ |
| 275 | #define MEM_SDADDR_E (1 << 20) | |
| 276 | #define MEM_SDADDR_CSBA (0x03FF << 10) | |
| 277 | #define MEM_SDADDR_CSMASK (0x03FF << 0) | |
| 278 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) | |
| 279 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) | |
| 80130204 | 280 | |
| 2ef1bb99 ML |
281 | /* MEM_SDREFCFG register content definitions */ |
| 282 | #define MEM_SDREFCFG_TRC (15 << 28) | |
| 283 | #define MEM_SDREFCFG_TRPM (3 << 26) | |
| 284 | #define MEM_SDREFCFG_E (1 << 25) | |
| 285 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) | |
| 286 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) | |
| 287 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) | |
| 288 | #define MEM_SDREFCFG_REF_N(N) (N) | |
| 80130204 | 289 | |
| 2ef1bb99 ML |
290 | /* Au1550 SDRAM Register Offsets */ |
| 291 | #define AU1550_MEM_SDMODE0 0x0800 | |
| 292 | #define AU1550_MEM_SDMODE1 0x0808 | |
| 293 | #define AU1550_MEM_SDMODE2 0x0810 | |
| 294 | #define AU1550_MEM_SDADDR0 0x0820 | |
| 295 | #define AU1550_MEM_SDADDR1 0x0828 | |
| 296 | #define AU1550_MEM_SDADDR2 0x0830 | |
| 297 | #define AU1550_MEM_SDCONFIGA 0x0840 | |
| 298 | #define AU1550_MEM_SDCONFIGB 0x0848 | |
| 299 | #define AU1550_MEM_SDSTAT 0x0850 | |
| 300 | #define AU1550_MEM_SDERRADDR 0x0858 | |
| 301 | #define AU1550_MEM_SDSTRIDE0 0x0860 | |
| 302 | #define AU1550_MEM_SDSTRIDE1 0x0868 | |
| 303 | #define AU1550_MEM_SDSTRIDE2 0x0870 | |
| 304 | #define AU1550_MEM_SDWRMD0 0x0880 | |
| 305 | #define AU1550_MEM_SDWRMD1 0x0888 | |
| 306 | #define AU1550_MEM_SDWRMD2 0x0890 | |
| 307 | #define AU1550_MEM_SDPRECMD 0x08C0 | |
| 308 | #define AU1550_MEM_SDAUTOREF 0x08C8 | |
| 309 | #define AU1550_MEM_SDSREF 0x08D0 | |
| 310 | #define AU1550_MEM_SDSLEEP MEM_SDSREF | |
| 80130204 | 311 | |
| 2ef1bb99 ML |
312 | /* Static Bus Controller */ |
| 313 | #define MEM_STCFG0 0xB4001000 | |
| 314 | #define MEM_STTIME0 0xB4001004 | |
| 315 | #define MEM_STADDR0 0xB4001008 | |
| 8402a158 | 316 | |
| 2ef1bb99 ML |
317 | #define MEM_STCFG1 0xB4001010 |
| 318 | #define MEM_STTIME1 0xB4001014 | |
| 319 | #define MEM_STADDR1 0xB4001018 | |
| 8402a158 | 320 | |
| 2ef1bb99 ML |
321 | #define MEM_STCFG2 0xB4001020 |
| 322 | #define MEM_STTIME2 0xB4001024 | |
| 323 | #define MEM_STADDR2 0xB4001028 | |
| 8402a158 | 324 | |
| 2ef1bb99 ML |
325 | #define MEM_STCFG3 0xB4001030 |
| 326 | #define MEM_STTIME3 0xB4001034 | |
| 327 | #define MEM_STADDR3 0xB4001038 | |
| 40d8bc28 | 328 | |
| 2ef1bb99 ML |
329 | #define MEM_STNDCTL 0xB4001100 |
| 330 | #define MEM_STSTAT 0xB4001104 | |
| 1da177e4 | 331 | |
| 2ef1bb99 ML |
332 | #define MEM_STNAND_CMD 0x0 |
| 333 | #define MEM_STNAND_ADDR 0x4 | |
| 334 | #define MEM_STNAND_DATA 0x20 | |
| 564365b0 | 335 | |
| ce6bc922 | 336 | |
| 2ef1bb99 | 337 | /* Programmable Counters 0 and 1 */ |
| 1d09de7d | 338 | #define AU1000_SYS_CNTRCTRL 0x14 |
| 2ef1bb99 ML |
339 | # define SYS_CNTRL_E1S (1 << 23) |
| 340 | # define SYS_CNTRL_T1S (1 << 20) | |
| 341 | # define SYS_CNTRL_M21 (1 << 19) | |
| 342 | # define SYS_CNTRL_M11 (1 << 18) | |
| 343 | # define SYS_CNTRL_M01 (1 << 17) | |
| 344 | # define SYS_CNTRL_C1S (1 << 16) | |
| 345 | # define SYS_CNTRL_BP (1 << 14) | |
| 346 | # define SYS_CNTRL_EN1 (1 << 13) | |
| 347 | # define SYS_CNTRL_BT1 (1 << 12) | |
| 348 | # define SYS_CNTRL_EN0 (1 << 11) | |
| 349 | # define SYS_CNTRL_BT0 (1 << 10) | |
| 350 | # define SYS_CNTRL_E0 (1 << 8) | |
| 351 | # define SYS_CNTRL_E0S (1 << 7) | |
| 352 | # define SYS_CNTRL_32S (1 << 5) | |
| 353 | # define SYS_CNTRL_T0S (1 << 4) | |
| 354 | # define SYS_CNTRL_M20 (1 << 3) | |
| 355 | # define SYS_CNTRL_M10 (1 << 2) | |
| 356 | # define SYS_CNTRL_M00 (1 << 1) | |
| 357 | # define SYS_CNTRL_C0S (1 << 0) | |
| 78814465 | 358 | |
| 2ef1bb99 | 359 | /* Programmable Counter 0 Registers */ |
| 1d09de7d ML |
360 | #define AU1000_SYS_TOYTRIM 0x00 |
| 361 | #define AU1000_SYS_TOYWRITE 0x04 | |
| 362 | #define AU1000_SYS_TOYMATCH0 0x08 | |
| 363 | #define AU1000_SYS_TOYMATCH1 0x0c | |
| 364 | #define AU1000_SYS_TOYMATCH2 0x10 | |
| 365 | #define AU1000_SYS_TOYREAD 0x40 | |
| 809f36c6 | 366 | |
| 2ef1bb99 | 367 | /* Programmable Counter 1 Registers */ |
| 1d09de7d ML |
368 | #define AU1000_SYS_RTCTRIM 0x44 |
| 369 | #define AU1000_SYS_RTCWRITE 0x48 | |
| 370 | #define AU1000_SYS_RTCMATCH0 0x4c | |
| 371 | #define AU1000_SYS_RTCMATCH1 0x50 | |
| 372 | #define AU1000_SYS_RTCMATCH2 0x54 | |
| 373 | #define AU1000_SYS_RTCREAD 0x58 | |
| 809f36c6 | 374 | |
| 809f36c6 | 375 | |
| 2ef1bb99 | 376 | /* GPIO */ |
| 1d09de7d | 377 | #define AU1000_SYS_PINFUNC 0x2C |
| 2ef1bb99 ML |
378 | # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ |
| 379 | # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ | |
| 380 | # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ | |
| 381 | # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ | |
| 382 | # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ | |
| 383 | # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ | |
| 384 | # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ | |
| 385 | # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ | |
| 386 | # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ | |
| 387 | # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ | |
| 388 | # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ | |
| 389 | # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ | |
| 390 | # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ | |
| 391 | # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ | |
| 392 | # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ | |
| 393 | # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ | |
| 78814465 | 394 | |
| 2ef1bb99 ML |
395 | /* Au1100 only */ |
| 396 | # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ | |
| 397 | # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ | |
| 398 | # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ | |
| 399 | # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ | |
| 78814465 | 400 | |
| 2ef1bb99 ML |
401 | /* Au1550 only. Redefines lots of pins */ |
| 402 | # define SYS_PF_PSC2_MASK (7 << 17) | |
| 403 | # define SYS_PF_PSC2_AC97 0 | |
| 404 | # define SYS_PF_PSC2_SPI 0 | |
| 405 | # define SYS_PF_PSC2_I2S (1 << 17) | |
| 406 | # define SYS_PF_PSC2_SMBUS (3 << 17) | |
| 407 | # define SYS_PF_PSC2_GPIO (7 << 17) | |
| 408 | # define SYS_PF_PSC3_MASK (7 << 20) | |
| 409 | # define SYS_PF_PSC3_AC97 0 | |
| 410 | # define SYS_PF_PSC3_SPI 0 | |
| 411 | # define SYS_PF_PSC3_I2S (1 << 20) | |
| 412 | # define SYS_PF_PSC3_SMBUS (3 << 20) | |
| 413 | # define SYS_PF_PSC3_GPIO (7 << 20) | |
| 414 | # define SYS_PF_PSC1_S1 (1 << 1) | |
| 415 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | |
| 809f36c6 | 416 | |
| 2ef1bb99 ML |
417 | /* Au1200 only */ |
| 418 | #define SYS_PINFUNC_DMA (1 << 31) | |
| 419 | #define SYS_PINFUNC_S0A (1 << 30) | |
| 420 | #define SYS_PINFUNC_S1A (1 << 29) | |
| 421 | #define SYS_PINFUNC_LP0 (1 << 28) | |
| 422 | #define SYS_PINFUNC_LP1 (1 << 27) | |
| 423 | #define SYS_PINFUNC_LD16 (1 << 26) | |
| 424 | #define SYS_PINFUNC_LD8 (1 << 25) | |
| 425 | #define SYS_PINFUNC_LD1 (1 << 24) | |
| 426 | #define SYS_PINFUNC_LD0 (1 << 23) | |
| 427 | #define SYS_PINFUNC_P1A (3 << 21) | |
| 428 | #define SYS_PINFUNC_P1B (1 << 20) | |
| 429 | #define SYS_PINFUNC_FS3 (1 << 19) | |
| 430 | #define SYS_PINFUNC_P0A (3 << 17) | |
| 431 | #define SYS_PINFUNC_CS (1 << 16) | |
| 432 | #define SYS_PINFUNC_CIM (1 << 15) | |
| 433 | #define SYS_PINFUNC_P1C (1 << 14) | |
| 434 | #define SYS_PINFUNC_U1T (1 << 12) | |
| 435 | #define SYS_PINFUNC_U1R (1 << 11) | |
| 436 | #define SYS_PINFUNC_EX1 (1 << 10) | |
| 437 | #define SYS_PINFUNC_EX0 (1 << 9) | |
| 438 | #define SYS_PINFUNC_U0R (1 << 8) | |
| 439 | #define SYS_PINFUNC_MC (1 << 7) | |
| 440 | #define SYS_PINFUNC_S0B (1 << 6) | |
| 441 | #define SYS_PINFUNC_S0C (1 << 5) | |
| 442 | #define SYS_PINFUNC_P0B (1 << 4) | |
| 443 | #define SYS_PINFUNC_U0T (1 << 3) | |
| 444 | #define SYS_PINFUNC_S1B (1 << 2) | |
| 78814465 | 445 | |
| 2ef1bb99 | 446 | /* Power Management */ |
| 1d09de7d ML |
447 | #define AU1000_SYS_SCRATCH0 0x18 |
| 448 | #define AU1000_SYS_SCRATCH1 0x1c | |
| 449 | #define AU1000_SYS_WAKEMSK 0x34 | |
| 450 | #define AU1000_SYS_ENDIAN 0x38 | |
| 451 | #define AU1000_SYS_POWERCTRL 0x3c | |
| 452 | #define AU1000_SYS_WAKESRC 0x5c | |
| 453 | #define AU1000_SYS_SLPPWR 0x78 | |
| 454 | #define AU1000_SYS_SLEEP 0x7c | |
| 78814465 | 455 | |
| 2ef1bb99 ML |
456 | #define SYS_WAKEMSK_D2 (1 << 9) |
| 457 | #define SYS_WAKEMSK_M2 (1 << 8) | |
| 458 | #define SYS_WAKEMSK_GPIO(x) (1 << (x)) | |
| 78814465 | 459 | |
| 2ef1bb99 | 460 | /* Clock Controller */ |
| 1d09de7d | 461 | #define AU1000_SYS_FREQCTRL0 0x20 |
| 2ef1bb99 ML |
462 | # define SYS_FC_FRDIV2_BIT 22 |
| 463 | # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | |
| 464 | # define SYS_FC_FE2 (1 << 21) | |
| 465 | # define SYS_FC_FS2 (1 << 20) | |
| 466 | # define SYS_FC_FRDIV1_BIT 12 | |
| 467 | # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | |
| 468 | # define SYS_FC_FE1 (1 << 11) | |
| 469 | # define SYS_FC_FS1 (1 << 10) | |
| 470 | # define SYS_FC_FRDIV0_BIT 2 | |
| 471 | # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | |
| 472 | # define SYS_FC_FE0 (1 << 1) | |
| 473 | # define SYS_FC_FS0 (1 << 0) | |
| 1d09de7d | 474 | #define AU1000_SYS_FREQCTRL1 0x24 |
| 2ef1bb99 ML |
475 | # define SYS_FC_FRDIV5_BIT 22 |
| 476 | # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | |
| 477 | # define SYS_FC_FE5 (1 << 21) | |
| 478 | # define SYS_FC_FS5 (1 << 20) | |
| 479 | # define SYS_FC_FRDIV4_BIT 12 | |
| 480 | # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | |
| 481 | # define SYS_FC_FE4 (1 << 11) | |
| 482 | # define SYS_FC_FS4 (1 << 10) | |
| 483 | # define SYS_FC_FRDIV3_BIT 2 | |
| 484 | # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | |
| 485 | # define SYS_FC_FE3 (1 << 1) | |
| 486 | # define SYS_FC_FS3 (1 << 0) | |
| 1d09de7d | 487 | #define AU1000_SYS_CLKSRC 0x28 |
| 2ef1bb99 ML |
488 | # define SYS_CS_ME1_BIT 27 |
| 489 | # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) | |
| 490 | # define SYS_CS_DE1 (1 << 26) | |
| 491 | # define SYS_CS_CE1 (1 << 25) | |
| 492 | # define SYS_CS_ME0_BIT 22 | |
| 493 | # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) | |
| 494 | # define SYS_CS_DE0 (1 << 21) | |
| 495 | # define SYS_CS_CE0 (1 << 20) | |
| 496 | # define SYS_CS_MI2_BIT 17 | |
| 497 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) | |
| 498 | # define SYS_CS_DI2 (1 << 16) | |
| 499 | # define SYS_CS_CI2 (1 << 15) | |
| 78814465 | 500 | |
| 2ef1bb99 ML |
501 | # define SYS_CS_ML_BIT 7 |
| 502 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) | |
| 503 | # define SYS_CS_DL (1 << 6) | |
| 504 | # define SYS_CS_CL (1 << 5) | |
| 78814465 | 505 | |
| 2ef1bb99 ML |
506 | # define SYS_CS_MUH_BIT 12 |
| 507 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) | |
| 508 | # define SYS_CS_DUH (1 << 11) | |
| 509 | # define SYS_CS_CUH (1 << 10) | |
| 510 | # define SYS_CS_MUD_BIT 7 | |
| 511 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) | |
| 512 | # define SYS_CS_DUD (1 << 6) | |
| 513 | # define SYS_CS_CUD (1 << 5) | |
| 78814465 | 514 | |
| 2ef1bb99 ML |
515 | # define SYS_CS_MIR_BIT 2 |
| 516 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) | |
| 517 | # define SYS_CS_DIR (1 << 1) | |
| 518 | # define SYS_CS_CIR (1 << 0) | |
| 78814465 | 519 | |
| 2ef1bb99 ML |
520 | # define SYS_CS_MUX_AUX 0x1 |
| 521 | # define SYS_CS_MUX_FQ0 0x2 | |
| 522 | # define SYS_CS_MUX_FQ1 0x3 | |
| 523 | # define SYS_CS_MUX_FQ2 0x4 | |
| 524 | # define SYS_CS_MUX_FQ3 0x5 | |
| 525 | # define SYS_CS_MUX_FQ4 0x6 | |
| 526 | # define SYS_CS_MUX_FQ5 0x7 | |
| 1d09de7d ML |
527 | |
| 528 | #define AU1000_SYS_CPUPLL 0x60 | |
| 529 | #define AU1000_SYS_AUXPLL 0x64 | |
| 530 | ||
| 531 | ||
| 532 | /**********************************************************************/ | |
| 78814465 | 533 | |
| 809f36c6 | 534 | |
| 2ef1bb99 ML |
535 | /* The PCI chip selects are outside the 32bit space, and since we can't |
| 536 | * just program the 36bit addresses into BARs, we have to take a chunk | |
| 537 | * out of the 32bit space and reserve it for PCI. When these addresses | |
| 538 | * are ioremap()ed, they'll be fixed up to the real 36bit address before | |
| 539 | * being passed to the real ioremap function. | |
| e3ad1c23 | 540 | */ |
| 2ef1bb99 ML |
541 | #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) |
| 542 | #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) | |
| e3ad1c23 | 543 | |
| 2ef1bb99 ML |
544 | /* for PCI IO it's simpler because we get to do the ioremap ourselves and then |
| 545 | * adjust the device's resources. | |
| 809f36c6 | 546 | */ |
| 2ef1bb99 ML |
547 | #define ALCHEMY_PCI_IOWIN_START 0x00001000 |
| 548 | #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF | |
| 809f36c6 | 549 | |
| 2ef1bb99 | 550 | #ifdef CONFIG_PCI |
| 809f36c6 | 551 | |
| 2ef1bb99 ML |
552 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ |
| 553 | #define IOPORT_RESOURCE_END 0xffffffff | |
| 554 | #define IOMEM_RESOURCE_START 0x10000000 | |
| 555 | #define IOMEM_RESOURCE_END 0xfffffffffULL | |
| 809f36c6 | 556 | |
| 2ef1bb99 | 557 | #else |
| 809f36c6 | 558 | |
| 2ef1bb99 ML |
559 | /* Don't allow any legacy ports probing */ |
| 560 | #define IOPORT_RESOURCE_START 0x10000000 | |
| 561 | #define IOPORT_RESOURCE_END 0xffffffff | |
| 562 | #define IOMEM_RESOURCE_START 0x10000000 | |
| 563 | #define IOMEM_RESOURCE_END 0xfffffffffULL | |
| 809f36c6 | 564 | |
| 2ef1bb99 | 565 | #endif |
| 37663860 | 566 | |
| 2ef1bb99 ML |
567 | /* PCI controller block register offsets */ |
| 568 | #define PCI_REG_CMEM 0x0000 | |
| 569 | #define PCI_REG_CONFIG 0x0004 | |
| 570 | #define PCI_REG_B2BMASK_CCH 0x0008 | |
| 571 | #define PCI_REG_B2BBASE0_VID 0x000C | |
| 572 | #define PCI_REG_B2BBASE1_SID 0x0010 | |
| 573 | #define PCI_REG_MWMASK_DEV 0x0014 | |
| 574 | #define PCI_REG_MWBASE_REV_CCL 0x0018 | |
| 575 | #define PCI_REG_ERR_ADDR 0x001C | |
| 576 | #define PCI_REG_SPEC_INTACK 0x0020 | |
| 577 | #define PCI_REG_ID 0x0100 | |
| 578 | #define PCI_REG_STATCMD 0x0104 | |
| 579 | #define PCI_REG_CLASSREV 0x0108 | |
| 580 | #define PCI_REG_PARAM 0x010C | |
| 581 | #define PCI_REG_MBAR 0x0110 | |
| 582 | #define PCI_REG_TIMEOUT 0x0140 | |
| 37663860 | 583 | |
| 2ef1bb99 ML |
584 | /* PCI controller block register bits */ |
| 585 | #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ | |
| 586 | #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) | |
| 587 | #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) | |
| 588 | #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ | |
| 589 | #define PCI_CONFIG_ET (1 << 26) /* error in target mode */ | |
| 590 | #define PCI_CONFIG_EF (1 << 25) /* fatal error */ | |
| 591 | #define PCI_CONFIG_EP (1 << 24) /* parity error */ | |
| 592 | #define PCI_CONFIG_EM (1 << 23) /* multiple errors */ | |
| 593 | #define PCI_CONFIG_BM (1 << 22) /* bad master error */ | |
| 594 | #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ | |
| 595 | #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ | |
| 596 | #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ | |
| 597 | #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ | |
| 598 | #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ | |
| 599 | #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ | |
| 600 | #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ | |
| 601 | #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ | |
| 602 | #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ | |
| 603 | #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ | |
| 604 | #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ | |
| 605 | #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ | |
| 606 | #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ | |
| 607 | #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ | |
| 608 | #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ | |
| 609 | #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ | |
| 610 | #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ | |
| 611 | #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ | |
| 612 | #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ | |
| 613 | #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ | |
| 614 | #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) | |
| 615 | #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ | |
| 616 | #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) | |
| 617 | #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) | |
| 618 | #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) | |
| 619 | #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) | |
| 620 | #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) | |
| 621 | #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) | |
| 622 | #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) | |
| 623 | #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) | |
| 624 | #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) | |
| 625 | #define PCI_ID_DID(x) (((x) & 0xffff) << 16) | |
| 626 | #define PCI_ID_VID(x) ((x) & 0xffff) | |
| 627 | #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) | |
| 628 | #define PCI_STATCMD_CMD(x) ((x) & 0xffff) | |
| 629 | #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) | |
| 630 | #define PCI_CLASSREV_REV(x) ((x) & 0xff) | |
| 631 | #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) | |
| 632 | #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) | |
| 633 | #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) | |
| 634 | #define PCI_PARAM_CLS(x) ((x) & 0xff) | |
| 635 | #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ | |
| 636 | #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ | |
| 37663860 | 637 | |
| 37663860 | 638 | |
| 2ef1bb99 | 639 | /**********************************************************************/ |
| 1da177e4 | 640 | |
| 1da177e4 | 641 | |
| 2ef1bb99 | 642 | #ifndef _LANGUAGE_ASSEMBLY |
| 1da177e4 | 643 | |
| 2ef1bb99 ML |
644 | #include <linux/delay.h> |
| 645 | #include <linux/types.h> | |
| 1da177e4 | 646 | |
| 2ef1bb99 ML |
647 | #include <linux/io.h> |
| 648 | #include <linux/irq.h> | |
| 1da177e4 | 649 | |
| 2ef1bb99 | 650 | #include <asm/cpu.h> |
| 1da177e4 | 651 | |
| 2ef1bb99 ML |
652 | /* cpu pipeline flush */ |
| 653 | void static inline au_sync(void) | |
| 654 | { | |
| 655 | __asm__ volatile ("sync"); | |
| 656 | } | |
| 0f0d85bc | 657 | |
| 2ef1bb99 ML |
658 | void static inline au_sync_udelay(int us) |
| 659 | { | |
| 660 | __asm__ volatile ("sync"); | |
| 661 | udelay(us); | |
| 662 | } | |
| 1da177e4 | 663 | |
| 2ef1bb99 ML |
664 | void static inline au_sync_delay(int ms) |
| 665 | { | |
| 666 | __asm__ volatile ("sync"); | |
| 667 | mdelay(ms); | |
| 668 | } | |
| 1da177e4 | 669 | |
| 2ef1bb99 ML |
670 | void static inline au_writeb(u8 val, unsigned long reg) |
| 671 | { | |
| 672 | *(volatile u8 *)reg = val; | |
| 673 | } | |
| 1da177e4 | 674 | |
| 2ef1bb99 ML |
675 | void static inline au_writew(u16 val, unsigned long reg) |
| 676 | { | |
| 677 | *(volatile u16 *)reg = val; | |
| 678 | } | |
| cd671c16 | 679 | |
| 2ef1bb99 ML |
680 | void static inline au_writel(u32 val, unsigned long reg) |
| 681 | { | |
| 682 | *(volatile u32 *)reg = val; | |
| 683 | } | |
| cd671c16 | 684 | |
| 2ef1bb99 ML |
685 | static inline u8 au_readb(unsigned long reg) |
| 686 | { | |
| 687 | return *(volatile u8 *)reg; | |
| 688 | } | |
| cd671c16 | 689 | |
| 2ef1bb99 ML |
690 | static inline u16 au_readw(unsigned long reg) |
| 691 | { | |
| 692 | return *(volatile u16 *)reg; | |
| 693 | } | |
| 1da177e4 | 694 | |
| 2ef1bb99 ML |
695 | static inline u32 au_readl(unsigned long reg) |
| 696 | { | |
| 697 | return *(volatile u32 *)reg; | |
| 698 | } | |
| ff6814d5 | 699 | |
| 1d09de7d ML |
700 | /* helpers to access the SYS_* registers */ |
| 701 | static inline unsigned long alchemy_rdsys(int regofs) | |
| 702 | { | |
| 703 | void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | |
| 704 | ||
| 705 | return __raw_readl(b + regofs); | |
| 706 | } | |
| 707 | ||
| 708 | static inline void alchemy_wrsys(unsigned long v, int regofs) | |
| 709 | { | |
| 710 | void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | |
| 711 | ||
| 712 | __raw_writel(v, b + regofs); | |
| 713 | wmb(); /* drain writebuffer */ | |
| 714 | } | |
| 715 | ||
| 2ef1bb99 ML |
716 | /* Early Au1000 have a write-only SYS_CPUPLL register. */ |
| 717 | static inline int au1xxx_cpu_has_pll_wo(void) | |
| 718 | { | |
| 719 | switch (read_c0_prid()) { | |
| 720 | case 0x00030100: /* Au1000 DA */ | |
| 721 | case 0x00030201: /* Au1000 HA */ | |
| 722 | case 0x00030202: /* Au1000 HB */ | |
| 723 | return 1; | |
| 724 | } | |
| 725 | return 0; | |
| 726 | } | |
| ff6814d5 | 727 | |
| 2ef1bb99 ML |
728 | /* does CPU need CONFIG[OD] set to fix tons of errata? */ |
| 729 | static inline int au1xxx_cpu_needs_config_od(void) | |
| 730 | { | |
| 731 | /* | |
| 732 | * c0_config.od (bit 19) was write only (and read as 0) on the | |
| 733 | * early revisions of Alchemy SOCs. It disables the bus trans- | |
| 734 | * action overlapping and needs to be set to fix various errata. | |
| 735 | */ | |
| 736 | switch (read_c0_prid()) { | |
| 737 | case 0x00030100: /* Au1000 DA */ | |
| 738 | case 0x00030201: /* Au1000 HA */ | |
| 739 | case 0x00030202: /* Au1000 HB */ | |
| 740 | case 0x01030200: /* Au1500 AB */ | |
| 741 | /* | |
| 742 | * Au1100/Au1200 errata actually keep silence about this bit, | |
| 743 | * so we set it just in case for those revisions that require | |
| 744 | * it to be set according to the (now gone) cpu_table. | |
| 745 | */ | |
| 746 | case 0x02030200: /* Au1100 AB */ | |
| 747 | case 0x02030201: /* Au1100 BA */ | |
| 748 | case 0x02030202: /* Au1100 BC */ | |
| 749 | case 0x04030201: /* Au1200 AC */ | |
| 750 | return 1; | |
| 751 | } | |
| 752 | return 0; | |
| 753 | } | |
| ff6814d5 | 754 | |
| 2ef1bb99 ML |
755 | #define ALCHEMY_CPU_UNKNOWN -1 |
| 756 | #define ALCHEMY_CPU_AU1000 0 | |
| 757 | #define ALCHEMY_CPU_AU1500 1 | |
| 758 | #define ALCHEMY_CPU_AU1100 2 | |
| 759 | #define ALCHEMY_CPU_AU1550 3 | |
| 760 | #define ALCHEMY_CPU_AU1200 4 | |
| 761 | #define ALCHEMY_CPU_AU1300 5 | |
| e3ad1c23 | 762 | |
| 2ef1bb99 ML |
763 | static inline int alchemy_get_cputype(void) |
| 764 | { | |
| 765 | switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) { | |
| 766 | case 0x00030000: | |
| 767 | return ALCHEMY_CPU_AU1000; | |
| 768 | break; | |
| 769 | case 0x01030000: | |
| 770 | return ALCHEMY_CPU_AU1500; | |
| 771 | break; | |
| 772 | case 0x02030000: | |
| 773 | return ALCHEMY_CPU_AU1100; | |
| 774 | break; | |
| 775 | case 0x03030000: | |
| 776 | return ALCHEMY_CPU_AU1550; | |
| 777 | break; | |
| 778 | case 0x04030000: | |
| 779 | case 0x05030000: | |
| 780 | return ALCHEMY_CPU_AU1200; | |
| 781 | break; | |
| 782 | case 0x800c0000: | |
| 783 | return ALCHEMY_CPU_AU1300; | |
| 784 | break; | |
| 785 | } | |
| 1da177e4 | 786 | |
| 2ef1bb99 ML |
787 | return ALCHEMY_CPU_UNKNOWN; |
| 788 | } | |
| 61f9c58d | 789 | |
| 2ef1bb99 ML |
790 | /* return number of uarts on a given cputype */ |
| 791 | static inline int alchemy_get_uarts(int type) | |
| 792 | { | |
| 793 | switch (type) { | |
| 794 | case ALCHEMY_CPU_AU1000: | |
| 795 | case ALCHEMY_CPU_AU1300: | |
| 796 | return 4; | |
| 797 | case ALCHEMY_CPU_AU1500: | |
| 798 | case ALCHEMY_CPU_AU1200: | |
| 799 | return 2; | |
| 800 | case ALCHEMY_CPU_AU1100: | |
| 801 | case ALCHEMY_CPU_AU1550: | |
| 802 | return 3; | |
| 803 | } | |
| 804 | return 0; | |
| 805 | } | |
| 37663860 | 806 | |
| 2ef1bb99 ML |
807 | /* enable an UART block if it isn't already */ |
| 808 | static inline void alchemy_uart_enable(u32 uart_phys) | |
| 809 | { | |
| 810 | void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); | |
| 37663860 | 811 | |
| 2ef1bb99 ML |
812 | /* reset, enable clock, deassert reset */ |
| 813 | if ((__raw_readl(addr + 0x100) & 3) != 3) { | |
| 814 | __raw_writel(0, addr + 0x100); | |
| 815 | wmb(); /* drain writebuffer */ | |
| 816 | __raw_writel(1, addr + 0x100); | |
| 817 | wmb(); /* drain writebuffer */ | |
| 818 | } | |
| 819 | __raw_writel(3, addr + 0x100); | |
| 820 | wmb(); /* drain writebuffer */ | |
| 821 | } | |
| 37663860 | 822 | |
| 2ef1bb99 ML |
823 | static inline void alchemy_uart_disable(u32 uart_phys) |
| 824 | { | |
| 825 | void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); | |
| ff6814d5 | 826 | |
| 2ef1bb99 ML |
827 | __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ |
| 828 | wmb(); /* drain writebuffer */ | |
| 829 | } | |
| 1da177e4 | 830 | |
| 2ef1bb99 ML |
831 | static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) |
| 832 | { | |
| 833 | void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); | |
| 834 | int timeout, i; | |
| 1da177e4 | 835 | |
| 2ef1bb99 ML |
836 | /* check LSR TX_EMPTY bit */ |
| 837 | timeout = 0xffffff; | |
| 838 | do { | |
| 839 | if (__raw_readl(base + 0x1c) & 0x20) | |
| 840 | break; | |
| 841 | /* slow down */ | |
| 842 | for (i = 10000; i; i--) | |
| 843 | asm volatile ("nop"); | |
| 844 | } while (--timeout); | |
| 1da177e4 | 845 | |
| 2ef1bb99 ML |
846 | __raw_writel(c, base + 0x04); /* tx */ |
| 847 | wmb(); /* drain writebuffer */ | |
| 848 | } | |
| dd99d966 | 849 | |
| 2ef1bb99 ML |
850 | /* return number of ethernet MACs on a given cputype */ |
| 851 | static inline int alchemy_get_macs(int type) | |
| 852 | { | |
| 853 | switch (type) { | |
| 854 | case ALCHEMY_CPU_AU1000: | |
| 855 | case ALCHEMY_CPU_AU1500: | |
| 856 | case ALCHEMY_CPU_AU1550: | |
| 857 | return 2; | |
| 858 | case ALCHEMY_CPU_AU1100: | |
| 859 | return 1; | |
| 860 | } | |
| 861 | return 0; | |
| 862 | } | |
| 1da177e4 | 863 | |
| 2ef1bb99 ML |
864 | /* arch/mips/au1000/common/clocks.c */ |
| 865 | extern void set_au1x00_speed(unsigned int new_freq); | |
| 866 | extern unsigned int get_au1x00_speed(void); | |
| 867 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); | |
| 868 | extern unsigned long get_au1x00_uart_baud_base(void); | |
| 869 | extern unsigned long au1xxx_calc_clock(void); | |
| 1da177e4 | 870 | |
| 2ef1bb99 ML |
871 | /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ |
| 872 | void alchemy_sleep_au1000(void); | |
| 873 | void alchemy_sleep_au1550(void); | |
| 874 | void alchemy_sleep_au1300(void); | |
| 875 | void au_sleep(void); | |
| 1da177e4 | 876 | |
| 2ef1bb99 ML |
877 | /* USB: arch/mips/alchemy/common/usb.c */ |
| 878 | enum alchemy_usb_block { | |
| 879 | ALCHEMY_USB_OHCI0, | |
| 880 | ALCHEMY_USB_UDC0, | |
| 881 | ALCHEMY_USB_EHCI0, | |
| 882 | ALCHEMY_USB_OTG0, | |
| 883 | ALCHEMY_USB_OHCI1, | |
| 884 | }; | |
| 885 | int alchemy_usb_control(int block, int enable); | |
| 1da177e4 | 886 | |
| 2ef1bb99 ML |
887 | /* PCI controller platform data */ |
| 888 | struct alchemy_pci_platdata { | |
| 889 | int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); | |
| 890 | int (*board_pci_idsel)(unsigned int devsel, int assert); | |
| 891 | /* bits to set/clear in PCI_CONFIG register */ | |
| 892 | unsigned long pci_cfg_set; | |
| 893 | unsigned long pci_cfg_clr; | |
| 894 | }; | |
| 1da177e4 | 895 | |
| 2ef1bb99 ML |
896 | /* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's |
| 897 | * not used to select FIR/SIR mode on the transceiver but as a GPIO. | |
| 898 | * Instead a CPLD has to be told about the mode. The driver calls the | |
| 899 | * set_phy_mode() function in addition to driving the IRFIRSEL pin. | |
| 900 | */ | |
| 901 | #define AU1000_IRDA_PHY_MODE_OFF 0 | |
| 902 | #define AU1000_IRDA_PHY_MODE_SIR 1 | |
| 903 | #define AU1000_IRDA_PHY_MODE_FIR 2 | |
| 7517de34 | 904 | |
| 2ef1bb99 ML |
905 | struct au1k_irda_platform_data { |
| 906 | void (*set_phy_mode)(int mode); | |
| 907 | }; | |
| 908 | ||
| 909 | ||
| 910 | /* Multifunction pins: Each of these pins can either be assigned to the | |
| 911 | * GPIO controller or a on-chip peripheral. | |
| 912 | * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to | |
| 913 | * assign one of these to either the GPIO controller or the device. | |
| 914 | */ | |
| 915 | enum au1300_multifunc_pins { | |
| 916 | /* wake-from-str pins 0-3 */ | |
| 917 | AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, | |
| 918 | AU1300_PIN_WAKE3, | |
| 919 | /* external clock sources for PSCs: 4-5 */ | |
| 920 | AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, | |
| 921 | /* 8bit MMC interface on SD0: 6-9 */ | |
| 922 | AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, | |
| 923 | AU1300_PIN_SD0DAT7, | |
| 924 | /* aux clk input for freqgen 3: 10 */ | |
| 925 | AU1300_PIN_FG3AUX, | |
| 926 | /* UART1 pins: 11-18 */ | |
| 927 | AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, | |
| 928 | AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, | |
| 929 | AU1300_PIN_U1RX, AU1300_PIN_U1TX, | |
| 930 | /* UART0 pins: 19-24 */ | |
| 931 | AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, | |
| 932 | AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, | |
| 933 | /* UART2: 25-26 */ | |
| 934 | AU1300_PIN_U2RX, AU1300_PIN_U2TX, | |
| 935 | /* UART3: 27-28 */ | |
| 936 | AU1300_PIN_U3RX, AU1300_PIN_U3TX, | |
| 937 | /* LCD controller PWMs, ext pixclock: 29-31 */ | |
| 938 | AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, | |
| 939 | /* SD1 interface: 32-37 */ | |
| 940 | AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, | |
| 941 | AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, | |
| 942 | /* SD2 interface: 38-43 */ | |
| 943 | AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, | |
| 944 | AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, | |
| 945 | /* PSC0/1 clocks: 44-45 */ | |
| 946 | AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, | |
| 947 | /* PSCs: 46-49/50-53/54-57/58-61 */ | |
| 948 | AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, | |
| 949 | AU1300_PIN_PSC0D1, | |
| 950 | AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, | |
| 951 | AU1300_PIN_PSC1D1, | |
| 952 | AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, | |
| 953 | AU1300_PIN_PSC2D1, | |
| 954 | AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, | |
| 955 | AU1300_PIN_PSC3D1, | |
| 956 | /* PCMCIA interface: 62-70 */ | |
| 957 | AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, | |
| 958 | AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, | |
| 959 | AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, | |
| 960 | /* camera interface H/V sync inputs: 71-72 */ | |
| 961 | AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, | |
| 962 | /* PSC2/3 clocks: 73-74 */ | |
| 963 | AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, | |
| 964 | }; | |
| 965 | ||
| 966 | /* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ | |
| 967 | extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); | |
| 968 | extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); | |
| 969 | extern void au1300_set_irq_priority(unsigned int irq, int p); | |
| 970 | extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); | |
| 971 | ||
| 972 | /* Au1300 allows to disconnect certain blocks from internal power supply */ | |
| 973 | enum au1300_vss_block { | |
| 974 | AU1300_VSS_MPE = 0, | |
| 975 | AU1300_VSS_BSA, | |
| 976 | AU1300_VSS_GPE, | |
| 977 | AU1300_VSS_MGP, | |
| 978 | }; | |
| 979 | ||
| 980 | extern void au1300_vss_block_control(int block, int enable); | |
| 981 | ||
| 982 | enum soc_au1000_ints { | |
| 983 | AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, | |
| 984 | AU1000_UART0_INT = AU1000_FIRST_INT, | |
| 985 | AU1000_UART1_INT, | |
| 986 | AU1000_UART2_INT, | |
| 987 | AU1000_UART3_INT, | |
| 988 | AU1000_SSI0_INT, | |
| 989 | AU1000_SSI1_INT, | |
| 990 | AU1000_DMA_INT_BASE, | |
| 991 | ||
| 992 | AU1000_TOY_INT = AU1000_FIRST_INT + 14, | |
| 993 | AU1000_TOY_MATCH0_INT, | |
| 994 | AU1000_TOY_MATCH1_INT, | |
| 995 | AU1000_TOY_MATCH2_INT, | |
| 996 | AU1000_RTC_INT, | |
| 997 | AU1000_RTC_MATCH0_INT, | |
| 998 | AU1000_RTC_MATCH1_INT, | |
| 999 | AU1000_RTC_MATCH2_INT, | |
| 1000 | AU1000_IRDA_TX_INT, | |
| 1001 | AU1000_IRDA_RX_INT, | |
| 1002 | AU1000_USB_DEV_REQ_INT, | |
| 1003 | AU1000_USB_DEV_SUS_INT, | |
| 1004 | AU1000_USB_HOST_INT, | |
| 1005 | AU1000_ACSYNC_INT, | |
| 1006 | AU1000_MAC0_DMA_INT, | |
| 1007 | AU1000_MAC1_DMA_INT, | |
| 1008 | AU1000_I2S_UO_INT, | |
| 1009 | AU1000_AC97C_INT, | |
| 1010 | AU1000_GPIO0_INT, | |
| 1011 | AU1000_GPIO1_INT, | |
| 1012 | AU1000_GPIO2_INT, | |
| 1013 | AU1000_GPIO3_INT, | |
| 1014 | AU1000_GPIO4_INT, | |
| 1015 | AU1000_GPIO5_INT, | |
| 1016 | AU1000_GPIO6_INT, | |
| 1017 | AU1000_GPIO7_INT, | |
| 1018 | AU1000_GPIO8_INT, | |
| 1019 | AU1000_GPIO9_INT, | |
| 1020 | AU1000_GPIO10_INT, | |
| 1021 | AU1000_GPIO11_INT, | |
| 1022 | AU1000_GPIO12_INT, | |
| 1023 | AU1000_GPIO13_INT, | |
| 1024 | AU1000_GPIO14_INT, | |
| 1025 | AU1000_GPIO15_INT, | |
| 1026 | AU1000_GPIO16_INT, | |
| 1027 | AU1000_GPIO17_INT, | |
| 1028 | AU1000_GPIO18_INT, | |
| 1029 | AU1000_GPIO19_INT, | |
| 1030 | AU1000_GPIO20_INT, | |
| 1031 | AU1000_GPIO21_INT, | |
| 1032 | AU1000_GPIO22_INT, | |
| 1033 | AU1000_GPIO23_INT, | |
| 1034 | AU1000_GPIO24_INT, | |
| 1035 | AU1000_GPIO25_INT, | |
| 1036 | AU1000_GPIO26_INT, | |
| 1037 | AU1000_GPIO27_INT, | |
| 1038 | AU1000_GPIO28_INT, | |
| 1039 | AU1000_GPIO29_INT, | |
| 1040 | AU1000_GPIO30_INT, | |
| 1041 | AU1000_GPIO31_INT, | |
| 1042 | }; | |
| 1043 | ||
| 1044 | enum soc_au1100_ints { | |
| 1045 | AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, | |
| 1046 | AU1100_UART0_INT = AU1100_FIRST_INT, | |
| 1047 | AU1100_UART1_INT, | |
| 1048 | AU1100_SD_INT, | |
| 1049 | AU1100_UART3_INT, | |
| 1050 | AU1100_SSI0_INT, | |
| 1051 | AU1100_SSI1_INT, | |
| 1052 | AU1100_DMA_INT_BASE, | |
| 1053 | ||
| 1054 | AU1100_TOY_INT = AU1100_FIRST_INT + 14, | |
| 1055 | AU1100_TOY_MATCH0_INT, | |
| 1056 | AU1100_TOY_MATCH1_INT, | |
| 1057 | AU1100_TOY_MATCH2_INT, | |
| 1058 | AU1100_RTC_INT, | |
| 1059 | AU1100_RTC_MATCH0_INT, | |
| 1060 | AU1100_RTC_MATCH1_INT, | |
| 1061 | AU1100_RTC_MATCH2_INT, | |
| 1062 | AU1100_IRDA_TX_INT, | |
| 1063 | AU1100_IRDA_RX_INT, | |
| 1064 | AU1100_USB_DEV_REQ_INT, | |
| 1065 | AU1100_USB_DEV_SUS_INT, | |
| 1066 | AU1100_USB_HOST_INT, | |
| 1067 | AU1100_ACSYNC_INT, | |
| 1068 | AU1100_MAC0_DMA_INT, | |
| 1069 | AU1100_GPIO208_215_INT, | |
| 1070 | AU1100_LCD_INT, | |
| 1071 | AU1100_AC97C_INT, | |
| 1072 | AU1100_GPIO0_INT, | |
| 1073 | AU1100_GPIO1_INT, | |
| 1074 | AU1100_GPIO2_INT, | |
| 1075 | AU1100_GPIO3_INT, | |
| 1076 | AU1100_GPIO4_INT, | |
| 1077 | AU1100_GPIO5_INT, | |
| 1078 | AU1100_GPIO6_INT, | |
| 1079 | AU1100_GPIO7_INT, | |
| 1080 | AU1100_GPIO8_INT, | |
| 1081 | AU1100_GPIO9_INT, | |
| 1082 | AU1100_GPIO10_INT, | |
| 1083 | AU1100_GPIO11_INT, | |
| 1084 | AU1100_GPIO12_INT, | |
| 1085 | AU1100_GPIO13_INT, | |
| 1086 | AU1100_GPIO14_INT, | |
| 1087 | AU1100_GPIO15_INT, | |
| 1088 | AU1100_GPIO16_INT, | |
| 1089 | AU1100_GPIO17_INT, | |
| 1090 | AU1100_GPIO18_INT, | |
| 1091 | AU1100_GPIO19_INT, | |
| 1092 | AU1100_GPIO20_INT, | |
| 1093 | AU1100_GPIO21_INT, | |
| 1094 | AU1100_GPIO22_INT, | |
| 1095 | AU1100_GPIO23_INT, | |
| 1096 | AU1100_GPIO24_INT, | |
| 1097 | AU1100_GPIO25_INT, | |
| 1098 | AU1100_GPIO26_INT, | |
| 1099 | AU1100_GPIO27_INT, | |
| 1100 | AU1100_GPIO28_INT, | |
| 1101 | AU1100_GPIO29_INT, | |
| 1102 | AU1100_GPIO30_INT, | |
| 1103 | AU1100_GPIO31_INT, | |
| 1104 | }; | |
| 1105 | ||
| 1106 | enum soc_au1500_ints { | |
| 1107 | AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, | |
| 1108 | AU1500_UART0_INT = AU1500_FIRST_INT, | |
| 1109 | AU1500_PCI_INTA, | |
| 1110 | AU1500_PCI_INTB, | |
| 1111 | AU1500_UART3_INT, | |
| 1112 | AU1500_PCI_INTC, | |
| 1113 | AU1500_PCI_INTD, | |
| 1114 | AU1500_DMA_INT_BASE, | |
| 1115 | ||
| 1116 | AU1500_TOY_INT = AU1500_FIRST_INT + 14, | |
| 1117 | AU1500_TOY_MATCH0_INT, | |
| 1118 | AU1500_TOY_MATCH1_INT, | |
| 1119 | AU1500_TOY_MATCH2_INT, | |
| 1120 | AU1500_RTC_INT, | |
| 1121 | AU1500_RTC_MATCH0_INT, | |
| 1122 | AU1500_RTC_MATCH1_INT, | |
| 1123 | AU1500_RTC_MATCH2_INT, | |
| 1124 | AU1500_PCI_ERR_INT, | |
| 1125 | AU1500_RESERVED_INT, | |
| 1126 | AU1500_USB_DEV_REQ_INT, | |
| 1127 | AU1500_USB_DEV_SUS_INT, | |
| 1128 | AU1500_USB_HOST_INT, | |
| 1129 | AU1500_ACSYNC_INT, | |
| 1130 | AU1500_MAC0_DMA_INT, | |
| 1131 | AU1500_MAC1_DMA_INT, | |
| 1132 | AU1500_AC97C_INT = AU1500_FIRST_INT + 31, | |
| 1133 | AU1500_GPIO0_INT, | |
| 1134 | AU1500_GPIO1_INT, | |
| 1135 | AU1500_GPIO2_INT, | |
| 1136 | AU1500_GPIO3_INT, | |
| 1137 | AU1500_GPIO4_INT, | |
| 1138 | AU1500_GPIO5_INT, | |
| 1139 | AU1500_GPIO6_INT, | |
| 1140 | AU1500_GPIO7_INT, | |
| 1141 | AU1500_GPIO8_INT, | |
| 1142 | AU1500_GPIO9_INT, | |
| 1143 | AU1500_GPIO10_INT, | |
| 1144 | AU1500_GPIO11_INT, | |
| 1145 | AU1500_GPIO12_INT, | |
| 1146 | AU1500_GPIO13_INT, | |
| 1147 | AU1500_GPIO14_INT, | |
| 1148 | AU1500_GPIO15_INT, | |
| 1149 | AU1500_GPIO200_INT, | |
| 1150 | AU1500_GPIO201_INT, | |
| 1151 | AU1500_GPIO202_INT, | |
| 1152 | AU1500_GPIO203_INT, | |
| 1153 | AU1500_GPIO20_INT, | |
| 1154 | AU1500_GPIO204_INT, | |
| 1155 | AU1500_GPIO205_INT, | |
| 1156 | AU1500_GPIO23_INT, | |
| 1157 | AU1500_GPIO24_INT, | |
| 1158 | AU1500_GPIO25_INT, | |
| 1159 | AU1500_GPIO26_INT, | |
| 1160 | AU1500_GPIO27_INT, | |
| 1161 | AU1500_GPIO28_INT, | |
| 1162 | AU1500_GPIO206_INT, | |
| 1163 | AU1500_GPIO207_INT, | |
| 1164 | AU1500_GPIO208_215_INT, | |
| 1165 | }; | |
| 1166 | ||
| 1167 | enum soc_au1550_ints { | |
| 1168 | AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, | |
| 1169 | AU1550_UART0_INT = AU1550_FIRST_INT, | |
| 1170 | AU1550_PCI_INTA, | |
| 1171 | AU1550_PCI_INTB, | |
| 1172 | AU1550_DDMA_INT, | |
| 1173 | AU1550_CRYPTO_INT, | |
| 1174 | AU1550_PCI_INTC, | |
| 1175 | AU1550_PCI_INTD, | |
| 1176 | AU1550_PCI_RST_INT, | |
| 1177 | AU1550_UART1_INT, | |
| 1178 | AU1550_UART3_INT, | |
| 1179 | AU1550_PSC0_INT, | |
| 1180 | AU1550_PSC1_INT, | |
| 1181 | AU1550_PSC2_INT, | |
| 1182 | AU1550_PSC3_INT, | |
| 1183 | AU1550_TOY_INT, | |
| 1184 | AU1550_TOY_MATCH0_INT, | |
| 1185 | AU1550_TOY_MATCH1_INT, | |
| 1186 | AU1550_TOY_MATCH2_INT, | |
| 1187 | AU1550_RTC_INT, | |
| 1188 | AU1550_RTC_MATCH0_INT, | |
| 1189 | AU1550_RTC_MATCH1_INT, | |
| 1190 | AU1550_RTC_MATCH2_INT, | |
| 1191 | ||
| 1192 | AU1550_NAND_INT = AU1550_FIRST_INT + 23, | |
| 1193 | AU1550_USB_DEV_REQ_INT, | |
| 1194 | AU1550_USB_DEV_SUS_INT, | |
| 1195 | AU1550_USB_HOST_INT, | |
| 1196 | AU1550_MAC0_DMA_INT, | |
| 1197 | AU1550_MAC1_DMA_INT, | |
| 1198 | AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, | |
| 1199 | AU1550_GPIO1_INT, | |
| 1200 | AU1550_GPIO2_INT, | |
| 1201 | AU1550_GPIO3_INT, | |
| 1202 | AU1550_GPIO4_INT, | |
| 1203 | AU1550_GPIO5_INT, | |
| 1204 | AU1550_GPIO6_INT, | |
| 1205 | AU1550_GPIO7_INT, | |
| 1206 | AU1550_GPIO8_INT, | |
| 1207 | AU1550_GPIO9_INT, | |
| 1208 | AU1550_GPIO10_INT, | |
| 1209 | AU1550_GPIO11_INT, | |
| 1210 | AU1550_GPIO12_INT, | |
| 1211 | AU1550_GPIO13_INT, | |
| 1212 | AU1550_GPIO14_INT, | |
| 1213 | AU1550_GPIO15_INT, | |
| 1214 | AU1550_GPIO200_INT, | |
| 1215 | AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ | |
| 1216 | AU1550_GPIO16_INT, | |
| 1217 | AU1550_GPIO17_INT, | |
| 1218 | AU1550_GPIO20_INT, | |
| 1219 | AU1550_GPIO21_INT, | |
| 1220 | AU1550_GPIO22_INT, | |
| 1221 | AU1550_GPIO23_INT, | |
| 1222 | AU1550_GPIO24_INT, | |
| 1223 | AU1550_GPIO25_INT, | |
| 1224 | AU1550_GPIO26_INT, | |
| 1225 | AU1550_GPIO27_INT, | |
| 1226 | AU1550_GPIO28_INT, | |
| 1227 | AU1550_GPIO206_INT, | |
| 1228 | AU1550_GPIO207_INT, | |
| 1229 | AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ | |
| 1230 | }; | |
| 1231 | ||
| 1232 | enum soc_au1200_ints { | |
| 1233 | AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, | |
| 1234 | AU1200_UART0_INT = AU1200_FIRST_INT, | |
| 1235 | AU1200_SWT_INT, | |
| 1236 | AU1200_SD_INT, | |
| 1237 | AU1200_DDMA_INT, | |
| 1238 | AU1200_MAE_BE_INT, | |
| 1239 | AU1200_GPIO200_INT, | |
| 1240 | AU1200_GPIO201_INT, | |
| 1241 | AU1200_GPIO202_INT, | |
| 1242 | AU1200_UART1_INT, | |
| 1243 | AU1200_MAE_FE_INT, | |
| 1244 | AU1200_PSC0_INT, | |
| 1245 | AU1200_PSC1_INT, | |
| 1246 | AU1200_AES_INT, | |
| 1247 | AU1200_CAMERA_INT, | |
| 1248 | AU1200_TOY_INT, | |
| 1249 | AU1200_TOY_MATCH0_INT, | |
| 1250 | AU1200_TOY_MATCH1_INT, | |
| 1251 | AU1200_TOY_MATCH2_INT, | |
| 1252 | AU1200_RTC_INT, | |
| 1253 | AU1200_RTC_MATCH0_INT, | |
| 1254 | AU1200_RTC_MATCH1_INT, | |
| 1255 | AU1200_RTC_MATCH2_INT, | |
| 1256 | AU1200_GPIO203_INT, | |
| 1257 | AU1200_NAND_INT, | |
| 1258 | AU1200_GPIO204_INT, | |
| 1259 | AU1200_GPIO205_INT, | |
| 1260 | AU1200_GPIO206_INT, | |
| 1261 | AU1200_GPIO207_INT, | |
| 1262 | AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ | |
| 1263 | AU1200_USB_INT, | |
| 1264 | AU1200_LCD_INT, | |
| 1265 | AU1200_MAE_BOTH_INT, | |
| 1266 | AU1200_GPIO0_INT, | |
| 1267 | AU1200_GPIO1_INT, | |
| 1268 | AU1200_GPIO2_INT, | |
| 1269 | AU1200_GPIO3_INT, | |
| 1270 | AU1200_GPIO4_INT, | |
| 1271 | AU1200_GPIO5_INT, | |
| 1272 | AU1200_GPIO6_INT, | |
| 1273 | AU1200_GPIO7_INT, | |
| 1274 | AU1200_GPIO8_INT, | |
| 1275 | AU1200_GPIO9_INT, | |
| 1276 | AU1200_GPIO10_INT, | |
| 1277 | AU1200_GPIO11_INT, | |
| 1278 | AU1200_GPIO12_INT, | |
| 1279 | AU1200_GPIO13_INT, | |
| 1280 | AU1200_GPIO14_INT, | |
| 1281 | AU1200_GPIO15_INT, | |
| 1282 | AU1200_GPIO16_INT, | |
| 1283 | AU1200_GPIO17_INT, | |
| 1284 | AU1200_GPIO18_INT, | |
| 1285 | AU1200_GPIO19_INT, | |
| 1286 | AU1200_GPIO20_INT, | |
| 1287 | AU1200_GPIO21_INT, | |
| 1288 | AU1200_GPIO22_INT, | |
| 1289 | AU1200_GPIO23_INT, | |
| 1290 | AU1200_GPIO24_INT, | |
| 1291 | AU1200_GPIO25_INT, | |
| 1292 | AU1200_GPIO26_INT, | |
| 1293 | AU1200_GPIO27_INT, | |
| 1294 | AU1200_GPIO28_INT, | |
| 1295 | AU1200_GPIO29_INT, | |
| 1296 | AU1200_GPIO30_INT, | |
| 1297 | AU1200_GPIO31_INT, | |
| 1298 | }; | |
| 1299 | ||
| 1300 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | |
| 7517de34 | 1301 | |
| e3ad1c23 | 1302 | #endif |