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ca585cf9 KC |
1 | /* |
2 | * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> | |
3 | * | |
4 | * IRQ mappings for Loongson 1 | |
5 | * | |
70342287 RB |
6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the | |
ca585cf9 KC |
8 | * Free Software Foundation; either version 2 of the License, or (at your |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | ||
13 | #ifndef __ASM_MACH_LOONGSON1_IRQ_H | |
14 | #define __ASM_MACH_LOONGSON1_IRQ_H | |
15 | ||
16 | /* | |
17 | * CPU core Interrupt Numbers | |
18 | */ | |
19 | #define MIPS_CPU_IRQ_BASE 0 | |
20 | #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) | |
21 | ||
22 | #define SOFTINT0_IRQ MIPS_CPU_IRQ(0) | |
23 | #define SOFTINT1_IRQ MIPS_CPU_IRQ(1) | |
24 | #define INT0_IRQ MIPS_CPU_IRQ(2) | |
25 | #define INT1_IRQ MIPS_CPU_IRQ(3) | |
26 | #define INT2_IRQ MIPS_CPU_IRQ(4) | |
27 | #define INT3_IRQ MIPS_CPU_IRQ(5) | |
28 | #define INT4_IRQ MIPS_CPU_IRQ(6) | |
29 | #define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ | |
30 | ||
31 | #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) | |
32 | ||
33 | /* | |
34 | * INT0~3 Interrupt Numbers | |
35 | */ | |
36 | #define LS1X_IRQ_BASE MIPS_CPU_IRQS | |
37 | #define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) | |
38 | ||
39 | #define LS1X_UART0_IRQ LS1X_IRQ(0, 2) | |
40 | #define LS1X_UART1_IRQ LS1X_IRQ(0, 3) | |
41 | #define LS1X_UART2_IRQ LS1X_IRQ(0, 4) | |
42 | #define LS1X_UART3_IRQ LS1X_IRQ(0, 5) | |
43 | #define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) | |
44 | #define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) | |
45 | #define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) | |
46 | #define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) | |
47 | #define LS1X_AC97_IRQ LS1X_IRQ(0, 10) | |
48 | #define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) | |
49 | #define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) | |
50 | #define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) | |
51 | #define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) | |
52 | #define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) | |
53 | #define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) | |
54 | #define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) | |
55 | #define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) | |
56 | #define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) | |
57 | #define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) | |
58 | #define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) | |
59 | #define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) | |
60 | #define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) | |
61 | #define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) | |
62 | #define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) | |
63 | ||
64 | #define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) | |
65 | #define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) | |
66 | #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) | |
67 | #define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) | |
68 | ||
69 | #define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) | |
70 | ||
71 | #define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) | |
72 | ||
73 | #endif /* __ASM_MACH_LOONGSON1_IRQ_H */ |