Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / arch / mips / include / asm / mach-sibyte / war.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
9#define __ASM_MIPS_MACH_SIBYTE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15
dd0bc75e 16#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
baf22c1e 17
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18#ifndef __ASSEMBLY__
19extern int sb1250_m3_workaround_needed(void);
20#endif
21
22#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
70342287 23#define SIBYTE_1956_WAR 1
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24
25#else
26
27#define BCM1250_M3_WAR 0
70342287 28#define SIBYTE_1956_WAR 0
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29
30#endif
31
32#define MIPS4K_ICACHE_REFILL_WAR 0
33#define MIPS_CACHE_SYNC_WAR 0
34#define TX49XX_ICACHE_INDEX_INV_WAR 0
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35#define ICACHE_REFILLS_WORKAROUND_WAR 0
36#define R10000_LLSC_WAR 0
37#define MIPS34K_MISSED_ITLB_WAR 0
38
39#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
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