Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle | |
7 | * Copyright (C) 2000 Silicon Graphics, Inc. | |
8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | |
9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
a3692020 | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
4194318c | 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
1da177e4 LT |
12 | */ |
13 | #ifndef _ASM_MIPSREGS_H | |
14 | #define _ASM_MIPSREGS_H | |
15 | ||
1da177e4 | 16 | #include <linux/linkage.h> |
87c99203 | 17 | #include <linux/types.h> |
1da177e4 | 18 | #include <asm/hazards.h> |
9267a30d | 19 | #include <asm/war.h> |
1da177e4 LT |
20 | |
21 | /* | |
22 | * The following macros are especially useful for __asm__ | |
23 | * inline assembler. | |
24 | */ | |
25 | #ifndef __STR | |
26 | #define __STR(x) #x | |
27 | #endif | |
28 | #ifndef STR | |
29 | #define STR(x) __STR(x) | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * Configure language | |
34 | */ | |
35 | #ifdef __ASSEMBLY__ | |
36 | #define _ULCAST_ | |
37 | #else | |
38 | #define _ULCAST_ (unsigned long) | |
39 | #endif | |
40 | ||
41 | /* | |
42 | * Coprocessor 0 register names | |
43 | */ | |
44 | #define CP0_INDEX $0 | |
45 | #define CP0_RANDOM $1 | |
46 | #define CP0_ENTRYLO0 $2 | |
47 | #define CP0_ENTRYLO1 $3 | |
48 | #define CP0_CONF $3 | |
49 | #define CP0_CONTEXT $4 | |
50 | #define CP0_PAGEMASK $5 | |
51 | #define CP0_WIRED $6 | |
52 | #define CP0_INFO $7 | |
195cee92 | 53 | #define CP0_HWRENA $7, 0 |
1da177e4 | 54 | #define CP0_BADVADDR $8 |
609cf6f2 | 55 | #define CP0_BADINSTR $8, 1 |
1da177e4 LT |
56 | #define CP0_COUNT $9 |
57 | #define CP0_ENTRYHI $10 | |
58 | #define CP0_COMPARE $11 | |
59 | #define CP0_STATUS $12 | |
60 | #define CP0_CAUSE $13 | |
61 | #define CP0_EPC $14 | |
62 | #define CP0_PRID $15 | |
609cf6f2 PB |
63 | #define CP0_EBASE $15, 1 |
64 | #define CP0_CMGCRBASE $15, 3 | |
1da177e4 | 65 | #define CP0_CONFIG $16 |
195cee92 JH |
66 | #define CP0_CONFIG3 $16, 3 |
67 | #define CP0_CONFIG5 $16, 5 | |
1da177e4 LT |
68 | #define CP0_LLADDR $17 |
69 | #define CP0_WATCHLO $18 | |
70 | #define CP0_WATCHHI $19 | |
71 | #define CP0_XCONTEXT $20 | |
72 | #define CP0_FRAMEMASK $21 | |
73 | #define CP0_DIAGNOSTIC $22 | |
74 | #define CP0_DEBUG $23 | |
75 | #define CP0_DEPC $24 | |
76 | #define CP0_PERFORMANCE $25 | |
77 | #define CP0_ECC $26 | |
78 | #define CP0_CACHEERR $27 | |
79 | #define CP0_TAGLO $28 | |
80 | #define CP0_TAGHI $29 | |
81 | #define CP0_ERROREPC $30 | |
82 | #define CP0_DESAVE $31 | |
83 | ||
84 | /* | |
85 | * R4640/R4650 cp0 register names. These registers are listed | |
86 | * here only for completeness; without MMU these CPUs are not useable | |
87 | * by Linux. A future ELKS port might take make Linux run on them | |
88 | * though ... | |
89 | */ | |
90 | #define CP0_IBASE $0 | |
91 | #define CP0_IBOUND $1 | |
92 | #define CP0_DBASE $2 | |
93 | #define CP0_DBOUND $3 | |
94 | #define CP0_CALG $17 | |
95 | #define CP0_IWATCH $18 | |
96 | #define CP0_DWATCH $19 | |
97 | ||
98 | /* | |
99 | * Coprocessor 0 Set 1 register names | |
100 | */ | |
101 | #define CP0_S1_DERRADDR0 $26 | |
102 | #define CP0_S1_DERRADDR1 $27 | |
103 | #define CP0_S1_INTCONTROL $20 | |
104 | ||
7a0fc58c RB |
105 | /* |
106 | * Coprocessor 0 Set 2 register names | |
107 | */ | |
108 | #define CP0_S2_SRSCTL $12 /* MIPSR2 */ | |
109 | ||
110 | /* | |
111 | * Coprocessor 0 Set 3 register names | |
112 | */ | |
113 | #define CP0_S3_SRSMAP $12 /* MIPSR2 */ | |
114 | ||
1da177e4 LT |
115 | /* |
116 | * TX39 Series | |
117 | */ | |
118 | #define CP0_TX39_CACHE $7 | |
119 | ||
1da177e4 | 120 | |
bae637a2 JH |
121 | /* Generic EntryLo bit definitions */ |
122 | #define ENTRYLO_G (_ULCAST_(1) << 0) | |
123 | #define ENTRYLO_V (_ULCAST_(1) << 1) | |
124 | #define ENTRYLO_D (_ULCAST_(1) << 2) | |
125 | #define ENTRYLO_C_SHIFT 3 | |
126 | #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) | |
127 | ||
128 | /* R3000 EntryLo bit definitions */ | |
129 | #define R3K_ENTRYLO_G (_ULCAST_(1) << 8) | |
130 | #define R3K_ENTRYLO_V (_ULCAST_(1) << 9) | |
131 | #define R3K_ENTRYLO_D (_ULCAST_(1) << 10) | |
132 | #define R3K_ENTRYLO_N (_ULCAST_(1) << 11) | |
133 | ||
134 | /* MIPS32/64 EntryLo bit definitions */ | |
c6956728 PB |
135 | #define MIPS_ENTRYLO_PFN_SHIFT 6 |
136 | #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) | |
137 | #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) | |
bae637a2 | 138 | |
1da177e4 LT |
139 | /* |
140 | * Values for PageMask register | |
141 | */ | |
142 | #ifdef CONFIG_CPU_VR41XX | |
143 | ||
144 | /* Why doesn't stupidity hurt ... */ | |
145 | ||
146 | #define PM_1K 0x00000000 | |
147 | #define PM_4K 0x00001800 | |
148 | #define PM_16K 0x00007800 | |
149 | #define PM_64K 0x0001f800 | |
150 | #define PM_256K 0x0007f800 | |
151 | ||
152 | #else | |
153 | ||
154 | #define PM_4K 0x00000000 | |
c52399be | 155 | #define PM_8K 0x00002000 |
1da177e4 | 156 | #define PM_16K 0x00006000 |
c52399be | 157 | #define PM_32K 0x0000e000 |
1da177e4 | 158 | #define PM_64K 0x0001e000 |
c52399be | 159 | #define PM_128K 0x0003e000 |
1da177e4 | 160 | #define PM_256K 0x0007e000 |
c52399be | 161 | #define PM_512K 0x000fe000 |
1da177e4 | 162 | #define PM_1M 0x001fe000 |
c52399be | 163 | #define PM_2M 0x003fe000 |
1da177e4 | 164 | #define PM_4M 0x007fe000 |
c52399be | 165 | #define PM_8M 0x00ffe000 |
1da177e4 | 166 | #define PM_16M 0x01ffe000 |
c52399be | 167 | #define PM_32M 0x03ffe000 |
1da177e4 LT |
168 | #define PM_64M 0x07ffe000 |
169 | #define PM_256M 0x1fffe000 | |
542c1020 | 170 | #define PM_1G 0x7fffe000 |
1da177e4 LT |
171 | |
172 | #endif | |
173 | ||
174 | /* | |
175 | * Default page size for a given kernel configuration | |
176 | */ | |
177 | #ifdef CONFIG_PAGE_SIZE_4KB | |
70342287 | 178 | #define PM_DEFAULT_MASK PM_4K |
c52399be | 179 | #elif defined(CONFIG_PAGE_SIZE_8KB) |
70342287 | 180 | #define PM_DEFAULT_MASK PM_8K |
1da177e4 | 181 | #elif defined(CONFIG_PAGE_SIZE_16KB) |
70342287 | 182 | #define PM_DEFAULT_MASK PM_16K |
c52399be | 183 | #elif defined(CONFIG_PAGE_SIZE_32KB) |
70342287 | 184 | #define PM_DEFAULT_MASK PM_32K |
1da177e4 | 185 | #elif defined(CONFIG_PAGE_SIZE_64KB) |
70342287 | 186 | #define PM_DEFAULT_MASK PM_64K |
1da177e4 LT |
187 | #else |
188 | #error Bad page size configuration! | |
189 | #endif | |
190 | ||
dd794392 DD |
191 | /* |
192 | * Default huge tlb size for a given kernel configuration | |
193 | */ | |
194 | #ifdef CONFIG_PAGE_SIZE_4KB | |
195 | #define PM_HUGE_MASK PM_1M | |
196 | #elif defined(CONFIG_PAGE_SIZE_8KB) | |
197 | #define PM_HUGE_MASK PM_4M | |
198 | #elif defined(CONFIG_PAGE_SIZE_16KB) | |
199 | #define PM_HUGE_MASK PM_16M | |
200 | #elif defined(CONFIG_PAGE_SIZE_32KB) | |
201 | #define PM_HUGE_MASK PM_64M | |
202 | #elif defined(CONFIG_PAGE_SIZE_64KB) | |
203 | #define PM_HUGE_MASK PM_256M | |
aa1762f4 | 204 | #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) |
dd794392 DD |
205 | #error Bad page size configuration for hugetlbfs! |
206 | #endif | |
1da177e4 LT |
207 | |
208 | /* | |
209 | * Values used for computation of new tlb entries | |
210 | */ | |
211 | #define PL_4K 12 | |
212 | #define PL_16K 14 | |
213 | #define PL_64K 16 | |
214 | #define PL_256K 18 | |
215 | #define PL_1M 20 | |
216 | #define PL_4M 22 | |
217 | #define PL_16M 24 | |
218 | #define PL_64M 26 | |
219 | #define PL_256M 28 | |
220 | ||
9fe2e9d6 DD |
221 | /* |
222 | * PageGrain bits | |
223 | */ | |
70342287 RB |
224 | #define PG_RIE (_ULCAST_(1) << 31) |
225 | #define PG_XIE (_ULCAST_(1) << 30) | |
226 | #define PG_ELPA (_ULCAST_(1) << 29) | |
227 | #define PG_ESP (_ULCAST_(1) << 28) | |
6575b1d4 | 228 | #define PG_IEC (_ULCAST_(1) << 27) |
9fe2e9d6 | 229 | |
bae637a2 JH |
230 | /* MIPS32/64 EntryHI bit definitions */ |
231 | #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) | |
232 | ||
1da177e4 LT |
233 | /* |
234 | * R4x00 interrupt enable / cause bits | |
235 | */ | |
70342287 RB |
236 | #define IE_SW0 (_ULCAST_(1) << 8) |
237 | #define IE_SW1 (_ULCAST_(1) << 9) | |
238 | #define IE_IRQ0 (_ULCAST_(1) << 10) | |
239 | #define IE_IRQ1 (_ULCAST_(1) << 11) | |
240 | #define IE_IRQ2 (_ULCAST_(1) << 12) | |
241 | #define IE_IRQ3 (_ULCAST_(1) << 13) | |
242 | #define IE_IRQ4 (_ULCAST_(1) << 14) | |
243 | #define IE_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
244 | |
245 | /* | |
246 | * R4x00 interrupt cause bits | |
247 | */ | |
70342287 RB |
248 | #define C_SW0 (_ULCAST_(1) << 8) |
249 | #define C_SW1 (_ULCAST_(1) << 9) | |
250 | #define C_IRQ0 (_ULCAST_(1) << 10) | |
251 | #define C_IRQ1 (_ULCAST_(1) << 11) | |
252 | #define C_IRQ2 (_ULCAST_(1) << 12) | |
253 | #define C_IRQ3 (_ULCAST_(1) << 13) | |
254 | #define C_IRQ4 (_ULCAST_(1) << 14) | |
255 | #define C_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
256 | |
257 | /* | |
258 | * Bitfields in the R4xx0 cp0 status register | |
259 | */ | |
260 | #define ST0_IE 0x00000001 | |
261 | #define ST0_EXL 0x00000002 | |
262 | #define ST0_ERL 0x00000004 | |
263 | #define ST0_KSU 0x00000018 | |
264 | # define KSU_USER 0x00000010 | |
265 | # define KSU_SUPERVISOR 0x00000008 | |
266 | # define KSU_KERNEL 0x00000000 | |
267 | #define ST0_UX 0x00000020 | |
268 | #define ST0_SX 0x00000040 | |
70342287 | 269 | #define ST0_KX 0x00000080 |
1da177e4 LT |
270 | #define ST0_DE 0x00010000 |
271 | #define ST0_CE 0x00020000 | |
272 | ||
273 | /* | |
274 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate | |
275 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 | |
276 | * processors. | |
277 | */ | |
278 | #define ST0_CO 0x08000000 | |
279 | ||
280 | /* | |
281 | * Bitfields in the R[23]000 cp0 status register. | |
282 | */ | |
70342287 | 283 | #define ST0_IEC 0x00000001 |
1da177e4 LT |
284 | #define ST0_KUC 0x00000002 |
285 | #define ST0_IEP 0x00000004 | |
286 | #define ST0_KUP 0x00000008 | |
287 | #define ST0_IEO 0x00000010 | |
288 | #define ST0_KUO 0x00000020 | |
289 | /* bits 6 & 7 are reserved on R[23]000 */ | |
290 | #define ST0_ISC 0x00010000 | |
291 | #define ST0_SWC 0x00020000 | |
292 | #define ST0_CM 0x00080000 | |
293 | ||
294 | /* | |
295 | * Bits specific to the R4640/R4650 | |
296 | */ | |
70342287 | 297 | #define ST0_UM (_ULCAST_(1) << 4) |
1da177e4 LT |
298 | #define ST0_IL (_ULCAST_(1) << 23) |
299 | #define ST0_DL (_ULCAST_(1) << 24) | |
300 | ||
e50c0a8f | 301 | /* |
3301edcb | 302 | * Enable the MIPS MDMX and DSP ASEs |
e50c0a8f RB |
303 | */ |
304 | #define ST0_MX 0x01000000 | |
305 | ||
1da177e4 LT |
306 | /* |
307 | * Status register bits available in all MIPS CPUs. | |
308 | */ | |
309 | #define ST0_IM 0x0000ff00 | |
70342287 RB |
310 | #define STATUSB_IP0 8 |
311 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | |
312 | #define STATUSB_IP1 9 | |
313 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | |
314 | #define STATUSB_IP2 10 | |
315 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | |
316 | #define STATUSB_IP3 11 | |
317 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | |
318 | #define STATUSB_IP4 12 | |
319 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | |
320 | #define STATUSB_IP5 13 | |
321 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | |
322 | #define STATUSB_IP6 14 | |
323 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | |
324 | #define STATUSB_IP7 15 | |
325 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | |
326 | #define STATUSB_IP8 0 | |
327 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | |
328 | #define STATUSB_IP9 1 | |
329 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | |
330 | #define STATUSB_IP10 2 | |
331 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | |
332 | #define STATUSB_IP11 3 | |
333 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | |
334 | #define STATUSB_IP12 4 | |
335 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | |
336 | #define STATUSB_IP13 5 | |
337 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | |
338 | #define STATUSB_IP14 6 | |
339 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | |
340 | #define STATUSB_IP15 7 | |
341 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | |
1da177e4 | 342 | #define ST0_CH 0x00040000 |
96ffa02d | 343 | #define ST0_NMI 0x00080000 |
1da177e4 LT |
344 | #define ST0_SR 0x00100000 |
345 | #define ST0_TS 0x00200000 | |
346 | #define ST0_BEV 0x00400000 | |
347 | #define ST0_RE 0x02000000 | |
348 | #define ST0_FR 0x04000000 | |
349 | #define ST0_CU 0xf0000000 | |
350 | #define ST0_CU0 0x10000000 | |
351 | #define ST0_CU1 0x20000000 | |
352 | #define ST0_CU2 0x40000000 | |
353 | #define ST0_CU3 0x80000000 | |
354 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | |
355 | ||
010c108d DV |
356 | /* |
357 | * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) | |
010c108d | 358 | */ |
9323f84f JH |
359 | #define INTCTLB_IPFDC 23 |
360 | #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) | |
010c108d DV |
361 | #define INTCTLB_IPPCI 26 |
362 | #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) | |
363 | #define INTCTLB_IPTI 29 | |
364 | #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) | |
365 | ||
1da177e4 LT |
366 | /* |
367 | * Bitfields and bit numbers in the coprocessor 0 cause register. | |
368 | * | |
369 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | |
370 | */ | |
1054533a MR |
371 | #define CAUSEB_EXCCODE 2 |
372 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | |
373 | #define CAUSEB_IP 8 | |
374 | #define CAUSEF_IP (_ULCAST_(255) << 8) | |
70342287 RB |
375 | #define CAUSEB_IP0 8 |
376 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | |
377 | #define CAUSEB_IP1 9 | |
378 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | |
379 | #define CAUSEB_IP2 10 | |
380 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | |
381 | #define CAUSEB_IP3 11 | |
382 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | |
383 | #define CAUSEB_IP4 12 | |
384 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | |
385 | #define CAUSEB_IP5 13 | |
386 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | |
387 | #define CAUSEB_IP6 14 | |
388 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | |
389 | #define CAUSEB_IP7 15 | |
390 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | |
1054533a MR |
391 | #define CAUSEB_FDCI 21 |
392 | #define CAUSEF_FDCI (_ULCAST_(1) << 21) | |
e233c733 JH |
393 | #define CAUSEB_WP 22 |
394 | #define CAUSEF_WP (_ULCAST_(1) << 22) | |
1054533a MR |
395 | #define CAUSEB_IV 23 |
396 | #define CAUSEF_IV (_ULCAST_(1) << 23) | |
397 | #define CAUSEB_PCI 26 | |
398 | #define CAUSEF_PCI (_ULCAST_(1) << 26) | |
9fd4af63 JH |
399 | #define CAUSEB_DC 27 |
400 | #define CAUSEF_DC (_ULCAST_(1) << 27) | |
1054533a MR |
401 | #define CAUSEB_CE 28 |
402 | #define CAUSEF_CE (_ULCAST_(3) << 28) | |
403 | #define CAUSEB_TI 30 | |
404 | #define CAUSEF_TI (_ULCAST_(1) << 30) | |
405 | #define CAUSEB_BD 31 | |
406 | #define CAUSEF_BD (_ULCAST_(1) << 31) | |
1da177e4 | 407 | |
16d100db JH |
408 | /* |
409 | * Cause.ExcCode trap codes. | |
410 | */ | |
411 | #define EXCCODE_INT 0 /* Interrupt pending */ | |
412 | #define EXCCODE_MOD 1 /* TLB modified fault */ | |
413 | #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */ | |
414 | #define EXCCODE_TLBS 3 /* TLB miss on a store */ | |
415 | #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */ | |
416 | #define EXCCODE_ADES 5 /* Address error on a store */ | |
417 | #define EXCCODE_IBE 6 /* Bus error on an ifetch */ | |
418 | #define EXCCODE_DBE 7 /* Bus error on a load or store */ | |
419 | #define EXCCODE_SYS 8 /* System call */ | |
420 | #define EXCCODE_BP 9 /* Breakpoint */ | |
421 | #define EXCCODE_RI 10 /* Reserved instruction exception */ | |
422 | #define EXCCODE_CPU 11 /* Coprocessor unusable */ | |
423 | #define EXCCODE_OV 12 /* Arithmetic overflow */ | |
424 | #define EXCCODE_TR 13 /* Trap instruction */ | |
16d100db JH |
425 | #define EXCCODE_MSAFPE 14 /* MSA floating point exception */ |
426 | #define EXCCODE_FPE 15 /* Floating point exception */ | |
044c9bb8 JH |
427 | #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */ |
428 | #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */ | |
16d100db | 429 | #define EXCCODE_MSADIS 21 /* MSA disabled exception */ |
044c9bb8 | 430 | #define EXCCODE_MDMX 22 /* MDMX unusable exception */ |
16d100db | 431 | #define EXCCODE_WATCH 23 /* Watch address reference */ |
044c9bb8 JH |
432 | #define EXCCODE_MCHECK 24 /* Machine check */ |
433 | #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */ | |
434 | #define EXCCODE_DSPDIS 26 /* DSP disabled exception */ | |
435 | #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */ | |
436 | ||
437 | /* Implementation specific trap codes used by MIPS cores */ | |
438 | #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ | |
16d100db | 439 | |
1da177e4 LT |
440 | /* |
441 | * Bits in the coprocessor 0 config register. | |
442 | */ | |
443 | /* Generic bits. */ | |
444 | #define CONF_CM_CACHABLE_NO_WA 0 | |
445 | #define CONF_CM_CACHABLE_WA 1 | |
446 | #define CONF_CM_UNCACHED 2 | |
447 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | |
448 | #define CONF_CM_CACHABLE_CE 4 | |
449 | #define CONF_CM_CACHABLE_COW 5 | |
450 | #define CONF_CM_CACHABLE_CUW 6 | |
451 | #define CONF_CM_CACHABLE_ACCELERATED 7 | |
452 | #define CONF_CM_CMASK 7 | |
453 | #define CONF_BE (_ULCAST_(1) << 15) | |
454 | ||
455 | /* Bits common to various processors. */ | |
70342287 RB |
456 | #define CONF_CU (_ULCAST_(1) << 3) |
457 | #define CONF_DB (_ULCAST_(1) << 4) | |
458 | #define CONF_IB (_ULCAST_(1) << 5) | |
459 | #define CONF_DC (_ULCAST_(7) << 6) | |
460 | #define CONF_IC (_ULCAST_(7) << 9) | |
1da177e4 LT |
461 | #define CONF_EB (_ULCAST_(1) << 13) |
462 | #define CONF_EM (_ULCAST_(1) << 14) | |
463 | #define CONF_SM (_ULCAST_(1) << 16) | |
464 | #define CONF_SC (_ULCAST_(1) << 17) | |
465 | #define CONF_EW (_ULCAST_(3) << 18) | |
466 | #define CONF_EP (_ULCAST_(15)<< 24) | |
467 | #define CONF_EC (_ULCAST_(7) << 28) | |
468 | #define CONF_CM (_ULCAST_(1) << 31) | |
469 | ||
70342287 | 470 | /* Bits specific to the R4xx0. */ |
1da177e4 LT |
471 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
472 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | |
e20368d5 | 473 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
1da177e4 | 474 | |
70342287 | 475 | /* Bits specific to the R5000. */ |
1da177e4 LT |
476 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
477 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | |
478 | ||
70342287 RB |
479 | /* Bits specific to the RM7000. */ |
480 | #define RM7K_CONF_SE (_ULCAST_(1) << 3) | |
c6ad7b7d MR |
481 | #define RM7K_CONF_TE (_ULCAST_(1) << 12) |
482 | #define RM7K_CONF_CLK (_ULCAST_(1) << 16) | |
483 | #define RM7K_CONF_TC (_ULCAST_(1) << 17) | |
484 | #define RM7K_CONF_SI (_ULCAST_(3) << 20) | |
485 | #define RM7K_CONF_SC (_ULCAST_(1) << 31) | |
ba5187db | 486 | |
70342287 RB |
487 | /* Bits specific to the R10000. */ |
488 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | |
489 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | |
490 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | |
491 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | |
492 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | |
1da177e4 LT |
493 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
494 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | |
495 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | |
496 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | |
497 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | |
498 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | |
499 | ||
70342287 | 500 | /* Bits specific to the VR41xx. */ |
1da177e4 | 501 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
2874fe55 | 502 | #define VR41_CONF_P4K (_ULCAST_(1) << 13) |
4e8ab361 | 503 | #define VR41_CONF_BP (_ULCAST_(1) << 16) |
1da177e4 LT |
504 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
505 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | |
506 | ||
70342287 | 507 | /* Bits specific to the R30xx. */ |
1da177e4 LT |
508 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
509 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | |
510 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | |
511 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | |
512 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | |
513 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | |
514 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | |
515 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | |
516 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | |
517 | ||
518 | /* Bits specific to the TX49. */ | |
519 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | |
520 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | |
521 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | |
522 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | |
523 | ||
70342287 RB |
524 | /* Bits specific to the MIPS32/64 PRA. */ |
525 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) | |
2f6f3136 JH |
526 | #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) |
527 | #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) | |
1da177e4 LT |
528 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
529 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | |
530 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | |
531 | ||
4194318c RB |
532 | /* |
533 | * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. | |
534 | */ | |
70342287 RB |
535 | #define MIPS_CONF1_FP (_ULCAST_(1) << 0) |
536 | #define MIPS_CONF1_EP (_ULCAST_(1) << 1) | |
537 | #define MIPS_CONF1_CA (_ULCAST_(1) << 2) | |
538 | #define MIPS_CONF1_WR (_ULCAST_(1) << 3) | |
539 | #define MIPS_CONF1_PC (_ULCAST_(1) << 4) | |
540 | #define MIPS_CONF1_MD (_ULCAST_(1) << 5) | |
541 | #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) | |
20a8d5d5 PB |
542 | #define MIPS_CONF1_DA_SHF 7 |
543 | #define MIPS_CONF1_DA_SZ 3 | |
70342287 | 544 | #define MIPS_CONF1_DA (_ULCAST_(7) << 7) |
20a8d5d5 PB |
545 | #define MIPS_CONF1_DL_SHF 10 |
546 | #define MIPS_CONF1_DL_SZ 3 | |
4194318c | 547 | #define MIPS_CONF1_DL (_ULCAST_(7) << 10) |
20a8d5d5 PB |
548 | #define MIPS_CONF1_DS_SHF 13 |
549 | #define MIPS_CONF1_DS_SZ 3 | |
4194318c | 550 | #define MIPS_CONF1_DS (_ULCAST_(7) << 13) |
20a8d5d5 PB |
551 | #define MIPS_CONF1_IA_SHF 16 |
552 | #define MIPS_CONF1_IA_SZ 3 | |
4194318c | 553 | #define MIPS_CONF1_IA (_ULCAST_(7) << 16) |
20a8d5d5 PB |
554 | #define MIPS_CONF1_IL_SHF 19 |
555 | #define MIPS_CONF1_IL_SZ 3 | |
4194318c | 556 | #define MIPS_CONF1_IL (_ULCAST_(7) << 19) |
20a8d5d5 PB |
557 | #define MIPS_CONF1_IS_SHF 22 |
558 | #define MIPS_CONF1_IS_SZ 3 | |
4194318c | 559 | #define MIPS_CONF1_IS (_ULCAST_(7) << 22) |
691038ba LY |
560 | #define MIPS_CONF1_TLBS_SHIFT (25) |
561 | #define MIPS_CONF1_TLBS_SIZE (6) | |
562 | #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) | |
4194318c | 563 | |
70342287 RB |
564 | #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) |
565 | #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) | |
566 | #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) | |
4194318c RB |
567 | #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) |
568 | #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) | |
569 | #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) | |
570 | #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) | |
571 | #define MIPS_CONF2_TU (_ULCAST_(7) << 28) | |
572 | ||
70342287 RB |
573 | #define MIPS_CONF3_TL (_ULCAST_(1) << 0) |
574 | #define MIPS_CONF3_SM (_ULCAST_(1) << 1) | |
575 | #define MIPS_CONF3_MT (_ULCAST_(1) << 2) | |
691038ba | 576 | #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) |
70342287 RB |
577 | #define MIPS_CONF3_SP (_ULCAST_(1) << 4) |
578 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) | |
579 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | |
580 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | |
691038ba LY |
581 | #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) |
582 | #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) | |
e50c0a8f | 583 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
ee80f7c7 | 584 | #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) |
b2ab4f08 | 585 | #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) |
a3692020 | 586 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
f8fa4811 | 587 | #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) |
c6213c6c | 588 | #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) |
691038ba LY |
589 | #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) |
590 | #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) | |
591 | #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) | |
1e7decdb | 592 | #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) |
691038ba LY |
593 | #define MIPS_CONF3_PW (_ULCAST_(1) << 24) |
594 | #define MIPS_CONF3_SC (_ULCAST_(1) << 25) | |
595 | #define MIPS_CONF3_BI (_ULCAST_(1) << 26) | |
596 | #define MIPS_CONF3_BP (_ULCAST_(1) << 27) | |
597 | #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) | |
598 | #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) | |
599 | #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) | |
600 | ||
601 | #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) | |
1b362e3e | 602 | #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) |
691038ba | 603 | #define MIPS_CONF4_FTLBSETS_SHIFT (0) |
691038ba LY |
604 | #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) |
605 | #define MIPS_CONF4_FTLBWAYS_SHIFT (4) | |
606 | #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) | |
607 | #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) | |
608 | /* bits 10:8 in FTLB-only configurations */ | |
609 | #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
610 | /* bits 12:8 in VTLB-FTLB only configurations */ | |
611 | #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
1b362e3e DD |
612 | #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) |
613 | #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) | |
691038ba LY |
614 | #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) |
615 | #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) | |
616 | #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) | |
617 | #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) | |
618 | #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) | |
619 | #define MIPS_CONF4_AE (_ULCAST_(1) << 28) | |
620 | #define MIPS_CONF4_IE (_ULCAST_(3) << 29) | |
621 | #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) | |
1b362e3e | 622 | |
2f9ee82c RB |
623 | #define MIPS_CONF5_NF (_ULCAST_(1) << 0) |
624 | #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) | |
e19d5dba | 625 | #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) |
5aed9da1 | 626 | #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) |
23d06e4f | 627 | #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) |
f270d881 | 628 | #define MIPS_CONF5_VP (_ULCAST_(1) << 7) |
5ff04a84 PB |
629 | #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) |
630 | #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) | |
2f9ee82c RB |
631 | #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) |
632 | #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) | |
633 | #define MIPS_CONF5_CV (_ULCAST_(1) << 29) | |
634 | #define MIPS_CONF5_K (_ULCAST_(1) << 30) | |
635 | ||
006a851b | 636 | #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) |
75b5b5e0 LY |
637 | /* proAptiv FTLB on/off bit */ |
638 | #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) | |
cf0a8aa0 MC |
639 | /* FTLB probability bits */ |
640 | #define MIPS_CONF6_FTLBP_SHIFT (16) | |
006a851b | 641 | |
4b3e975e RB |
642 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
643 | ||
9267a30d MSJ |
644 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
645 | ||
02dc6bfb MC |
646 | #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) |
647 | #define MIPS_CONF7_AR (_ULCAST_(1) << 16) | |
20a7f7e5 MC |
648 | /* FTLB probability bits for R6 */ |
649 | #define MIPS_CONF7_FTLBP_SHIFT (18) | |
02dc6bfb | 650 | |
50af501c JH |
651 | /* WatchLo* register definitions */ |
652 | #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0) | |
653 | ||
654 | /* WatchHi* register definitions */ | |
655 | #define MIPS_WATCHHI_M (_ULCAST_(1) << 31) | |
656 | #define MIPS_WATCHHI_G (_ULCAST_(1) << 30) | |
657 | #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28) | |
658 | #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28) | |
659 | #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28) | |
660 | #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28) | |
661 | #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24) | |
662 | #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16) | |
663 | #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3) | |
664 | #define MIPS_WATCHHI_I (_ULCAST_(1) << 2) | |
665 | #define MIPS_WATCHHI_R (_ULCAST_(1) << 1) | |
666 | #define MIPS_WATCHHI_W (_ULCAST_(1) << 0) | |
667 | #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0) | |
668 | ||
e19d5dba PB |
669 | /* MAAR bit definitions */ |
670 | #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) | |
671 | #define MIPS_MAAR_ADDR_SHIFT 12 | |
672 | #define MIPS_MAAR_S (_ULCAST_(1) << 1) | |
673 | #define MIPS_MAAR_V (_ULCAST_(1) << 0) | |
674 | ||
4dd8ee5d PB |
675 | /* CMGCRBase bit definitions */ |
676 | #define MIPS_CMGCRB_BASE 11 | |
677 | #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) | |
678 | ||
4a0156fb SH |
679 | /* |
680 | * Bits in the MIPS32 Memory Segmentation registers. | |
681 | */ | |
682 | #define MIPS_SEGCFG_PA_SHIFT 9 | |
683 | #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) | |
684 | #define MIPS_SEGCFG_AM_SHIFT 4 | |
685 | #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) | |
686 | #define MIPS_SEGCFG_EU_SHIFT 3 | |
687 | #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) | |
688 | #define MIPS_SEGCFG_C_SHIFT 0 | |
689 | #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) | |
690 | ||
691 | #define MIPS_SEGCFG_UUSK _ULCAST_(7) | |
692 | #define MIPS_SEGCFG_USK _ULCAST_(5) | |
693 | #define MIPS_SEGCFG_MUSUK _ULCAST_(4) | |
694 | #define MIPS_SEGCFG_MUSK _ULCAST_(3) | |
695 | #define MIPS_SEGCFG_MSK _ULCAST_(2) | |
696 | #define MIPS_SEGCFG_MK _ULCAST_(1) | |
697 | #define MIPS_SEGCFG_UK _ULCAST_(0) | |
698 | ||
87d08bc9 MC |
699 | #define MIPS_PWFIELD_GDI_SHIFT 24 |
700 | #define MIPS_PWFIELD_GDI_MASK 0x3f000000 | |
701 | #define MIPS_PWFIELD_UDI_SHIFT 18 | |
702 | #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 | |
703 | #define MIPS_PWFIELD_MDI_SHIFT 12 | |
704 | #define MIPS_PWFIELD_MDI_MASK 0x0003f000 | |
705 | #define MIPS_PWFIELD_PTI_SHIFT 6 | |
706 | #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 | |
707 | #define MIPS_PWFIELD_PTEI_SHIFT 0 | |
708 | #define MIPS_PWFIELD_PTEI_MASK 0x0000003f | |
709 | ||
710 | #define MIPS_PWSIZE_GDW_SHIFT 24 | |
711 | #define MIPS_PWSIZE_GDW_MASK 0x3f000000 | |
712 | #define MIPS_PWSIZE_UDW_SHIFT 18 | |
713 | #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 | |
714 | #define MIPS_PWSIZE_MDW_SHIFT 12 | |
715 | #define MIPS_PWSIZE_MDW_MASK 0x0003f000 | |
716 | #define MIPS_PWSIZE_PTW_SHIFT 6 | |
717 | #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 | |
718 | #define MIPS_PWSIZE_PTEW_SHIFT 0 | |
719 | #define MIPS_PWSIZE_PTEW_MASK 0x0000003f | |
720 | ||
721 | #define MIPS_PWCTL_PWEN_SHIFT 31 | |
722 | #define MIPS_PWCTL_PWEN_MASK 0x80000000 | |
723 | #define MIPS_PWCTL_DPH_SHIFT 7 | |
724 | #define MIPS_PWCTL_DPH_MASK 0x00000080 | |
725 | #define MIPS_PWCTL_HUGEPG_SHIFT 6 | |
726 | #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 | |
727 | #define MIPS_PWCTL_PSN_SHIFT 0 | |
728 | #define MIPS_PWCTL_PSN_MASK 0x0000003f | |
729 | ||
9b3274bd JH |
730 | /* CDMMBase register bit definitions */ |
731 | #define MIPS_CDMMBASE_SIZE_SHIFT 0 | |
732 | #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) | |
733 | #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) | |
734 | #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) | |
735 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 | |
736 | #define MIPS_CDMMBASE_ADDR_START 15 | |
737 | ||
e08384ca MR |
738 | /* |
739 | * Bitfields in the TX39 family CP0 Configuration Register 3 | |
740 | */ | |
741 | #define TX39_CONF_ICS_SHIFT 19 | |
742 | #define TX39_CONF_ICS_MASK 0x00380000 | |
743 | #define TX39_CONF_ICS_1KB 0x00000000 | |
744 | #define TX39_CONF_ICS_2KB 0x00080000 | |
745 | #define TX39_CONF_ICS_4KB 0x00100000 | |
746 | #define TX39_CONF_ICS_8KB 0x00180000 | |
747 | #define TX39_CONF_ICS_16KB 0x00200000 | |
748 | ||
749 | #define TX39_CONF_DCS_SHIFT 16 | |
750 | #define TX39_CONF_DCS_MASK 0x00070000 | |
751 | #define TX39_CONF_DCS_1KB 0x00000000 | |
752 | #define TX39_CONF_DCS_2KB 0x00010000 | |
753 | #define TX39_CONF_DCS_4KB 0x00020000 | |
754 | #define TX39_CONF_DCS_8KB 0x00030000 | |
755 | #define TX39_CONF_DCS_16KB 0x00040000 | |
756 | ||
757 | #define TX39_CONF_CWFON 0x00004000 | |
758 | #define TX39_CONF_WBON 0x00002000 | |
759 | #define TX39_CONF_RF_SHIFT 10 | |
760 | #define TX39_CONF_RF_MASK 0x00000c00 | |
761 | #define TX39_CONF_DOZE 0x00000200 | |
762 | #define TX39_CONF_HALT 0x00000100 | |
763 | #define TX39_CONF_LOCK 0x00000080 | |
764 | #define TX39_CONF_ICE 0x00000020 | |
765 | #define TX39_CONF_DCE 0x00000010 | |
766 | #define TX39_CONF_IRSIZE_SHIFT 2 | |
767 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | |
768 | #define TX39_CONF_DRSIZE_SHIFT 0 | |
769 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | |
770 | ||
8d5ded16 JK |
771 | /* |
772 | * Interesting Bits in the R10K CP0 Branch Diagnostic Register | |
773 | */ | |
774 | /* Disable Branch Target Address Cache */ | |
775 | #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) | |
776 | /* Enable Branch Prediction Global History */ | |
777 | #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) | |
778 | /* Disable Branch Return Cache */ | |
779 | #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) | |
fda51906 MR |
780 | |
781 | /* | |
782 | * Coprocessor 1 (FPU) register names | |
783 | */ | |
c491cfa2 MR |
784 | #define CP1_REVISION $0 |
785 | #define CP1_UFR $1 | |
786 | #define CP1_UNFR $4 | |
787 | #define CP1_FCCR $25 | |
788 | #define CP1_FEXR $26 | |
789 | #define CP1_FENR $28 | |
790 | #define CP1_STATUS $31 | |
fda51906 MR |
791 | |
792 | ||
793 | /* | |
794 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | |
795 | */ | |
796 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | |
797 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | |
798 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | |
799 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | |
800 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | |
801 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | |
802 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | |
f1f3b7eb MR |
803 | #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) |
804 | #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) | |
fda51906 MR |
805 | #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) |
806 | ||
c491cfa2 MR |
807 | /* |
808 | * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. | |
809 | */ | |
810 | #define MIPS_FCCR_CONDX_S 0 | |
811 | #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) | |
812 | #define MIPS_FCCR_COND0_S 0 | |
813 | #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) | |
814 | #define MIPS_FCCR_COND1_S 1 | |
815 | #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) | |
816 | #define MIPS_FCCR_COND2_S 2 | |
817 | #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) | |
818 | #define MIPS_FCCR_COND3_S 3 | |
819 | #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) | |
820 | #define MIPS_FCCR_COND4_S 4 | |
821 | #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) | |
822 | #define MIPS_FCCR_COND5_S 5 | |
823 | #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) | |
824 | #define MIPS_FCCR_COND6_S 6 | |
825 | #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) | |
826 | #define MIPS_FCCR_COND7_S 7 | |
827 | #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) | |
828 | ||
829 | /* | |
830 | * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. | |
831 | */ | |
832 | #define MIPS_FENR_FS_S 2 | |
833 | #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) | |
834 | ||
fda51906 MR |
835 | /* |
836 | * FPU Status Register Values | |
837 | */ | |
c491cfa2 MR |
838 | #define FPU_CSR_COND_S 23 /* $fcc0 */ |
839 | #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) | |
840 | ||
841 | #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ | |
842 | #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) | |
843 | ||
844 | #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ | |
845 | #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) | |
846 | #define FPU_CSR_COND1_S 25 /* $fcc1 */ | |
847 | #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) | |
848 | #define FPU_CSR_COND2_S 26 /* $fcc2 */ | |
849 | #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) | |
850 | #define FPU_CSR_COND3_S 27 /* $fcc3 */ | |
851 | #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) | |
852 | #define FPU_CSR_COND4_S 28 /* $fcc4 */ | |
853 | #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) | |
854 | #define FPU_CSR_COND5_S 29 /* $fcc5 */ | |
855 | #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) | |
856 | #define FPU_CSR_COND6_S 30 /* $fcc6 */ | |
857 | #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) | |
858 | #define FPU_CSR_COND7_S 31 /* $fcc7 */ | |
859 | #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) | |
fda51906 MR |
860 | |
861 | /* | |
f1f3b7eb | 862 | * Bits 22:20 of the FPU Status Register will be read as 0, |
fda51906 MR |
863 | * and should be written as zero. |
864 | */ | |
f1f3b7eb MR |
865 | #define FPU_CSR_RSVD (_ULCAST_(7) << 20) |
866 | ||
867 | #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) | |
868 | #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) | |
fda51906 MR |
869 | |
870 | /* | |
871 | * X the exception cause indicator | |
872 | * E the exception enable | |
873 | * S the sticky/flag bit | |
874 | */ | |
875 | #define FPU_CSR_ALL_X 0x0003f000 | |
876 | #define FPU_CSR_UNI_X 0x00020000 | |
877 | #define FPU_CSR_INV_X 0x00010000 | |
878 | #define FPU_CSR_DIV_X 0x00008000 | |
879 | #define FPU_CSR_OVF_X 0x00004000 | |
880 | #define FPU_CSR_UDF_X 0x00002000 | |
881 | #define FPU_CSR_INE_X 0x00001000 | |
882 | ||
883 | #define FPU_CSR_ALL_E 0x00000f80 | |
884 | #define FPU_CSR_INV_E 0x00000800 | |
885 | #define FPU_CSR_DIV_E 0x00000400 | |
886 | #define FPU_CSR_OVF_E 0x00000200 | |
887 | #define FPU_CSR_UDF_E 0x00000100 | |
888 | #define FPU_CSR_INE_E 0x00000080 | |
889 | ||
890 | #define FPU_CSR_ALL_S 0x0000007c | |
891 | #define FPU_CSR_INV_S 0x00000040 | |
892 | #define FPU_CSR_DIV_S 0x00000020 | |
893 | #define FPU_CSR_OVF_S 0x00000010 | |
894 | #define FPU_CSR_UDF_S 0x00000008 | |
895 | #define FPU_CSR_INE_S 0x00000004 | |
896 | ||
897 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ | |
898 | #define FPU_CSR_RM 0x00000003 | |
899 | #define FPU_CSR_RN 0x0 /* nearest */ | |
900 | #define FPU_CSR_RZ 0x1 /* towards zero */ | |
901 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | |
902 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | |
903 | ||
904 | ||
1da177e4 LT |
905 | #ifndef __ASSEMBLY__ |
906 | ||
bfd08baa | 907 | /* |
377cb1b6 | 908 | * Macros for handling the ISA mode bit for MIPS16 and microMIPS. |
bfd08baa | 909 | */ |
377cb1b6 RB |
910 | #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ |
911 | defined(CONFIG_SYS_SUPPORTS_MICROMIPS) | |
bfd08baa SH |
912 | #define get_isa16_mode(x) ((x) & 0x1) |
913 | #define msk_isa16_mode(x) ((x) & ~0x1) | |
914 | #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) | |
377cb1b6 RB |
915 | #else |
916 | #define get_isa16_mode(x) 0 | |
917 | #define msk_isa16_mode(x) (x) | |
918 | #define set_isa16_mode(x) do { } while(0) | |
919 | #endif | |
bfd08baa SH |
920 | |
921 | /* | |
922 | * microMIPS instructions can be 16-bit or 32-bit in length. This | |
923 | * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. | |
924 | */ | |
925 | static inline int mm_insn_16bit(u16 insn) | |
926 | { | |
927 | u16 opcode = (insn >> 10) & 0x7; | |
928 | ||
929 | return (opcode >= 1 && opcode <= 3) ? 1 : 0; | |
930 | } | |
931 | ||
198bb4ce LY |
932 | /* |
933 | * TLB Invalidate Flush | |
934 | */ | |
935 | static inline void tlbinvf(void) | |
936 | { | |
937 | __asm__ __volatile__( | |
938 | ".set push\n\t" | |
939 | ".set noreorder\n\t" | |
940 | ".word 0x42000004\n\t" /* tlbinvf */ | |
941 | ".set pop"); | |
942 | } | |
943 | ||
944 | ||
1da177e4 | 945 | /* |
70342287 | 946 | * Functions to access the R10000 performance counters. These are basically |
1da177e4 LT |
947 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit |
948 | * performance counter number encoded into bits 1 ... 5 of the instruction. | |
949 | * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware | |
950 | * disassembler these will look like an access to sel 0 or 1. | |
951 | */ | |
952 | #define read_r10k_perf_cntr(counter) \ | |
953 | ({ \ | |
954 | unsigned int __res; \ | |
955 | __asm__ __volatile__( \ | |
956 | "mfpc\t%0, %1" \ | |
70342287 | 957 | : "=r" (__res) \ |
1da177e4 LT |
958 | : "i" (counter)); \ |
959 | \ | |
70342287 | 960 | __res; \ |
1da177e4 LT |
961 | }) |
962 | ||
70342287 | 963 | #define write_r10k_perf_cntr(counter,val) \ |
1da177e4 LT |
964 | do { \ |
965 | __asm__ __volatile__( \ | |
966 | "mtpc\t%0, %1" \ | |
967 | : \ | |
968 | : "r" (val), "i" (counter)); \ | |
969 | } while (0) | |
970 | ||
971 | #define read_r10k_perf_event(counter) \ | |
972 | ({ \ | |
973 | unsigned int __res; \ | |
974 | __asm__ __volatile__( \ | |
975 | "mfps\t%0, %1" \ | |
70342287 | 976 | : "=r" (__res) \ |
1da177e4 LT |
977 | : "i" (counter)); \ |
978 | \ | |
70342287 | 979 | __res; \ |
1da177e4 LT |
980 | }) |
981 | ||
70342287 | 982 | #define write_r10k_perf_cntl(counter,val) \ |
1da177e4 LT |
983 | do { \ |
984 | __asm__ __volatile__( \ | |
985 | "mtps\t%0, %1" \ | |
986 | : \ | |
987 | : "r" (val), "i" (counter)); \ | |
988 | } while (0) | |
989 | ||
990 | ||
991 | /* | |
992 | * Macros to access the system control coprocessor | |
993 | */ | |
994 | ||
995 | #define __read_32bit_c0_register(source, sel) \ | |
82eb8f73 | 996 | ({ unsigned int __res; \ |
1da177e4 LT |
997 | if (sel == 0) \ |
998 | __asm__ __volatile__( \ | |
999 | "mfc0\t%0, " #source "\n\t" \ | |
1000 | : "=r" (__res)); \ | |
1001 | else \ | |
1002 | __asm__ __volatile__( \ | |
1003 | ".set\tmips32\n\t" \ | |
1004 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | |
1005 | ".set\tmips0\n\t" \ | |
1006 | : "=r" (__res)); \ | |
1007 | __res; \ | |
1008 | }) | |
1009 | ||
1010 | #define __read_64bit_c0_register(source, sel) \ | |
1011 | ({ unsigned long long __res; \ | |
1012 | if (sizeof(unsigned long) == 4) \ | |
1013 | __res = __read_64bit_c0_split(source, sel); \ | |
1014 | else if (sel == 0) \ | |
1015 | __asm__ __volatile__( \ | |
1016 | ".set\tmips3\n\t" \ | |
1017 | "dmfc0\t%0, " #source "\n\t" \ | |
1018 | ".set\tmips0" \ | |
1019 | : "=r" (__res)); \ | |
1020 | else \ | |
1021 | __asm__ __volatile__( \ | |
1022 | ".set\tmips64\n\t" \ | |
1023 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | |
1024 | ".set\tmips0" \ | |
1025 | : "=r" (__res)); \ | |
1026 | __res; \ | |
1027 | }) | |
1028 | ||
1029 | #define __write_32bit_c0_register(register, sel, value) \ | |
1030 | do { \ | |
1031 | if (sel == 0) \ | |
1032 | __asm__ __volatile__( \ | |
1033 | "mtc0\t%z0, " #register "\n\t" \ | |
0952e290 | 1034 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1035 | else \ |
1036 | __asm__ __volatile__( \ | |
1037 | ".set\tmips32\n\t" \ | |
1038 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | |
1039 | ".set\tmips0" \ | |
0952e290 | 1040 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1041 | } while (0) |
1042 | ||
1043 | #define __write_64bit_c0_register(register, sel, value) \ | |
1044 | do { \ | |
1045 | if (sizeof(unsigned long) == 4) \ | |
1046 | __write_64bit_c0_split(register, sel, value); \ | |
1047 | else if (sel == 0) \ | |
1048 | __asm__ __volatile__( \ | |
1049 | ".set\tmips3\n\t" \ | |
1050 | "dmtc0\t%z0, " #register "\n\t" \ | |
1051 | ".set\tmips0" \ | |
1052 | : : "Jr" (value)); \ | |
1053 | else \ | |
1054 | __asm__ __volatile__( \ | |
1055 | ".set\tmips64\n\t" \ | |
1056 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | |
1057 | ".set\tmips0" \ | |
1058 | : : "Jr" (value)); \ | |
1059 | } while (0) | |
1060 | ||
1061 | #define __read_ulong_c0_register(reg, sel) \ | |
1062 | ((sizeof(unsigned long) == 4) ? \ | |
1063 | (unsigned long) __read_32bit_c0_register(reg, sel) : \ | |
1064 | (unsigned long) __read_64bit_c0_register(reg, sel)) | |
1065 | ||
1066 | #define __write_ulong_c0_register(reg, sel, val) \ | |
1067 | do { \ | |
1068 | if (sizeof(unsigned long) == 4) \ | |
1069 | __write_32bit_c0_register(reg, sel, val); \ | |
1070 | else \ | |
1071 | __write_64bit_c0_register(reg, sel, val); \ | |
1072 | } while (0) | |
1073 | ||
1074 | /* | |
1075 | * On RM7000/RM9000 these are uses to access cop0 set 1 registers | |
1076 | */ | |
1077 | #define __read_32bit_c0_ctrl_register(source) \ | |
82eb8f73 | 1078 | ({ unsigned int __res; \ |
1da177e4 LT |
1079 | __asm__ __volatile__( \ |
1080 | "cfc0\t%0, " #source "\n\t" \ | |
1081 | : "=r" (__res)); \ | |
1082 | __res; \ | |
1083 | }) | |
1084 | ||
1085 | #define __write_32bit_c0_ctrl_register(register, value) \ | |
1086 | do { \ | |
1087 | __asm__ __volatile__( \ | |
1088 | "ctc0\t%z0, " #register "\n\t" \ | |
0952e290 | 1089 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1090 | } while (0) |
1091 | ||
1092 | /* | |
1093 | * These versions are only needed for systems with more than 38 bits of | |
1094 | * physical address space running the 32-bit kernel. That's none atm :-) | |
1095 | */ | |
1096 | #define __read_64bit_c0_split(source, sel) \ | |
1097 | ({ \ | |
87d43dd4 AN |
1098 | unsigned long long __val; \ |
1099 | unsigned long __flags; \ | |
1da177e4 | 1100 | \ |
87d43dd4 | 1101 | local_irq_save(__flags); \ |
1da177e4 LT |
1102 | if (sel == 0) \ |
1103 | __asm__ __volatile__( \ | |
1104 | ".set\tmips64\n\t" \ | |
1105 | "dmfc0\t%M0, " #source "\n\t" \ | |
1106 | "dsll\t%L0, %M0, 32\n\t" \ | |
0b543526 RB |
1107 | "dsra\t%M0, %M0, 32\n\t" \ |
1108 | "dsra\t%L0, %L0, 32\n\t" \ | |
1da177e4 | 1109 | ".set\tmips0" \ |
87d43dd4 | 1110 | : "=r" (__val)); \ |
1da177e4 LT |
1111 | else \ |
1112 | __asm__ __volatile__( \ | |
1113 | ".set\tmips64\n\t" \ | |
1114 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ | |
1115 | "dsll\t%L0, %M0, 32\n\t" \ | |
0b543526 RB |
1116 | "dsra\t%M0, %M0, 32\n\t" \ |
1117 | "dsra\t%L0, %L0, 32\n\t" \ | |
1da177e4 | 1118 | ".set\tmips0" \ |
87d43dd4 AN |
1119 | : "=r" (__val)); \ |
1120 | local_irq_restore(__flags); \ | |
1da177e4 | 1121 | \ |
87d43dd4 | 1122 | __val; \ |
1da177e4 LT |
1123 | }) |
1124 | ||
1125 | #define __write_64bit_c0_split(source, sel, val) \ | |
1126 | do { \ | |
87d43dd4 | 1127 | unsigned long __flags; \ |
1da177e4 | 1128 | \ |
87d43dd4 | 1129 | local_irq_save(__flags); \ |
1da177e4 LT |
1130 | if (sel == 0) \ |
1131 | __asm__ __volatile__( \ | |
1132 | ".set\tmips64\n\t" \ | |
1133 | "dsll\t%L0, %L0, 32\n\t" \ | |
1134 | "dsrl\t%L0, %L0, 32\n\t" \ | |
1135 | "dsll\t%M0, %M0, 32\n\t" \ | |
1136 | "or\t%L0, %L0, %M0\n\t" \ | |
1137 | "dmtc0\t%L0, " #source "\n\t" \ | |
1138 | ".set\tmips0" \ | |
1139 | : : "r" (val)); \ | |
1140 | else \ | |
1141 | __asm__ __volatile__( \ | |
1142 | ".set\tmips64\n\t" \ | |
1143 | "dsll\t%L0, %L0, 32\n\t" \ | |
1144 | "dsrl\t%L0, %L0, 32\n\t" \ | |
1145 | "dsll\t%M0, %M0, 32\n\t" \ | |
1146 | "or\t%L0, %L0, %M0\n\t" \ | |
1147 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | |
1148 | ".set\tmips0" \ | |
1149 | : : "r" (val)); \ | |
87d43dd4 | 1150 | local_irq_restore(__flags); \ |
1da177e4 LT |
1151 | } while (0) |
1152 | ||
23d06e4f SH |
1153 | #define __readx_32bit_c0_register(source) \ |
1154 | ({ \ | |
1155 | unsigned int __res; \ | |
1156 | \ | |
1157 | __asm__ __volatile__( \ | |
1158 | " .set push \n" \ | |
1159 | " .set noat \n" \ | |
1160 | " .set mips32r2 \n" \ | |
1161 | " .insn \n" \ | |
1162 | " # mfhc0 $1, %1 \n" \ | |
1163 | " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ | |
1164 | " move %0, $1 \n" \ | |
1165 | " .set pop \n" \ | |
1166 | : "=r" (__res) \ | |
1167 | : "i" (source)); \ | |
1168 | __res; \ | |
1169 | }) | |
1170 | ||
1171 | #define __writex_32bit_c0_register(register, value) \ | |
1172 | do { \ | |
1173 | __asm__ __volatile__( \ | |
1174 | " .set push \n" \ | |
1175 | " .set noat \n" \ | |
1176 | " .set mips32r2 \n" \ | |
1177 | " move $1, %0 \n" \ | |
1178 | " # mthc0 $1, %1 \n" \ | |
1179 | " .insn \n" \ | |
1180 | " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ | |
1181 | " .set pop \n" \ | |
1182 | : \ | |
1183 | : "r" (value), "i" (register)); \ | |
1184 | } while (0) | |
1185 | ||
1da177e4 LT |
1186 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
1187 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | |
1188 | ||
272bace7 RB |
1189 | #define read_c0_random() __read_32bit_c0_register($1, 0) |
1190 | #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) | |
1191 | ||
1da177e4 LT |
1192 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
1193 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | |
1194 | ||
23d06e4f SH |
1195 | #define readx_c0_entrylo0() __readx_32bit_c0_register(2) |
1196 | #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) | |
1197 | ||
1da177e4 LT |
1198 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) |
1199 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | |
1200 | ||
23d06e4f SH |
1201 | #define readx_c0_entrylo1() __readx_32bit_c0_register(3) |
1202 | #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) | |
1203 | ||
1da177e4 LT |
1204 | #define read_c0_conf() __read_32bit_c0_register($3, 0) |
1205 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | |
1206 | ||
1207 | #define read_c0_context() __read_ulong_c0_register($4, 0) | |
1208 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | |
1209 | ||
a3692020 | 1210 | #define read_c0_userlocal() __read_ulong_c0_register($4, 2) |
70342287 | 1211 | #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) |
a3692020 | 1212 | |
1da177e4 LT |
1213 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
1214 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | |
1215 | ||
9fe2e9d6 | 1216 | #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) |
70342287 | 1217 | #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) |
9fe2e9d6 | 1218 | |
1da177e4 LT |
1219 | #define read_c0_wired() __read_32bit_c0_register($6, 0) |
1220 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | |
1221 | ||
1222 | #define read_c0_info() __read_32bit_c0_register($7, 0) | |
1223 | ||
70342287 | 1224 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ |
1da177e4 LT |
1225 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) |
1226 | ||
15c4f67a RB |
1227 | #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) |
1228 | #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) | |
1229 | ||
1da177e4 LT |
1230 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
1231 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | |
1232 | ||
bdf21b18 PP |
1233 | #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ |
1234 | #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) | |
1235 | ||
1236 | #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ | |
1237 | #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) | |
1238 | ||
1da177e4 LT |
1239 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
1240 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | |
1241 | ||
1242 | #define read_c0_compare() __read_32bit_c0_register($11, 0) | |
1243 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | |
1244 | ||
bdf21b18 PP |
1245 | #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ |
1246 | #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) | |
1247 | ||
1248 | #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ | |
1249 | #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) | |
1250 | ||
1da177e4 | 1251 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
b633648c | 1252 | |
1da177e4 LT |
1253 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
1254 | ||
1255 | #define read_c0_cause() __read_32bit_c0_register($13, 0) | |
1256 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | |
1257 | ||
1258 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | |
1259 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | |
1260 | ||
1261 | #define read_c0_prid() __read_32bit_c0_register($15, 0) | |
1262 | ||
4dd8ee5d PB |
1263 | #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) |
1264 | ||
1da177e4 LT |
1265 | #define read_c0_config() __read_32bit_c0_register($16, 0) |
1266 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | |
1267 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | |
1268 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | |
0efe2761 RB |
1269 | #define read_c0_config4() __read_32bit_c0_register($16, 4) |
1270 | #define read_c0_config5() __read_32bit_c0_register($16, 5) | |
1271 | #define read_c0_config6() __read_32bit_c0_register($16, 6) | |
1272 | #define read_c0_config7() __read_32bit_c0_register($16, 7) | |
1da177e4 LT |
1273 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
1274 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | |
1275 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | |
1276 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | |
0efe2761 RB |
1277 | #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
1278 | #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) | |
1279 | #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) | |
1280 | #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) | |
1da177e4 | 1281 | |
b55b9e27 MC |
1282 | #define read_c0_lladdr() __read_ulong_c0_register($17, 0) |
1283 | #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) | |
e19d5dba PB |
1284 | #define read_c0_maar() __read_ulong_c0_register($17, 1) |
1285 | #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) | |
1286 | #define read_c0_maari() __read_32bit_c0_register($17, 2) | |
1287 | #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) | |
1288 | ||
1da177e4 | 1289 | /* |
25985edc | 1290 | * The WatchLo register. There may be up to 8 of them. |
1da177e4 LT |
1291 | */ |
1292 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | |
1293 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | |
1294 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | |
1295 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | |
1296 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | |
1297 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | |
1298 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | |
1299 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | |
1300 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | |
1301 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | |
1302 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | |
1303 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | |
1304 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | |
1305 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | |
1306 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | |
1307 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | |
1308 | ||
1309 | /* | |
25985edc | 1310 | * The WatchHi register. There may be up to 8 of them. |
1da177e4 LT |
1311 | */ |
1312 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | |
1313 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | |
1314 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | |
1315 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | |
1316 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | |
1317 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | |
1318 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | |
1319 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | |
1320 | ||
1321 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | |
1322 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | |
1323 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | |
1324 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | |
1325 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | |
1326 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | |
1327 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | |
1328 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | |
1329 | ||
1330 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | |
1331 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | |
1332 | ||
1333 | #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) | |
1334 | #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) | |
1335 | ||
1336 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | |
70342287 | 1337 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) |
1da177e4 | 1338 | |
1da177e4 LT |
1339 | #define read_c0_diag() __read_32bit_c0_register($22, 0) |
1340 | #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) | |
1341 | ||
8d5ded16 JK |
1342 | /* R10K CP0 Branch Diagnostic register is 64bits wide */ |
1343 | #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) | |
1344 | #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) | |
1345 | ||
1da177e4 LT |
1346 | #define read_c0_diag1() __read_32bit_c0_register($22, 1) |
1347 | #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) | |
1348 | ||
1349 | #define read_c0_diag2() __read_32bit_c0_register($22, 2) | |
1350 | #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) | |
1351 | ||
1352 | #define read_c0_diag3() __read_32bit_c0_register($22, 3) | |
1353 | #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) | |
1354 | ||
1355 | #define read_c0_diag4() __read_32bit_c0_register($22, 4) | |
1356 | #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) | |
1357 | ||
1358 | #define read_c0_diag5() __read_32bit_c0_register($22, 5) | |
1359 | #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) | |
1360 | ||
1361 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | |
1362 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | |
1363 | ||
1364 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | |
1365 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | |
1366 | ||
1367 | /* | |
1368 | * MIPS32 / MIPS64 performance counters | |
1369 | */ | |
1370 | #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) | |
70342287 | 1371 | #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) |
1da177e4 | 1372 | #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) |
70342287 | 1373 | #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) |
4d36f59d DD |
1374 | #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) |
1375 | #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) | |
1da177e4 | 1376 | #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) |
70342287 | 1377 | #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) |
1da177e4 | 1378 | #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) |
70342287 | 1379 | #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) |
4d36f59d DD |
1380 | #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) |
1381 | #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) | |
1da177e4 | 1382 | #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) |
70342287 | 1383 | #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) |
1da177e4 | 1384 | #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) |
70342287 | 1385 | #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) |
4d36f59d DD |
1386 | #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) |
1387 | #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) | |
1da177e4 | 1388 | #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) |
70342287 | 1389 | #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) |
1da177e4 | 1390 | #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) |
70342287 | 1391 | #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) |
4d36f59d DD |
1392 | #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) |
1393 | #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) | |
1da177e4 | 1394 | |
1da177e4 LT |
1395 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) |
1396 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | |
1397 | ||
1398 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | |
70342287 | 1399 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) |
1da177e4 LT |
1400 | |
1401 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | |
1402 | ||
1403 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | |
70342287 | 1404 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) |
1da177e4 LT |
1405 | |
1406 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | |
1407 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | |
1408 | ||
41c594ab RB |
1409 | #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) |
1410 | #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) | |
1411 | ||
af231172 KC |
1412 | #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) |
1413 | #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) | |
1414 | ||
1415 | #define read_c0_staglo() __read_32bit_c0_register($28, 4) | |
1416 | #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) | |
1417 | ||
1da177e4 LT |
1418 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
1419 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | |
1420 | ||
1421 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | |
1422 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | |
1423 | ||
7a0fc58c | 1424 | /* MIPSR2 */ |
21a151d8 | 1425 | #define read_c0_hwrena() __read_32bit_c0_register($7, 0) |
7a0fc58c RB |
1426 | #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) |
1427 | ||
1428 | #define read_c0_intctl() __read_32bit_c0_register($12, 1) | |
1429 | #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) | |
1430 | ||
1431 | #define read_c0_srsctl() __read_32bit_c0_register($12, 2) | |
1432 | #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) | |
1433 | ||
1434 | #define read_c0_srsmap() __read_32bit_c0_register($12, 3) | |
1435 | #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) | |
1436 | ||
21a151d8 | 1437 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) |
7a0fc58c RB |
1438 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) |
1439 | ||
9b3274bd JH |
1440 | #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) |
1441 | #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) | |
1442 | ||
4a0156fb SH |
1443 | /* MIPSR3 */ |
1444 | #define read_c0_segctl0() __read_32bit_c0_register($5, 2) | |
1445 | #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) | |
1446 | ||
1447 | #define read_c0_segctl1() __read_32bit_c0_register($5, 3) | |
1448 | #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) | |
1449 | ||
1450 | #define read_c0_segctl2() __read_32bit_c0_register($5, 4) | |
1451 | #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) | |
ed918c2d | 1452 | |
87d08bc9 MC |
1453 | /* Hardware Page Table Walker */ |
1454 | #define read_c0_pwbase() __read_ulong_c0_register($5, 5) | |
1455 | #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) | |
1456 | ||
1457 | #define read_c0_pwfield() __read_ulong_c0_register($5, 6) | |
1458 | #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) | |
1459 | ||
1460 | #define read_c0_pwsize() __read_ulong_c0_register($5, 7) | |
1461 | #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) | |
1462 | ||
1463 | #define read_c0_pwctl() __read_32bit_c0_register($6, 6) | |
1464 | #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) | |
1465 | ||
ed918c2d DD |
1466 | /* Cavium OCTEON (cnMIPS) */ |
1467 | #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) | |
1468 | #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) | |
1469 | ||
1470 | #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) | |
1471 | #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) | |
1472 | ||
1473 | #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) | |
70342287 | 1474 | #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) |
ed918c2d | 1475 | /* |
70342287 | 1476 | * The cacheerr registers are not standardized. On OCTEON, they are |
ed918c2d DD |
1477 | * 64 bits wide. |
1478 | */ | |
1479 | #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) | |
1480 | #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) | |
1481 | ||
1482 | #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) | |
1483 | #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) | |
1484 | ||
af231172 KC |
1485 | /* BMIPS3300 */ |
1486 | #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) | |
1487 | #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) | |
1488 | ||
1489 | #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) | |
1490 | #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) | |
1491 | ||
1492 | #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) | |
1493 | #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) | |
1494 | ||
020232f1 | 1495 | /* BMIPS43xx */ |
af231172 KC |
1496 | #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) |
1497 | #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) | |
1498 | ||
1499 | #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) | |
1500 | #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) | |
1501 | ||
1502 | #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) | |
1503 | #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) | |
1504 | ||
1505 | #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) | |
1506 | #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) | |
1507 | ||
1508 | #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) | |
1509 | #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) | |
1510 | ||
1511 | /* BMIPS5000 */ | |
1512 | #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) | |
1513 | #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) | |
1514 | ||
1515 | #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) | |
1516 | #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) | |
1517 | ||
1518 | #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) | |
1519 | #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) | |
1520 | ||
1521 | #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) | |
1522 | #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) | |
1523 | ||
1524 | #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) | |
1525 | #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) | |
1526 | ||
1527 | #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) | |
1528 | #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) | |
1529 | ||
1da177e4 LT |
1530 | /* |
1531 | * Macros to access the floating point coprocessor control registers | |
1532 | */ | |
842dfc11 | 1533 | #define _read_32bit_cp1_register(source, gas_hardfloat) \ |
b9688310 | 1534 | ({ \ |
c46a2f01 | 1535 | unsigned int __res; \ |
b9688310 SH |
1536 | \ |
1537 | __asm__ __volatile__( \ | |
1538 | " .set push \n" \ | |
1539 | " .set reorder \n" \ | |
1540 | " # gas fails to assemble cfc1 for some archs, \n" \ | |
1541 | " # like Octeon. \n" \ | |
1542 | " .set mips1 \n" \ | |
842dfc11 | 1543 | " "STR(gas_hardfloat)" \n" \ |
b9688310 SH |
1544 | " cfc1 %0,"STR(source)" \n" \ |
1545 | " .set pop \n" \ | |
1546 | : "=r" (__res)); \ | |
1547 | __res; \ | |
1548 | }) | |
1da177e4 | 1549 | |
5e32033e JH |
1550 | #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ |
1551 | do { \ | |
1552 | __asm__ __volatile__( \ | |
1553 | " .set push \n" \ | |
1554 | " .set reorder \n" \ | |
1555 | " "STR(gas_hardfloat)" \n" \ | |
1556 | " ctc1 %0,"STR(dest)" \n" \ | |
1557 | " .set pop \n" \ | |
1558 | : : "r" (val)); \ | |
1559 | } while (0) | |
1560 | ||
842dfc11 ML |
1561 | #ifdef GAS_HAS_SET_HARDFLOAT |
1562 | #define read_32bit_cp1_register(source) \ | |
1563 | _read_32bit_cp1_register(source, .set hardfloat) | |
5e32033e JH |
1564 | #define write_32bit_cp1_register(dest, val) \ |
1565 | _write_32bit_cp1_register(dest, val, .set hardfloat) | |
842dfc11 ML |
1566 | #else |
1567 | #define read_32bit_cp1_register(source) \ | |
1568 | _read_32bit_cp1_register(source, ) | |
5e32033e JH |
1569 | #define write_32bit_cp1_register(dest, val) \ |
1570 | _write_32bit_cp1_register(dest, val, ) | |
842dfc11 ML |
1571 | #endif |
1572 | ||
32a7ede6 | 1573 | #ifdef HAVE_AS_DSP |
e50c0a8f RB |
1574 | #define rddsp(mask) \ |
1575 | ({ \ | |
32a7ede6 | 1576 | unsigned int __dspctl; \ |
e50c0a8f RB |
1577 | \ |
1578 | __asm__ __volatile__( \ | |
63c2b681 FF |
1579 | " .set push \n" \ |
1580 | " .set dsp \n" \ | |
32a7ede6 | 1581 | " rddsp %0, %x1 \n" \ |
63c2b681 | 1582 | " .set pop \n" \ |
32a7ede6 | 1583 | : "=r" (__dspctl) \ |
e50c0a8f | 1584 | : "i" (mask)); \ |
32a7ede6 | 1585 | __dspctl; \ |
e50c0a8f RB |
1586 | }) |
1587 | ||
1588 | #define wrdsp(val, mask) \ | |
1589 | do { \ | |
e50c0a8f | 1590 | __asm__ __volatile__( \ |
63c2b681 FF |
1591 | " .set push \n" \ |
1592 | " .set dsp \n" \ | |
32a7ede6 | 1593 | " wrdsp %0, %x1 \n" \ |
63c2b681 | 1594 | " .set pop \n" \ |
70342287 | 1595 | : \ |
e50c0a8f | 1596 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
1597 | } while (0) |
1598 | ||
63c2b681 FF |
1599 | #define mflo0() \ |
1600 | ({ \ | |
1601 | long mflo0; \ | |
1602 | __asm__( \ | |
1603 | " .set push \n" \ | |
1604 | " .set dsp \n" \ | |
1605 | " mflo %0, $ac0 \n" \ | |
1606 | " .set pop \n" \ | |
1607 | : "=r" (mflo0)); \ | |
1608 | mflo0; \ | |
1609 | }) | |
1610 | ||
1611 | #define mflo1() \ | |
1612 | ({ \ | |
1613 | long mflo1; \ | |
1614 | __asm__( \ | |
1615 | " .set push \n" \ | |
1616 | " .set dsp \n" \ | |
1617 | " mflo %0, $ac1 \n" \ | |
1618 | " .set pop \n" \ | |
1619 | : "=r" (mflo1)); \ | |
1620 | mflo1; \ | |
1621 | }) | |
1622 | ||
1623 | #define mflo2() \ | |
1624 | ({ \ | |
1625 | long mflo2; \ | |
1626 | __asm__( \ | |
1627 | " .set push \n" \ | |
1628 | " .set dsp \n" \ | |
1629 | " mflo %0, $ac2 \n" \ | |
1630 | " .set pop \n" \ | |
1631 | : "=r" (mflo2)); \ | |
1632 | mflo2; \ | |
1633 | }) | |
1634 | ||
1635 | #define mflo3() \ | |
1636 | ({ \ | |
1637 | long mflo3; \ | |
1638 | __asm__( \ | |
1639 | " .set push \n" \ | |
1640 | " .set dsp \n" \ | |
1641 | " mflo %0, $ac3 \n" \ | |
1642 | " .set pop \n" \ | |
1643 | : "=r" (mflo3)); \ | |
1644 | mflo3; \ | |
1645 | }) | |
1646 | ||
1647 | #define mfhi0() \ | |
1648 | ({ \ | |
1649 | long mfhi0; \ | |
1650 | __asm__( \ | |
1651 | " .set push \n" \ | |
1652 | " .set dsp \n" \ | |
1653 | " mfhi %0, $ac0 \n" \ | |
1654 | " .set pop \n" \ | |
1655 | : "=r" (mfhi0)); \ | |
1656 | mfhi0; \ | |
1657 | }) | |
1658 | ||
1659 | #define mfhi1() \ | |
1660 | ({ \ | |
1661 | long mfhi1; \ | |
1662 | __asm__( \ | |
1663 | " .set push \n" \ | |
1664 | " .set dsp \n" \ | |
1665 | " mfhi %0, $ac1 \n" \ | |
1666 | " .set pop \n" \ | |
1667 | : "=r" (mfhi1)); \ | |
1668 | mfhi1; \ | |
1669 | }) | |
1670 | ||
1671 | #define mfhi2() \ | |
1672 | ({ \ | |
1673 | long mfhi2; \ | |
1674 | __asm__( \ | |
1675 | " .set push \n" \ | |
1676 | " .set dsp \n" \ | |
1677 | " mfhi %0, $ac2 \n" \ | |
1678 | " .set pop \n" \ | |
1679 | : "=r" (mfhi2)); \ | |
1680 | mfhi2; \ | |
1681 | }) | |
1682 | ||
1683 | #define mfhi3() \ | |
1684 | ({ \ | |
1685 | long mfhi3; \ | |
1686 | __asm__( \ | |
1687 | " .set push \n" \ | |
1688 | " .set dsp \n" \ | |
1689 | " mfhi %0, $ac3 \n" \ | |
1690 | " .set pop \n" \ | |
1691 | : "=r" (mfhi3)); \ | |
1692 | mfhi3; \ | |
1693 | }) | |
1694 | ||
1695 | ||
1696 | #define mtlo0(x) \ | |
1697 | ({ \ | |
1698 | __asm__( \ | |
1699 | " .set push \n" \ | |
1700 | " .set dsp \n" \ | |
1701 | " mtlo %0, $ac0 \n" \ | |
1702 | " .set pop \n" \ | |
1703 | : \ | |
1704 | : "r" (x)); \ | |
1705 | }) | |
1706 | ||
1707 | #define mtlo1(x) \ | |
1708 | ({ \ | |
1709 | __asm__( \ | |
1710 | " .set push \n" \ | |
1711 | " .set dsp \n" \ | |
1712 | " mtlo %0, $ac1 \n" \ | |
1713 | " .set pop \n" \ | |
1714 | : \ | |
1715 | : "r" (x)); \ | |
1716 | }) | |
1717 | ||
1718 | #define mtlo2(x) \ | |
1719 | ({ \ | |
1720 | __asm__( \ | |
1721 | " .set push \n" \ | |
1722 | " .set dsp \n" \ | |
1723 | " mtlo %0, $ac2 \n" \ | |
1724 | " .set pop \n" \ | |
1725 | : \ | |
1726 | : "r" (x)); \ | |
1727 | }) | |
1728 | ||
1729 | #define mtlo3(x) \ | |
1730 | ({ \ | |
1731 | __asm__( \ | |
1732 | " .set push \n" \ | |
1733 | " .set dsp \n" \ | |
1734 | " mtlo %0, $ac3 \n" \ | |
1735 | " .set pop \n" \ | |
1736 | : \ | |
1737 | : "r" (x)); \ | |
1738 | }) | |
1739 | ||
1740 | #define mthi0(x) \ | |
1741 | ({ \ | |
1742 | __asm__( \ | |
1743 | " .set push \n" \ | |
1744 | " .set dsp \n" \ | |
1745 | " mthi %0, $ac0 \n" \ | |
1746 | " .set pop \n" \ | |
1747 | : \ | |
1748 | : "r" (x)); \ | |
1749 | }) | |
1750 | ||
1751 | #define mthi1(x) \ | |
1752 | ({ \ | |
1753 | __asm__( \ | |
1754 | " .set push \n" \ | |
1755 | " .set dsp \n" \ | |
1756 | " mthi %0, $ac1 \n" \ | |
1757 | " .set pop \n" \ | |
1758 | : \ | |
1759 | : "r" (x)); \ | |
1760 | }) | |
1761 | ||
1762 | #define mthi2(x) \ | |
1763 | ({ \ | |
1764 | __asm__( \ | |
1765 | " .set push \n" \ | |
1766 | " .set dsp \n" \ | |
1767 | " mthi %0, $ac2 \n" \ | |
1768 | " .set pop \n" \ | |
1769 | : \ | |
1770 | : "r" (x)); \ | |
1771 | }) | |
1772 | ||
1773 | #define mthi3(x) \ | |
1774 | ({ \ | |
1775 | __asm__( \ | |
1776 | " .set push \n" \ | |
1777 | " .set dsp \n" \ | |
1778 | " mthi %0, $ac3 \n" \ | |
1779 | " .set pop \n" \ | |
1780 | : \ | |
1781 | : "r" (x)); \ | |
1782 | }) | |
e50c0a8f RB |
1783 | |
1784 | #else | |
1785 | ||
d0c1b478 SH |
1786 | #ifdef CONFIG_CPU_MICROMIPS |
1787 | #define rddsp(mask) \ | |
e50c0a8f | 1788 | ({ \ |
d0c1b478 | 1789 | unsigned int __res; \ |
e50c0a8f RB |
1790 | \ |
1791 | __asm__ __volatile__( \ | |
e50c0a8f RB |
1792 | " .set push \n" \ |
1793 | " .set noat \n" \ | |
d0c1b478 SH |
1794 | " # rddsp $1, %x1 \n" \ |
1795 | " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ | |
1796 | " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ | |
1797 | " move %0, $1 \n" \ | |
e50c0a8f | 1798 | " .set pop \n" \ |
d0c1b478 SH |
1799 | : "=r" (__res) \ |
1800 | : "i" (mask)); \ | |
1801 | __res; \ | |
1802 | }) | |
e50c0a8f | 1803 | |
d0c1b478 | 1804 | #define wrdsp(val, mask) \ |
e50c0a8f RB |
1805 | do { \ |
1806 | __asm__ __volatile__( \ | |
1807 | " .set push \n" \ | |
1808 | " .set noat \n" \ | |
1809 | " move $1, %0 \n" \ | |
d0c1b478 SH |
1810 | " # wrdsp $1, %x1 \n" \ |
1811 | " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ | |
1812 | " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ | |
e50c0a8f RB |
1813 | " .set pop \n" \ |
1814 | : \ | |
d0c1b478 | 1815 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
1816 | } while (0) |
1817 | ||
d0c1b478 SH |
1818 | #define _umips_dsp_mfxxx(ins) \ |
1819 | ({ \ | |
1820 | unsigned long __treg; \ | |
1821 | \ | |
e50c0a8f RB |
1822 | __asm__ __volatile__( \ |
1823 | " .set push \n" \ | |
1824 | " .set noat \n" \ | |
d0c1b478 SH |
1825 | " .hword 0x0001 \n" \ |
1826 | " .hword %x1 \n" \ | |
1827 | " move %0, $1 \n" \ | |
e50c0a8f | 1828 | " .set pop \n" \ |
d0c1b478 SH |
1829 | : "=r" (__treg) \ |
1830 | : "i" (ins)); \ | |
1831 | __treg; \ | |
1832 | }) | |
e50c0a8f | 1833 | |
d0c1b478 | 1834 | #define _umips_dsp_mtxxx(val, ins) \ |
e50c0a8f RB |
1835 | do { \ |
1836 | __asm__ __volatile__( \ | |
1837 | " .set push \n" \ | |
1838 | " .set noat \n" \ | |
1839 | " move $1, %0 \n" \ | |
d0c1b478 SH |
1840 | " .hword 0x0001 \n" \ |
1841 | " .hword %x1 \n" \ | |
e50c0a8f RB |
1842 | " .set pop \n" \ |
1843 | : \ | |
d0c1b478 | 1844 | : "r" (val), "i" (ins)); \ |
e50c0a8f RB |
1845 | } while (0) |
1846 | ||
d0c1b478 SH |
1847 | #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) |
1848 | #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) | |
1849 | ||
1850 | #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) | |
1851 | #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) | |
1852 | ||
1853 | #define mflo0() _umips_dsp_mflo(0) | |
1854 | #define mflo1() _umips_dsp_mflo(1) | |
1855 | #define mflo2() _umips_dsp_mflo(2) | |
1856 | #define mflo3() _umips_dsp_mflo(3) | |
1857 | ||
1858 | #define mfhi0() _umips_dsp_mfhi(0) | |
1859 | #define mfhi1() _umips_dsp_mfhi(1) | |
1860 | #define mfhi2() _umips_dsp_mfhi(2) | |
1861 | #define mfhi3() _umips_dsp_mfhi(3) | |
1862 | ||
1863 | #define mtlo0(x) _umips_dsp_mtlo(x, 0) | |
1864 | #define mtlo1(x) _umips_dsp_mtlo(x, 1) | |
1865 | #define mtlo2(x) _umips_dsp_mtlo(x, 2) | |
1866 | #define mtlo3(x) _umips_dsp_mtlo(x, 3) | |
1867 | ||
1868 | #define mthi0(x) _umips_dsp_mthi(x, 0) | |
1869 | #define mthi1(x) _umips_dsp_mthi(x, 1) | |
1870 | #define mthi2(x) _umips_dsp_mthi(x, 2) | |
1871 | #define mthi3(x) _umips_dsp_mthi(x, 3) | |
1872 | ||
1873 | #else /* !CONFIG_CPU_MICROMIPS */ | |
32a7ede6 SH |
1874 | #define rddsp(mask) \ |
1875 | ({ \ | |
1876 | unsigned int __res; \ | |
1877 | \ | |
e50c0a8f | 1878 | __asm__ __volatile__( \ |
32a7ede6 SH |
1879 | " .set push \n" \ |
1880 | " .set noat \n" \ | |
1881 | " # rddsp $1, %x1 \n" \ | |
1882 | " .word 0x7c000cb8 | (%x1 << 16) \n" \ | |
1883 | " move %0, $1 \n" \ | |
1884 | " .set pop \n" \ | |
1885 | : "=r" (__res) \ | |
1886 | : "i" (mask)); \ | |
1887 | __res; \ | |
1888 | }) | |
e50c0a8f | 1889 | |
32a7ede6 | 1890 | #define wrdsp(val, mask) \ |
e50c0a8f RB |
1891 | do { \ |
1892 | __asm__ __volatile__( \ | |
1893 | " .set push \n" \ | |
1894 | " .set noat \n" \ | |
1895 | " move $1, %0 \n" \ | |
32a7ede6 SH |
1896 | " # wrdsp $1, %x1 \n" \ |
1897 | " .word 0x7c2004f8 | (%x1 << 11) \n" \ | |
e50c0a8f | 1898 | " .set pop \n" \ |
32a7ede6 SH |
1899 | : \ |
1900 | : "r" (val), "i" (mask)); \ | |
e50c0a8f RB |
1901 | } while (0) |
1902 | ||
4cb764b4 | 1903 | #define _dsp_mfxxx(ins) \ |
e50c0a8f RB |
1904 | ({ \ |
1905 | unsigned long __treg; \ | |
1906 | \ | |
e50c0a8f RB |
1907 | __asm__ __volatile__( \ |
1908 | " .set push \n" \ | |
1909 | " .set noat \n" \ | |
4cb764b4 SH |
1910 | " .word (0x00000810 | %1) \n" \ |
1911 | " move %0, $1 \n" \ | |
e50c0a8f | 1912 | " .set pop \n" \ |
4cb764b4 SH |
1913 | : "=r" (__treg) \ |
1914 | : "i" (ins)); \ | |
1915 | __treg; \ | |
1916 | }) | |
e50c0a8f | 1917 | |
4cb764b4 | 1918 | #define _dsp_mtxxx(val, ins) \ |
e50c0a8f RB |
1919 | do { \ |
1920 | __asm__ __volatile__( \ | |
1921 | " .set push \n" \ | |
1922 | " .set noat \n" \ | |
1923 | " move $1, %0 \n" \ | |
4cb764b4 | 1924 | " .word (0x00200011 | %1) \n" \ |
e50c0a8f RB |
1925 | " .set pop \n" \ |
1926 | : \ | |
4cb764b4 | 1927 | : "r" (val), "i" (ins)); \ |
e50c0a8f RB |
1928 | } while (0) |
1929 | ||
4cb764b4 SH |
1930 | #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) |
1931 | #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) | |
e50c0a8f | 1932 | |
4cb764b4 SH |
1933 | #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) |
1934 | #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) | |
e50c0a8f | 1935 | |
4cb764b4 SH |
1936 | #define mflo0() _dsp_mflo(0) |
1937 | #define mflo1() _dsp_mflo(1) | |
1938 | #define mflo2() _dsp_mflo(2) | |
1939 | #define mflo3() _dsp_mflo(3) | |
e50c0a8f | 1940 | |
4cb764b4 SH |
1941 | #define mfhi0() _dsp_mfhi(0) |
1942 | #define mfhi1() _dsp_mfhi(1) | |
1943 | #define mfhi2() _dsp_mfhi(2) | |
1944 | #define mfhi3() _dsp_mfhi(3) | |
e50c0a8f | 1945 | |
4cb764b4 SH |
1946 | #define mtlo0(x) _dsp_mtlo(x, 0) |
1947 | #define mtlo1(x) _dsp_mtlo(x, 1) | |
1948 | #define mtlo2(x) _dsp_mtlo(x, 2) | |
1949 | #define mtlo3(x) _dsp_mtlo(x, 3) | |
e50c0a8f | 1950 | |
4cb764b4 SH |
1951 | #define mthi0(x) _dsp_mthi(x, 0) |
1952 | #define mthi1(x) _dsp_mthi(x, 1) | |
1953 | #define mthi2(x) _dsp_mthi(x, 2) | |
1954 | #define mthi3(x) _dsp_mthi(x, 3) | |
e50c0a8f | 1955 | |
d0c1b478 | 1956 | #endif /* CONFIG_CPU_MICROMIPS */ |
e50c0a8f RB |
1957 | #endif |
1958 | ||
1da177e4 LT |
1959 | /* |
1960 | * TLB operations. | |
1961 | * | |
1962 | * It is responsibility of the caller to take care of any TLB hazards. | |
1963 | */ | |
1964 | static inline void tlb_probe(void) | |
1965 | { | |
1966 | __asm__ __volatile__( | |
1967 | ".set noreorder\n\t" | |
1968 | "tlbp\n\t" | |
1969 | ".set reorder"); | |
1970 | } | |
1971 | ||
1972 | static inline void tlb_read(void) | |
1973 | { | |
9267a30d MSJ |
1974 | #if MIPS34K_MISSED_ITLB_WAR |
1975 | int res = 0; | |
1976 | ||
1977 | __asm__ __volatile__( | |
1978 | " .set push \n" | |
1979 | " .set noreorder \n" | |
1980 | " .set noat \n" | |
1981 | " .set mips32r2 \n" | |
1982 | " .word 0x41610001 # dvpe $1 \n" | |
1983 | " move %0, $1 \n" | |
1984 | " ehb \n" | |
1985 | " .set pop \n" | |
1986 | : "=r" (res)); | |
1987 | ||
1988 | instruction_hazard(); | |
1989 | #endif | |
1990 | ||
1da177e4 LT |
1991 | __asm__ __volatile__( |
1992 | ".set noreorder\n\t" | |
1993 | "tlbr\n\t" | |
1994 | ".set reorder"); | |
9267a30d MSJ |
1995 | |
1996 | #if MIPS34K_MISSED_ITLB_WAR | |
1997 | if ((res & _ULCAST_(1))) | |
1998 | __asm__ __volatile__( | |
1999 | " .set push \n" | |
2000 | " .set noreorder \n" | |
2001 | " .set noat \n" | |
2002 | " .set mips32r2 \n" | |
2003 | " .word 0x41600021 # evpe \n" | |
2004 | " ehb \n" | |
2005 | " .set pop \n"); | |
2006 | #endif | |
1da177e4 LT |
2007 | } |
2008 | ||
2009 | static inline void tlb_write_indexed(void) | |
2010 | { | |
2011 | __asm__ __volatile__( | |
2012 | ".set noreorder\n\t" | |
2013 | "tlbwi\n\t" | |
2014 | ".set reorder"); | |
2015 | } | |
2016 | ||
2017 | static inline void tlb_write_random(void) | |
2018 | { | |
2019 | __asm__ __volatile__( | |
2020 | ".set noreorder\n\t" | |
2021 | "tlbwr\n\t" | |
2022 | ".set reorder"); | |
2023 | } | |
2024 | ||
2025 | /* | |
2026 | * Manipulate bits in a c0 register. | |
2027 | */ | |
2028 | #define __BUILD_SET_C0(name) \ | |
2029 | static inline unsigned int \ | |
2030 | set_c0_##name(unsigned int set) \ | |
2031 | { \ | |
89e18eb3 | 2032 | unsigned int res, new; \ |
1da177e4 LT |
2033 | \ |
2034 | res = read_c0_##name(); \ | |
89e18eb3 RB |
2035 | new = res | set; \ |
2036 | write_c0_##name(new); \ | |
1da177e4 LT |
2037 | \ |
2038 | return res; \ | |
2039 | } \ | |
2040 | \ | |
2041 | static inline unsigned int \ | |
2042 | clear_c0_##name(unsigned int clear) \ | |
2043 | { \ | |
89e18eb3 | 2044 | unsigned int res, new; \ |
1da177e4 LT |
2045 | \ |
2046 | res = read_c0_##name(); \ | |
89e18eb3 RB |
2047 | new = res & ~clear; \ |
2048 | write_c0_##name(new); \ | |
1da177e4 LT |
2049 | \ |
2050 | return res; \ | |
2051 | } \ | |
2052 | \ | |
2053 | static inline unsigned int \ | |
89e18eb3 | 2054 | change_c0_##name(unsigned int change, unsigned int val) \ |
1da177e4 | 2055 | { \ |
89e18eb3 | 2056 | unsigned int res, new; \ |
1da177e4 LT |
2057 | \ |
2058 | res = read_c0_##name(); \ | |
89e18eb3 RB |
2059 | new = res & ~change; \ |
2060 | new |= (val & change); \ | |
2061 | write_c0_##name(new); \ | |
1da177e4 LT |
2062 | \ |
2063 | return res; \ | |
2064 | } | |
2065 | ||
2066 | __BUILD_SET_C0(status) | |
2067 | __BUILD_SET_C0(cause) | |
2068 | __BUILD_SET_C0(config) | |
7f65afb9 | 2069 | __BUILD_SET_C0(config5) |
1da177e4 | 2070 | __BUILD_SET_C0(intcontrol) |
7a0fc58c RB |
2071 | __BUILD_SET_C0(intctl) |
2072 | __BUILD_SET_C0(srsmap) | |
a5770df0 | 2073 | __BUILD_SET_C0(pagegrain) |
020232f1 KC |
2074 | __BUILD_SET_C0(brcm_config_0) |
2075 | __BUILD_SET_C0(brcm_bus_pll) | |
2076 | __BUILD_SET_C0(brcm_reset) | |
2077 | __BUILD_SET_C0(brcm_cmt_intr) | |
2078 | __BUILD_SET_C0(brcm_cmt_ctrl) | |
2079 | __BUILD_SET_C0(brcm_config) | |
2080 | __BUILD_SET_C0(brcm_mode) | |
1da177e4 | 2081 | |
45b585c8 DD |
2082 | /* |
2083 | * Return low 10 bits of ebase. | |
2084 | * Note that under KVM (MIPSVZ) this returns vcpu id. | |
2085 | */ | |
2086 | static inline unsigned int get_ebase_cpunum(void) | |
2087 | { | |
2088 | return read_c0_ebase() & 0x3ff; | |
2089 | } | |
2090 | ||
1da177e4 LT |
2091 | #endif /* !__ASSEMBLY__ */ |
2092 | ||
2093 | #endif /* _ASM_MIPSREGS_H */ |