[deliverable/linux.git] / arch / mips / include / asm / mmu_context.h

/*
 * Switch a MMU context.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
 */
#ifndef _ASM_MMU_CONTEXT_H
#define _ASM_MMU_CONTEXT_H

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <asm/cacheflush.h>
#include <asm/hazards.h>
#include <asm/tlbflush.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#include <asm/smtc.h>
#endif /* SMTC */
#include <asm-generic/mm_hooks.h>

/*
 * For the fast tlb miss handlers, we keep a per cpu array of pointers
 * to the current pgd for each processor. Also, the proc. id is stuffed
 * into the context register.
 */
extern unsigned long pgd_current[];

#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
	pgd_current[smp_processor_id()] = (unsigned long)(pgd)

#ifdef CONFIG_32BIT
#define TLBMISS_HANDLER_SETUP()						\
	write_c0_context((unsigned long) smp_processor_id() << 25);	\
	back_to_back_c0_hazard();					\
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif
#ifdef CONFIG_64BIT
#define TLBMISS_HANDLER_SETUP()						\
	write_c0_context((unsigned long) smp_processor_id() << 26);	\
	back_to_back_c0_hazard();					\
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

#define ASID_INC	0x40
#define ASID_MASK	0xfc0

#elif defined(CONFIG_CPU_R8000)

#define ASID_INC	0x10
#define ASID_MASK	0xff0

#elif defined(CONFIG_CPU_RM9000)

#define ASID_INC	0x1
#define ASID_MASK	0xfff

/* SMTC/34K debug hack - but maybe we'll keep it */
#elif defined(CONFIG_MIPS_MT_SMTC)

#define ASID_INC	0x1
extern unsigned long smtc_asid_mask;
#define ASID_MASK	(smtc_asid_mask)
#define	HW_ASID_MASK	0xff
/* End SMTC/34K debug hack */
#else /* FIXME: not correct for R6000 */

#define ASID_INC	0x1
#define ASID_MASK	0xff

#endif

#define cpu_context(cpu, mm)	((mm)->context[cpu])
#define cpu_asid(cpu, mm)	(cpu_context((cpu), (mm)) & ASID_MASK)
#define asid_cache(cpu)		(cpu_data[cpu].asid_cache)

static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}

/*
 *  All unused by hardware upper bits will be considered
 *  as a software asid extension.
 */
#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)

#ifndef CONFIG_MIPS_MT_SMTC
/* Normal, classic MIPS get_new_mmu_context */
static inline void
get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
	unsigned long asid = asid_cache(cpu);

	if (! ((asid += ASID_INC) & ASID_MASK) ) {
		if (cpu_has_vtag_icache)
			flush_icache_all();
		local_flush_tlb_all();	/* start new asid cycle */
		if (!asid)		/* fix version if needed */
			asid = ASID_FIRST_VERSION;
	}
	cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}

#else /* CONFIG_MIPS_MT_SMTC */

#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))

#endif /* CONFIG_MIPS_MT_SMTC */

/*
 * Initialize the context related info for a new mm_struct
 * instance.
 */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
	int i;

	for_each_online_cpu(i)
		cpu_context(i, mm) = 0;

	return 0;
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                             struct task_struct *tsk)
{
	unsigned int cpu = smp_processor_id();
	unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	unsigned long mtflags;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	local_irq_save(flags);
	mtflags = dvpe();
#else /* Not SMTC */
	local_irq_save(flags);
#endif /* CONFIG_MIPS_MT_SMTC */

	/* Check if our ASID is of an older version and thus invalid */
	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
		get_new_mmu_context(next, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * If the EntryHi ASID being replaced happens to be
	 * the value flagged at ASID recycling time as having
	 * an extended life, clear the bit showing it being
	 * in use by this "CPU", and if that's the last bit,
	 * free up the ASID value for use and flush any old
	 * instances of it from the TLB.
	 */
	oldasid = (read_c0_entryhi() & ASID_MASK);
	if(smtc_live_asid[mytlb][oldasid]) {
		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
		if(smtc_live_asid[mytlb][oldasid] == 0)
			smtc_flush_tlb_asid(oldasid);
	}
	/*
	 * Tread softly on EntryHi, and so long as we support
	 * having ASID_MASK smaller than the hardware maximum,
	 * make sure no "soft" bits become "hard"...
	 */
	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
			 cpu_asid(cpu, next));
	ehb(); /* Make sure it propagates to TCStatus */
	evpe(mtflags);
#else
	write_c0_entryhi(cpu_asid(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
	TLBMISS_HANDLER_SETUP_PGD(next->pgd);

	/*
	 * Mark current->active_mm as not "active" anymore.
	 * We don't want to mislead possible IPI tlb flush routines.
	 */
	cpumask_clear_cpu(cpu, mm_cpumask(prev));
	cpumask_set_cpu(cpu, mm_cpumask(next));

	local_irq_restore(flags);
}

/*
 * Destroy context related info for an mm_struct that is about
 * to be put to rest.
 */
static inline void destroy_context(struct mm_struct *mm)
{
}

#define deactivate_mm(tsk, mm)	do { } while (0)

/*
 * After we have set current->mm to a new value, this activates
 * the context for the new mm so we see the new mappings.
 */
static inline void
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
	unsigned long flags;
	unsigned int cpu = smp_processor_id();

#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	unsigned long mtflags;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */

	local_irq_save(flags);

	/* Unconditionally get a new ASID.  */
	get_new_mmu_context(next, cpu);

#ifdef CONFIG_MIPS_MT_SMTC
	/* See comments for similar code above */
	mtflags = dvpe();
	oldasid = read_c0_entryhi() & ASID_MASK;
	if(smtc_live_asid[mytlb][oldasid]) {
		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
		if(smtc_live_asid[mytlb][oldasid] == 0)
			 smtc_flush_tlb_asid(oldasid);
	}
	/* See comments for similar code above */
	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
	                 cpu_asid(cpu, next));
	ehb(); /* Make sure it propagates to TCStatus */
	evpe(mtflags);
#else
	write_c0_entryhi(cpu_asid(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
	TLBMISS_HANDLER_SETUP_PGD(next->pgd);

	/* mark mmu ownership change */
	cpumask_clear_cpu(cpu, mm_cpumask(prev));
	cpumask_set_cpu(cpu, mm_cpumask(next));

	local_irq_restore(flags);
}

/*
 * If mm is currently active_mm, we can't really drop it.  Instead,
 * we will get a new one for it.
 */
static inline void
drop_mmu_context(struct mm_struct *mm, unsigned cpu)
{
	unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
	unsigned long oldasid;
	/* Can't use spinlock because called from TLB flush within DVPE */
	unsigned int prevvpe;
	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */

	local_irq_save(flags);

	if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
		get_new_mmu_context(mm, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
		/* See comments for similar code above */
		prevvpe = dvpe();
		oldasid = (read_c0_entryhi() & ASID_MASK);
		if (smtc_live_asid[mytlb][oldasid]) {
			smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
			if(smtc_live_asid[mytlb][oldasid] == 0)
				smtc_flush_tlb_asid(oldasid);
		}
		/* See comments for similar code above */
		write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
				| cpu_asid(cpu, mm));
		ehb(); /* Make sure it propagates to TCStatus */
		evpe(prevvpe);
#else /* not CONFIG_MIPS_MT_SMTC */
		write_c0_entryhi(cpu_asid(cpu, mm));
#endif /* CONFIG_MIPS_MT_SMTC */
	} else {
		/* will get a new context next time */
#ifndef CONFIG_MIPS_MT_SMTC
		cpu_context(cpu, mm) = 0;
#else /* SMTC */
		int i;

		/* SMTC shares the TLB (and ASIDs) across VPEs */
		for_each_online_cpu(i) {
		    if((smtc_status & SMTC_TLB_SHARED)
		    || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
			cpu_context(i, mm) = 0;
		}
#endif /* CONFIG_MIPS_MT_SMTC */
	}
	local_irq_restore(flags);
}

#endif /* _ASM_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Switch a MMU context.
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	*/
	11	#ifndef _ASM_MMU_CONTEXT_H
	12	#define _ASM_MMU_CONTEXT_H
	13
1da177e4 LT	14	#include <linux/errno.h>
1da177e4 LT	15	#include <linux/sched.h>
631330f5	16	#include <linux/smp.h>
1da177e4 LT	17	#include <linux/slab.h>
1da177e4 LT	18	#include <asm/cacheflush.h>
c2ea1d56	19	#include <asm/hazards.h>
1da177e4	20	#include <asm/tlbflush.h>
41c594ab RB	21	#ifdef CONFIG_MIPS_MT_SMTC
	22	#include <asm/mipsmtregs.h>
	23	#include <asm/smtc.h>
	24	#endif /* SMTC */
d6dd61c8	25	#include <asm-generic/mm_hooks.h>
1da177e4 LT	26
	27	/*
	28	* For the fast tlb miss handlers, we keep a per cpu array of pointers
	29	* to the current pgd for each processor. Also, the proc. id is stuffed
	30	* into the context register.
	31	*/
	32	extern unsigned long pgd_current[];
	33
	34	#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
	35	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
	36
875d43e7	37	#ifdef CONFIG_32BIT
1da177e4	38	#define TLBMISS_HANDLER_SETUP() \
1b3a6e97	39	write_c0_context((unsigned long) smp_processor_id() << 25); \
c2ea1d56	40	back_to_back_c0_hazard(); \
1da177e4 LT	41	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
1da177e4 LT	42	#endif
8145095c	43	#ifdef CONFIG_64BIT
1da177e4	44	#define TLBMISS_HANDLER_SETUP() \
1b3a6e97	45	write_c0_context((unsigned long) smp_processor_id() << 26); \
c2ea1d56	46	back_to_back_c0_hazard(); \
1da177e4 LT	47	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
	48	#endif
	49
	50	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	51
	52	#define ASID_INC 0x40
	53	#define ASID_MASK 0xfc0
	54
	55	#elif defined(CONFIG_CPU_R8000)
	56
	57	#define ASID_INC 0x10
	58	#define ASID_MASK 0xff0
	59
	60	#elif defined(CONFIG_CPU_RM9000)
	61
	62	#define ASID_INC 0x1
	63	#define ASID_MASK 0xfff
	64
41c594ab RB	65	/* SMTC/34K debug hack - but maybe we'll keep it */
	66	#elif defined(CONFIG_MIPS_MT_SMTC)
	67
	68	#define ASID_INC 0x1
	69	extern unsigned long smtc_asid_mask;
	70	#define ASID_MASK (smtc_asid_mask)
	71	#define HW_ASID_MASK 0xff
	72	/* End SMTC/34K debug hack */
1da177e4 LT	73	#else /* FIXME: not correct for R6000 */
	74
	75	#define ASID_INC 0x1
	76	#define ASID_MASK 0xff
	77
	78	#endif
	79
	80	#define cpu_context(cpu, mm) ((mm)->context[cpu])
	81	#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
	82	#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
	83
	84	static inline void enter_lazy_tlb(struct mm_struct mm, struct task_struct tsk)
	85	{
	86	}
	87
	88	/*
	89	* All unused by hardware upper bits will be considered
	90	* as a software asid extension.
	91	*/
	92	#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK\|(ASID_MASK-1)))
	93	#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
	94
41c594ab RB	95	#ifndef CONFIG_MIPS_MT_SMTC
41c594ab RB	96	/* Normal, classic MIPS get_new_mmu_context */
1da177e4 LT	97	static inline void
	98	get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
	99	{
	100	unsigned long asid = asid_cache(cpu);
	101
	102	if (! ((asid += ASID_INC) & ASID_MASK) ) {
	103	if (cpu_has_vtag_icache)
	104	flush_icache_all();
	105	local_flush_tlb_all(); /* start new asid cycle */
	106	if (!asid) /* fix version if needed */
	107	asid = ASID_FIRST_VERSION;
	108	}
	109	cpu_context(cpu, mm) = asid_cache(cpu) = asid;
	110	}
	111
41c594ab RB	112	#else /* CONFIG_MIPS_MT_SMTC */
41c594ab RB	113
21a151d8	114	#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
41c594ab RB	115
	116	#endif /* CONFIG_MIPS_MT_SMTC */
	117
1da177e4 LT	118	/*
	119	* Initialize the context related info for a new mm_struct
	120	* instance.
	121	*/
	122	static inline int
	123	init_new_context(struct task_struct tsk, struct mm_struct mm)
	124	{
	125	int i;
	126
b5eb5511	127	for_each_online_cpu(i)
1da177e4 LT	128	cpu_context(i, mm) = 0;
	129
	130	return 0;
	131	}
	132
	133	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	134	struct task_struct *tsk)
	135	{
	136	unsigned int cpu = smp_processor_id();
	137	unsigned long flags;
41c594ab RB	138	#ifdef CONFIG_MIPS_MT_SMTC
	139	unsigned long oldasid;
	140	unsigned long mtflags;
	141	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
1da177e4	142	local_irq_save(flags);
41c594ab RB	143	mtflags = dvpe();
	144	#else /* Not SMTC */
	145	local_irq_save(flags);
	146	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	147
	148	/* Check if our ASID is of an older version and thus invalid */
	149	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
	150	get_new_mmu_context(next, cpu);
41c594ab RB	151	#ifdef CONFIG_MIPS_MT_SMTC
	152	/*
	153	* If the EntryHi ASID being replaced happens to be
	154	* the value flagged at ASID recycling time as having
	155	* an extended life, clear the bit showing it being
	156	* in use by this "CPU", and if that's the last bit,
	157	* free up the ASID value for use and flush any old
	158	* instances of it from the TLB.
	159	*/
	160	oldasid = (read_c0_entryhi() & ASID_MASK);
	161	if(smtc_live_asid[mytlb][oldasid]) {
	162	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
	163	if(smtc_live_asid[mytlb][oldasid] == 0)
	164	smtc_flush_tlb_asid(oldasid);
	165	}
	166	/*
	167	* Tread softly on EntryHi, and so long as we support
	168	* having ASID_MASK smaller than the hardware maximum,
	169	* make sure no "soft" bits become "hard"...
	170	*/
d30cecbc RB	171	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) \|
d30cecbc RB	172	cpu_asid(cpu, next));
41c594ab RB	173	ehb(); /* Make sure it propagates to TCStatus */
	174	evpe(mtflags);
	175	#else
d30cecbc	176	write_c0_entryhi(cpu_asid(cpu, next));
41c594ab	177	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	178	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
	179
	180	/*
	181	* Mark current->active_mm as not "active" anymore.
	182	* We don't want to mislead possible IPI tlb flush routines.
	183	*/
55b8cab4 RR	184	cpumask_clear_cpu(cpu, mm_cpumask(prev));
55b8cab4 RR	185	cpumask_set_cpu(cpu, mm_cpumask(next));
1da177e4 LT	186
	187	local_irq_restore(flags);
	188	}
	189
	190	/*
	191	* Destroy context related info for an mm_struct that is about
	192	* to be put to rest.
	193	*/
	194	static inline void destroy_context(struct mm_struct *mm)
	195	{
	196	}
	197
21a151d8	198	#define deactivate_mm(tsk, mm) do { } while (0)
1da177e4 LT	199
	200	/*
	201	* After we have set current->mm to a new value, this activates
	202	* the context for the new mm so we see the new mappings.
	203	*/
	204	static inline void
	205	activate_mm(struct mm_struct prev, struct mm_struct next)
	206	{
	207	unsigned long flags;
	208	unsigned int cpu = smp_processor_id();
	209
41c594ab RB	210	#ifdef CONFIG_MIPS_MT_SMTC
	211	unsigned long oldasid;
	212	unsigned long mtflags;
	213	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	214	#endif /* CONFIG_MIPS_MT_SMTC */
	215
1da177e4 LT	216	local_irq_save(flags);
	217
	218	/* Unconditionally get a new ASID. */
	219	get_new_mmu_context(next, cpu);
	220
41c594ab RB	221	#ifdef CONFIG_MIPS_MT_SMTC
	222	/* See comments for similar code above */
	223	mtflags = dvpe();
	224	oldasid = read_c0_entryhi() & ASID_MASK;
	225	if(smtc_live_asid[mytlb][oldasid]) {
	226	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
384740dc RB	227	if(smtc_live_asid[mytlb][oldasid] == 0)
384740dc RB	228	smtc_flush_tlb_asid(oldasid);
41c594ab RB	229	}
	230	/* See comments for similar code above */
	231	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) \|
d30cecbc	232	cpu_asid(cpu, next));
41c594ab RB	233	ehb(); /* Make sure it propagates to TCStatus */
	234	evpe(mtflags);
	235	#else
d30cecbc	236	write_c0_entryhi(cpu_asid(cpu, next));
41c594ab	237	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	238	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
	239
	240	/* mark mmu ownership change */
55b8cab4 RR	241	cpumask_clear_cpu(cpu, mm_cpumask(prev));
55b8cab4 RR	242	cpumask_set_cpu(cpu, mm_cpumask(next));
1da177e4 LT	243
	244	local_irq_restore(flags);
	245	}
	246
	247	/*
	248	* If mm is currently active_mm, we can't really drop it. Instead,
	249	* we will get a new one for it.
	250	*/
	251	static inline void
	252	drop_mmu_context(struct mm_struct *mm, unsigned cpu)
	253	{
	254	unsigned long flags;
41c594ab RB	255	#ifdef CONFIG_MIPS_MT_SMTC
	256	unsigned long oldasid;
	257	/* Can't use spinlock because called from TLB flush within DVPE */
	258	unsigned int prevvpe;
	259	int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
	260	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	261
	262	local_irq_save(flags);
	263
55b8cab4	264	if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
1da177e4	265	get_new_mmu_context(mm, cpu);
41c594ab RB	266	#ifdef CONFIG_MIPS_MT_SMTC
	267	/* See comments for similar code above */
	268	prevvpe = dvpe();
	269	oldasid = (read_c0_entryhi() & ASID_MASK);
6b8aab09 RB	270	if (smtc_live_asid[mytlb][oldasid]) {
	271	smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
	272	if(smtc_live_asid[mytlb][oldasid] == 0)
	273	smtc_flush_tlb_asid(oldasid);
41c594ab RB	274	}
	275	/* See comments for similar code above */
	276	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
	277	\| cpu_asid(cpu, mm));
	278	ehb(); /* Make sure it propagates to TCStatus */
	279	evpe(prevvpe);
	280	#else /* not CONFIG_MIPS_MT_SMTC */
1da177e4	281	write_c0_entryhi(cpu_asid(cpu, mm));
41c594ab	282	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	283	} else {
1da177e4 LT	284	/* will get a new context next time */
41c594ab	285	#ifndef CONFIG_MIPS_MT_SMTC
1da177e4	286	cpu_context(cpu, mm) = 0;
41c594ab RB	287	#else /* SMTC */
	288	int i;
	289
	290	/* SMTC shares the TLB (and ASIDs) across VPEs */
b5eb5511	291	for_each_online_cpu(i) {
384740dc RB	292	if((smtc_status & SMTC_TLB_SHARED)
384740dc RB	293	\|\| (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
41c594ab RB	294	cpu_context(i, mm) = 0;
	295	}
	296	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	297	}
1da177e4 LT	298	local_irq_restore(flags);
	299	}
	300
	301	#endif /* _ASM_MMU_CONTEXT_H */