projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c642506 J |
1 | /* |
| 2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
| 3 | * reserved. | |
| 4 | * | |
| 5 | * This software is available to you under a choice of one of two | |
| 6 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 7 | * General Public License (GPL) Version 2, available from the file | |
| 8 | * COPYING in the main directory of this source tree, or the NetLogic | |
| 9 | * license below: | |
| 10 | * | |
| 11 | * Redistribution and use in source and binary forms, with or without | |
| 12 | * modification, are permitted provided that the following conditions | |
| 13 | * are met: | |
| 14 | * | |
| 15 | * 1. Redistributions of source code must retain the above copyright | |
| 16 | * notice, this list of conditions and the following disclaimer. | |
| 17 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 18 | * notice, this list of conditions and the following disclaimer in | |
| 19 | * the documentation and/or other materials provided with the | |
| 20 | * distribution. | |
| 21 | * | |
| 22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
| 23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
| 24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
| 27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
| 28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
| 29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
| 30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
| 31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
| 32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 33 | */ | |
| 34 | ||
| 35 | #ifndef _ASM_NLM_MIPS_EXTS_H | |
| 36 | #define _ASM_NLM_MIPS_EXTS_H | |
| 37 | ||
| 38 | /* | |
| 39 | * XLR and XLP interrupt request and interrupt mask registers | |
| 40 | */ | |
| 41 | #define read_c0_eirr() __read_64bit_c0_register($9, 6) | |
| 42 | #define read_c0_eimr() __read_64bit_c0_register($9, 7) | |
| 43 | #define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) | |
| 44 | ||
| 45 | /* | |
| 46 | * Writing EIMR in 32 bit is a special case, the lower 8 bit of the | |
| 47 | * EIMR is shadowed in the status register, so we cannot save and | |
| 48 | * restore status register for split read. | |
| 49 | */ | |
| 50 | #define write_c0_eimr(val) \ | |
| 51 | do { \ | |
| 52 | if (sizeof(unsigned long) == 4) { \ | |
| 53 | unsigned long __flags; \ | |
| 54 | \ | |
| 55 | local_irq_save(__flags); \ | |
| 56 | __asm__ __volatile__( \ | |
| 57 | ".set\tmips64\n\t" \ | |
| 58 | "dsll\t%L0, %L0, 32\n\t" \ | |
| 59 | "dsrl\t%L0, %L0, 32\n\t" \ | |
| 60 | "dsll\t%M0, %M0, 32\n\t" \ | |
| 61 | "or\t%L0, %L0, %M0\n\t" \ | |
| 62 | "dmtc0\t%L0, $9, 7\n\t" \ | |
| 63 | ".set\tmips0" \ | |
| 64 | : : "r" (val)); \ | |
| 65 | __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ | |
| 66 | local_irq_restore(__flags); \ | |
| 67 | } else \ | |
| 68 | __write_64bit_c0_register($9, 7, (val)); \ | |
| 69 | } while (0) | |
| 70 | ||
| 71 | static inline int hard_smp_processor_id(void) | |
| 72 | { | |
| 73 | return __read_32bit_c0_register($15, 1) & 0x3ff; | |
| 74 | } | |
| 75 | ||
| 76 | #endif /*_ASM_NLM_MIPS_EXTS_H */ |