[deliverable/linux.git] / arch / mips / include / asm / netlogic / xlp-hal / uart.h

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __XLP_HAL_UART_H__
#define __XLP_HAL_UART_H__

/* UART Specific registers */
#define UART_RX_DATA		0x00
#define UART_TX_DATA		0x00

#define UART_INT_EN		0x01
#define UART_INT_ID		0x02
#define UART_FIFO_CTL		0x02
#define UART_LINE_CTL		0x03
#define UART_MODEM_CTL		0x04
#define UART_LINE_STS		0x05
#define UART_MODEM_STS		0x06

#define UART_DIVISOR0		0x00
#define UART_DIVISOR1		0x01

#define BASE_BAUD		(XLP_IO_CLK/16)
#define BAUD_DIVISOR(baud)	(BASE_BAUD / baud)

/* LCR mask values */
#define LCR_5BITS		0x00
#define LCR_6BITS		0x01
#define LCR_7BITS		0x02
#define LCR_8BITS		0x03
#define LCR_STOPB		0x04
#define LCR_PENAB		0x08
#define LCR_PODD		0x00
#define LCR_PEVEN		0x10
#define LCR_PONE		0x20
#define LCR_PZERO		0x30
#define LCR_SBREAK		0x40
#define LCR_EFR_ENABLE		0xbf
#define LCR_DLAB		0x80

/* MCR mask values */
#define MCR_DTR			0x01
#define MCR_RTS			0x02
#define MCR_DRS			0x04
#define MCR_IE			0x08
#define MCR_LOOPBACK		0x10

/* FCR mask values */
#define FCR_RCV_RST		0x02
#define FCR_XMT_RST		0x04
#define FCR_RX_LOW		0x00
#define FCR_RX_MEDL		0x40
#define FCR_RX_MEDH		0x80
#define FCR_RX_HIGH		0xc0

/* IER mask values */
#define IER_ERXRDY		0x1
#define IER_ETXRDY		0x2
#define IER_ERLS		0x4
#define IER_EMSC		0x8

#if !defined(LOCORE) && !defined(__ASSEMBLY__)

#define nlm_read_uart_reg(b, r)		nlm_read_reg(b, r)
#define nlm_write_uart_reg(b, r, v)	nlm_write_reg(b, r, v)
#define nlm_get_uart_pcibase(node, inst)	\
		nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
#define nlm_get_uart_regbase(node, inst)	\
			(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)

static inline void
nlm_uart_set_baudrate(uint64_t base, int baud)
{
	uint32_t lcr;

	lcr = nlm_read_uart_reg(base, UART_LINE_CTL);

	/* enable divisor register, and write baud values */
	nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
	nlm_write_uart_reg(base, UART_DIVISOR0,
			(BAUD_DIVISOR(baud) & 0xff));
	nlm_write_uart_reg(base, UART_DIVISOR1,
			((BAUD_DIVISOR(baud) >> 8) & 0xff));

	/* restore default lcr */
	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
}

static inline void
nlm_uart_outbyte(uint64_t base, char c)
{
	uint32_t lsr;

	for (;;) {
		lsr = nlm_read_uart_reg(base, UART_LINE_STS);
		if (lsr & 0x20)
			break;
	}

	nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
}

static inline char
nlm_uart_inbyte(uint64_t base)
{
	int data, lsr;

	for (;;) {
		lsr = nlm_read_uart_reg(base, UART_LINE_STS);
		if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
			data = 0;
			break;
		}
		if (lsr & 0x01) {	/* Rx data */
			data = nlm_read_uart_reg(base, UART_RX_DATA);
			break;
		}
	}

	return (char)data;
}

static inline int
nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
	int parity, int int_en, int loopback)
{
	uint32_t lcr;

	lcr = 0;
	if (databits >= 8)
		lcr |= LCR_8BITS;
	else if (databits == 7)
		lcr |= LCR_7BITS;
	else if (databits == 6)
		lcr |= LCR_6BITS;
	else
		lcr |= LCR_5BITS;

	if (stopbits > 1)
		lcr |= LCR_STOPB;

	lcr |= parity << 3;

	/* setup default lcr */
	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);

	/* Reset the FIFOs */
	nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);

	nlm_uart_set_baudrate(base, baud);

	if (loopback)
		nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);

	if (int_en)
		nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);

	return 0;
}
#endif /* !LOCORE && !__ASSEMBLY__ */
#endif /* __XLP_HAL_UART_H__ */
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#ifndef __XLP_HAL_UART_H__
	36	#define __XLP_HAL_UART_H__
	37
	38	/* UART Specific registers */
	39	#define UART_RX_DATA 0x00
	40	#define UART_TX_DATA 0x00
	41
	42	#define UART_INT_EN 0x01
	43	#define UART_INT_ID 0x02
	44	#define UART_FIFO_CTL 0x02
	45	#define UART_LINE_CTL 0x03
	46	#define UART_MODEM_CTL 0x04
	47	#define UART_LINE_STS 0x05
	48	#define UART_MODEM_STS 0x06
	49
	50	#define UART_DIVISOR0 0x00
	51	#define UART_DIVISOR1 0x01
	52
	53	#define BASE_BAUD (XLP_IO_CLK/16)
	54	#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
	55
	56	/* LCR mask values */
	57	#define LCR_5BITS 0x00
	58	#define LCR_6BITS 0x01
	59	#define LCR_7BITS 0x02
	60	#define LCR_8BITS 0x03
	61	#define LCR_STOPB 0x04
	62	#define LCR_PENAB 0x08
	63	#define LCR_PODD 0x00
	64	#define LCR_PEVEN 0x10
65	#define LCR_PONE 0x20
66	#define LCR_PZERO 0x30
67	#define LCR_SBREAK 0x40
68	#define LCR_EFR_ENABLE 0xbf
69	#define LCR_DLAB 0x80
70
71	/* MCR mask values */
72	#define MCR_DTR 0x01
73	#define MCR_RTS 0x02
74	#define MCR_DRS 0x04
75	#define MCR_IE 0x08
76	#define MCR_LOOPBACK 0x10
77
78	/* FCR mask values */
79	#define FCR_RCV_RST 0x02
80	#define FCR_XMT_RST 0x04
81	#define FCR_RX_LOW 0x00
82	#define FCR_RX_MEDL 0x40
83	#define FCR_RX_MEDH 0x80
84	#define FCR_RX_HIGH 0xc0
85
86	/* IER mask values */
87	#define IER_ERXRDY 0x1
88	#define IER_ETXRDY 0x2
89	#define IER_ERLS 0x4
90	#define IER_EMSC 0x8
91
92	#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93
70342287 RB	94	#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
70342287 RB	95	#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
65040e22 J	96	#define nlm_get_uart_pcibase(node, inst) \
	97	nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
	98	#define nlm_get_uart_regbase(node, inst) \
	99	(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
	100
	101	static inline void
	102	nlm_uart_set_baudrate(uint64_t base, int baud)
	103	{
	104	uint32_t lcr;
	105
	106	lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
	107
	108	/* enable divisor register, and write baud values */
	109	nlm_write_uart_reg(base, UART_LINE_CTL, lcr \| (1 << 7));
	110	nlm_write_uart_reg(base, UART_DIVISOR0,
	111	(BAUD_DIVISOR(baud) & 0xff));
	112	nlm_write_uart_reg(base, UART_DIVISOR1,
	113	((BAUD_DIVISOR(baud) >> 8) & 0xff));
	114
	115	/* restore default lcr */
	116	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
	117	}
	118
	119	static inline void
	120	nlm_uart_outbyte(uint64_t base, char c)
	121	{
	122	uint32_t lsr;
	123
	124	for (;;) {
	125	lsr = nlm_read_uart_reg(base, UART_LINE_STS);
	126	if (lsr & 0x20)
	127	break;
	128	}
	129
	130	nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
	131	}
	132
	133	static inline char
	134	nlm_uart_inbyte(uint64_t base)
	135	{
	136	int data, lsr;
	137
	138	for (;;) {
	139	lsr = nlm_read_uart_reg(base, UART_LINE_STS);
	140	if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
	141	data = 0;
	142	break;
	143	}
	144	if (lsr & 0x01) { /* Rx data */
	145	data = nlm_read_uart_reg(base, UART_RX_DATA);
	146	break;
	147	}
	148	}
	149
	150	return (char)data;
	151	}
	152
	153	static inline int
	154	nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
	155	int parity, int int_en, int loopback)
	156	{
	157	uint32_t lcr;
	158
	159	lcr = 0;
160	if (databits >= 8)
161	lcr \|= LCR_8BITS;
162	else if (databits == 7)
163	lcr \|= LCR_7BITS;
164	else if (databits == 6)
165	lcr \|= LCR_6BITS;
166	else
167	lcr \|= LCR_5BITS;
168
169	if (stopbits > 1)
170	lcr \|= LCR_STOPB;
171
172	lcr \|= parity << 3;
173
174	/* setup default lcr */
175	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176
177	/* Reset the FIFOs */
178	nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST \| FCR_XMT_RST);
179
180	nlm_uart_set_baudrate(base, baud);
181
182	if (loopback)
183	nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
184
185	if (int_en)
186	nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY \| IER_ETXRDY);
187
188	return 0;
189	}
190	#endif /* !LOCORE && !__ASSEMBLY__ */
191	#endif /* __XLP_HAL_UART_H__ */