projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS: KVM: Make various Cause variables 32-bit
[deliverable/linux.git] / arch / mips / include / asm / octeon / cvmx-mio-defs.h
CommitLineData
54293ec3
DD		 1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
c5aa59e8 7 * Copyright (c) 2003-2012 Cavium Networks
54293ec3
DD		 8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIO_DEFS_H__
29#define __CVMX_MIO_DEFS_H__
30
aa32a955
DD		 31#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
32#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
33#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
34#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
35#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
36#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
37#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
38#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
39#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
40#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
41#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
42#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
751c9f68
DD		 46#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
aa32a955
DD		 62#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
63#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
64#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
65#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
66#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
67#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
68#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
69#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
70#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
71#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
72#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
73#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
74#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
75#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
76#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
77#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
78#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
751c9f68 79#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
aa32a955
DD		 80#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
81#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
82#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
83#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
84#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
85#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
86#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
87#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
751c9f68
DD		 88#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
aa32a955
DD		 92#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
93#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
94#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
95#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
96#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
c5aa59e8 97#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
751c9f68
DD		 98#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
99#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
100#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
101#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
aa32a955 102#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
751c9f68 103#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
aa32a955
DD		 104#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
105#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
751c9f68
DD		 106#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
107#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
aa32a955
DD		 108#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
109#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
110#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
111#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
112#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
113#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
114#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
115#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
116#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
117#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
118#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
119#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
120#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
121#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
122#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
123#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
124#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
125#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
126#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
127#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
128#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
129#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
130#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
131#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
132#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
133#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
134#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
135#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
136#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
137#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
138#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
139#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
140#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
141#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
142#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
143#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
144#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
145#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
146#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
147#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
148#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
149#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
150#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
151#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
152#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
153#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
154#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
155#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
156#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
157#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
158#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
159#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
160#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
161#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
162#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
163#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
164#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
165#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
54293ec3
DD		 166
167union cvmx_mio_boot_bist_stat {
168 uint64_t u64;
169 struct cvmx_mio_boot_bist_stat_s {
c5aa59e8 170#ifdef __BIG_ENDIAN_BITFIELD
aa32a955 171 uint64_t reserved_0_63:64;
c5aa59e8
DD		 172#else
173 uint64_t reserved_0_63:64;
174#endif
54293ec3
DD		 175 } s;
176 struct cvmx_mio_boot_bist_stat_cn30xx {
c5aa59e8 177#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 178 uint64_t reserved_4_63:60;
179 uint64_t ncbo_1:1;
180 uint64_t ncbo_0:1;
181 uint64_t loc:1;
182 uint64_t ncbi:1;
c5aa59e8
DD		 183#else
184 uint64_t ncbi:1;
185 uint64_t loc:1;
186 uint64_t ncbo_0:1;
187 uint64_t ncbo_1:1;
188 uint64_t reserved_4_63:60;
189#endif
54293ec3
DD		 190 } cn30xx;
191 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
192 struct cvmx_mio_boot_bist_stat_cn38xx {
c5aa59e8 193#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 194 uint64_t reserved_3_63:61;
195 uint64_t ncbo_0:1;
196 uint64_t loc:1;
197 uint64_t ncbi:1;
c5aa59e8
DD		 198#else
199 uint64_t ncbi:1;
200 uint64_t loc:1;
201 uint64_t ncbo_0:1;
202 uint64_t reserved_3_63:61;
203#endif
54293ec3
DD		 204 } cn38xx;
205 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
206 struct cvmx_mio_boot_bist_stat_cn50xx {
c5aa59e8 207#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 208 uint64_t reserved_6_63:58;
209 uint64_t pcm_1:1;
210 uint64_t pcm_0:1;
211 uint64_t ncbo_1:1;
212 uint64_t ncbo_0:1;
213 uint64_t loc:1;
214 uint64_t ncbi:1;
c5aa59e8
DD		 215#else
216 uint64_t ncbi:1;
217 uint64_t loc:1;
218 uint64_t ncbo_0:1;
219 uint64_t ncbo_1:1;
220 uint64_t pcm_0:1;
221 uint64_t pcm_1:1;
222 uint64_t reserved_6_63:58;
223#endif
54293ec3
DD		 224 } cn50xx;
225 struct cvmx_mio_boot_bist_stat_cn52xx {
c5aa59e8 226#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 227 uint64_t reserved_6_63:58;
228 uint64_t ndf:2;
229 uint64_t ncbo_0:1;
230 uint64_t dma:1;
231 uint64_t loc:1;
232 uint64_t ncbi:1;
c5aa59e8
DD		 233#else
234 uint64_t ncbi:1;
235 uint64_t loc:1;
236 uint64_t dma:1;
237 uint64_t ncbo_0:1;
238 uint64_t ndf:2;
239 uint64_t reserved_6_63:58;
240#endif
54293ec3
DD		 241 } cn52xx;
242 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
c5aa59e8 243#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 244 uint64_t reserved_4_63:60;
245 uint64_t ncbo_0:1;
246 uint64_t dma:1;
247 uint64_t loc:1;
248 uint64_t ncbi:1;
c5aa59e8
DD		 249#else
250 uint64_t ncbi:1;
251 uint64_t loc:1;
252 uint64_t dma:1;
253 uint64_t ncbo_0:1;
254 uint64_t reserved_4_63:60;
255#endif
54293ec3
DD		 256 } cn52xxp1;
257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
258 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
260 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
751c9f68 261 struct cvmx_mio_boot_bist_stat_cn61xx {
c5aa59e8 262#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 263 uint64_t reserved_12_63:52;
264 uint64_t stat:12;
c5aa59e8
DD		 265#else
266 uint64_t stat:12;
267 uint64_t reserved_12_63:52;
268#endif
751c9f68 269 } cn61xx;
aa32a955 270 struct cvmx_mio_boot_bist_stat_cn63xx {
c5aa59e8 271#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 272 uint64_t reserved_9_63:55;
273 uint64_t stat:9;
c5aa59e8
DD		 274#else
275 uint64_t stat:9;
276 uint64_t reserved_9_63:55;
277#endif
aa32a955
DD		 278 } cn63xx;
279 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
751c9f68 280 struct cvmx_mio_boot_bist_stat_cn66xx {
c5aa59e8 281#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 282 uint64_t reserved_10_63:54;
283 uint64_t stat:10;
c5aa59e8
DD		 284#else
285 uint64_t stat:10;
286 uint64_t reserved_10_63:54;
287#endif
751c9f68
DD		 288 } cn66xx;
289 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
290 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
c5aa59e8 291 struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx;
54293ec3
DD		 292};
293
294union cvmx_mio_boot_comp {
295 uint64_t u64;
296 struct cvmx_mio_boot_comp_s {
c5aa59e8
DD		 297#ifdef __BIG_ENDIAN_BITFIELD
298 uint64_t reserved_0_63:64;
299#else
aa32a955 300 uint64_t reserved_0_63:64;
c5aa59e8 301#endif
aa32a955
DD		 302 } s;
303 struct cvmx_mio_boot_comp_cn50xx {
c5aa59e8 304#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 305 uint64_t reserved_10_63:54;
306 uint64_t pctl:5;
307 uint64_t nctl:5;
c5aa59e8
DD		 308#else
309 uint64_t nctl:5;
310 uint64_t pctl:5;
311 uint64_t reserved_10_63:54;
312#endif
aa32a955
DD		 313 } cn50xx;
314 struct cvmx_mio_boot_comp_cn50xx cn52xx;
315 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
316 struct cvmx_mio_boot_comp_cn50xx cn56xx;
317 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
751c9f68 318 struct cvmx_mio_boot_comp_cn61xx {
c5aa59e8 319#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 320 uint64_t reserved_12_63:52;
321 uint64_t pctl:6;
322 uint64_t nctl:6;
c5aa59e8
DD		 323#else
324 uint64_t nctl:6;
325 uint64_t pctl:6;
326 uint64_t reserved_12_63:52;
327#endif
751c9f68
DD		 328 } cn61xx;
329 struct cvmx_mio_boot_comp_cn61xx cn63xx;
330 struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
331 struct cvmx_mio_boot_comp_cn61xx cn66xx;
332 struct cvmx_mio_boot_comp_cn61xx cn68xx;
333 struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
c5aa59e8 334 struct cvmx_mio_boot_comp_cn61xx cnf71xx;
54293ec3
DD		 335};
336
337union cvmx_mio_boot_dma_cfgx {
338 uint64_t u64;
339 struct cvmx_mio_boot_dma_cfgx_s {
c5aa59e8 340#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 341 uint64_t en:1;
342 uint64_t rw:1;
343 uint64_t clr:1;
344 uint64_t reserved_60_60:1;
345 uint64_t swap32:1;
346 uint64_t swap16:1;
347 uint64_t swap8:1;
348 uint64_t endian:1;
349 uint64_t size:20;
350 uint64_t adr:36;
c5aa59e8
DD		 351#else
352 uint64_t adr:36;
353 uint64_t size:20;
354 uint64_t endian:1;
355 uint64_t swap8:1;
356 uint64_t swap16:1;
357 uint64_t swap32:1;
358 uint64_t reserved_60_60:1;
359 uint64_t clr:1;
360 uint64_t rw:1;
361 uint64_t en:1;
362#endif
54293ec3
DD		 363 } s;
364 struct cvmx_mio_boot_dma_cfgx_s cn52xx;
365 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
366 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
367 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
751c9f68 368 struct cvmx_mio_boot_dma_cfgx_s cn61xx;
aa32a955
DD		 369 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
370 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
751c9f68
DD		 371 struct cvmx_mio_boot_dma_cfgx_s cn66xx;
372 struct cvmx_mio_boot_dma_cfgx_s cn68xx;
373 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
c5aa59e8 374 struct cvmx_mio_boot_dma_cfgx_s cnf71xx;
54293ec3
DD		 375};
376
377union cvmx_mio_boot_dma_intx {
378 uint64_t u64;
379 struct cvmx_mio_boot_dma_intx_s {
c5aa59e8 380#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 381 uint64_t reserved_2_63:62;
382 uint64_t dmarq:1;
383 uint64_t done:1;
c5aa59e8
DD		 384#else
385 uint64_t done:1;
386 uint64_t dmarq:1;
387 uint64_t reserved_2_63:62;
388#endif
54293ec3
DD		 389 } s;
390 struct cvmx_mio_boot_dma_intx_s cn52xx;
391 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
392 struct cvmx_mio_boot_dma_intx_s cn56xx;
393 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
751c9f68 394 struct cvmx_mio_boot_dma_intx_s cn61xx;
aa32a955
DD		 395 struct cvmx_mio_boot_dma_intx_s cn63xx;
396 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
751c9f68
DD		 397 struct cvmx_mio_boot_dma_intx_s cn66xx;
398 struct cvmx_mio_boot_dma_intx_s cn68xx;
399 struct cvmx_mio_boot_dma_intx_s cn68xxp1;
c5aa59e8 400 struct cvmx_mio_boot_dma_intx_s cnf71xx;
54293ec3
DD		 401};
402
403union cvmx_mio_boot_dma_int_enx {
404 uint64_t u64;
405 struct cvmx_mio_boot_dma_int_enx_s {
c5aa59e8 406#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 407 uint64_t reserved_2_63:62;
408 uint64_t dmarq:1;
409 uint64_t done:1;
c5aa59e8
DD		 410#else
411 uint64_t done:1;
412 uint64_t dmarq:1;
413 uint64_t reserved_2_63:62;
414#endif
54293ec3
DD		 415 } s;
416 struct cvmx_mio_boot_dma_int_enx_s cn52xx;
417 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
418 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
419 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
751c9f68 420 struct cvmx_mio_boot_dma_int_enx_s cn61xx;
aa32a955
DD		 421 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
422 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
751c9f68
DD		 423 struct cvmx_mio_boot_dma_int_enx_s cn66xx;
424 struct cvmx_mio_boot_dma_int_enx_s cn68xx;
425 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
c5aa59e8 426 struct cvmx_mio_boot_dma_int_enx_s cnf71xx;
54293ec3
DD		 427};
428
429union cvmx_mio_boot_dma_timx {
430 uint64_t u64;
431 struct cvmx_mio_boot_dma_timx_s {
c5aa59e8 432#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 433 uint64_t dmack_pi:1;
434 uint64_t dmarq_pi:1;
435 uint64_t tim_mult:2;
436 uint64_t rd_dly:3;
437 uint64_t ddr:1;
438 uint64_t width:1;
439 uint64_t reserved_48_54:7;
440 uint64_t pause:6;
441 uint64_t dmack_h:6;
442 uint64_t we_n:6;
443 uint64_t we_a:6;
444 uint64_t oe_n:6;
445 uint64_t oe_a:6;
446 uint64_t dmack_s:6;
447 uint64_t dmarq:6;
c5aa59e8
DD		 448#else
449 uint64_t dmarq:6;
450 uint64_t dmack_s:6;
451 uint64_t oe_a:6;
452 uint64_t oe_n:6;
453 uint64_t we_a:6;
454 uint64_t we_n:6;
455 uint64_t dmack_h:6;
456 uint64_t pause:6;
457 uint64_t reserved_48_54:7;
458 uint64_t width:1;
459 uint64_t ddr:1;
460 uint64_t rd_dly:3;
461 uint64_t tim_mult:2;
462 uint64_t dmarq_pi:1;
463 uint64_t dmack_pi:1;
464#endif
54293ec3
DD		 465 } s;
466 struct cvmx_mio_boot_dma_timx_s cn52xx;
467 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
468 struct cvmx_mio_boot_dma_timx_s cn56xx;
469 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
751c9f68 470 struct cvmx_mio_boot_dma_timx_s cn61xx;
aa32a955
DD		 471 struct cvmx_mio_boot_dma_timx_s cn63xx;
472 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
751c9f68
DD		 473 struct cvmx_mio_boot_dma_timx_s cn66xx;
474 struct cvmx_mio_boot_dma_timx_s cn68xx;
475 struct cvmx_mio_boot_dma_timx_s cn68xxp1;
c5aa59e8 476 struct cvmx_mio_boot_dma_timx_s cnf71xx;
54293ec3
DD		 477};
478
479union cvmx_mio_boot_err {
480 uint64_t u64;
481 struct cvmx_mio_boot_err_s {
c5aa59e8 482#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 483 uint64_t reserved_2_63:62;
484 uint64_t wait_err:1;
485 uint64_t adr_err:1;
c5aa59e8
DD		 486#else
487 uint64_t adr_err:1;
488 uint64_t wait_err:1;
489 uint64_t reserved_2_63:62;
490#endif
54293ec3
DD		 491 } s;
492 struct cvmx_mio_boot_err_s cn30xx;
493 struct cvmx_mio_boot_err_s cn31xx;
494 struct cvmx_mio_boot_err_s cn38xx;
495 struct cvmx_mio_boot_err_s cn38xxp2;
496 struct cvmx_mio_boot_err_s cn50xx;
497 struct cvmx_mio_boot_err_s cn52xx;
498 struct cvmx_mio_boot_err_s cn52xxp1;
499 struct cvmx_mio_boot_err_s cn56xx;
500 struct cvmx_mio_boot_err_s cn56xxp1;
501 struct cvmx_mio_boot_err_s cn58xx;
502 struct cvmx_mio_boot_err_s cn58xxp1;
751c9f68 503 struct cvmx_mio_boot_err_s cn61xx;
aa32a955
DD		 504 struct cvmx_mio_boot_err_s cn63xx;
505 struct cvmx_mio_boot_err_s cn63xxp1;
751c9f68
DD		 506 struct cvmx_mio_boot_err_s cn66xx;
507 struct cvmx_mio_boot_err_s cn68xx;
508 struct cvmx_mio_boot_err_s cn68xxp1;
c5aa59e8 509 struct cvmx_mio_boot_err_s cnf71xx;
54293ec3
DD		 510};
511
512union cvmx_mio_boot_int {
513 uint64_t u64;
514 struct cvmx_mio_boot_int_s {
c5aa59e8 515#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 516 uint64_t reserved_2_63:62;
517 uint64_t wait_int:1;
518 uint64_t adr_int:1;
c5aa59e8
DD		 519#else
520 uint64_t adr_int:1;
521 uint64_t wait_int:1;
522 uint64_t reserved_2_63:62;
523#endif
54293ec3
DD		 524 } s;
525 struct cvmx_mio_boot_int_s cn30xx;
526 struct cvmx_mio_boot_int_s cn31xx;
527 struct cvmx_mio_boot_int_s cn38xx;
528 struct cvmx_mio_boot_int_s cn38xxp2;
529 struct cvmx_mio_boot_int_s cn50xx;
530 struct cvmx_mio_boot_int_s cn52xx;
531 struct cvmx_mio_boot_int_s cn52xxp1;
532 struct cvmx_mio_boot_int_s cn56xx;
533 struct cvmx_mio_boot_int_s cn56xxp1;
534 struct cvmx_mio_boot_int_s cn58xx;
535 struct cvmx_mio_boot_int_s cn58xxp1;
751c9f68 536 struct cvmx_mio_boot_int_s cn61xx;
aa32a955
DD		 537 struct cvmx_mio_boot_int_s cn63xx;
538 struct cvmx_mio_boot_int_s cn63xxp1;
751c9f68
DD		 539 struct cvmx_mio_boot_int_s cn66xx;
540 struct cvmx_mio_boot_int_s cn68xx;
541 struct cvmx_mio_boot_int_s cn68xxp1;
c5aa59e8 542 struct cvmx_mio_boot_int_s cnf71xx;
54293ec3
DD		 543};
544
545union cvmx_mio_boot_loc_adr {
546 uint64_t u64;
547 struct cvmx_mio_boot_loc_adr_s {
c5aa59e8 548#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 549 uint64_t reserved_8_63:56;
550 uint64_t adr:5;
551 uint64_t reserved_0_2:3;
c5aa59e8
DD		 552#else
553 uint64_t reserved_0_2:3;
554 uint64_t adr:5;
555 uint64_t reserved_8_63:56;
556#endif
54293ec3
DD		 557 } s;
558 struct cvmx_mio_boot_loc_adr_s cn30xx;
559 struct cvmx_mio_boot_loc_adr_s cn31xx;
560 struct cvmx_mio_boot_loc_adr_s cn38xx;
561 struct cvmx_mio_boot_loc_adr_s cn38xxp2;
562 struct cvmx_mio_boot_loc_adr_s cn50xx;
563 struct cvmx_mio_boot_loc_adr_s cn52xx;
564 struct cvmx_mio_boot_loc_adr_s cn52xxp1;
565 struct cvmx_mio_boot_loc_adr_s cn56xx;
566 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
567 struct cvmx_mio_boot_loc_adr_s cn58xx;
568 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
751c9f68 569 struct cvmx_mio_boot_loc_adr_s cn61xx;
aa32a955
DD		 570 struct cvmx_mio_boot_loc_adr_s cn63xx;
571 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
751c9f68
DD		 572 struct cvmx_mio_boot_loc_adr_s cn66xx;
573 struct cvmx_mio_boot_loc_adr_s cn68xx;
574 struct cvmx_mio_boot_loc_adr_s cn68xxp1;
c5aa59e8 575 struct cvmx_mio_boot_loc_adr_s cnf71xx;
54293ec3
DD		 576};
577
578union cvmx_mio_boot_loc_cfgx {
579 uint64_t u64;
580 struct cvmx_mio_boot_loc_cfgx_s {
c5aa59e8 581#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 582 uint64_t reserved_32_63:32;
583 uint64_t en:1;
584 uint64_t reserved_28_30:3;
585 uint64_t base:25;
586 uint64_t reserved_0_2:3;
c5aa59e8
DD		 587#else
588 uint64_t reserved_0_2:3;
589 uint64_t base:25;
590 uint64_t reserved_28_30:3;
591 uint64_t en:1;
592 uint64_t reserved_32_63:32;
593#endif
54293ec3
DD		 594 } s;
595 struct cvmx_mio_boot_loc_cfgx_s cn30xx;
596 struct cvmx_mio_boot_loc_cfgx_s cn31xx;
597 struct cvmx_mio_boot_loc_cfgx_s cn38xx;
598 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
599 struct cvmx_mio_boot_loc_cfgx_s cn50xx;
600 struct cvmx_mio_boot_loc_cfgx_s cn52xx;
601 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
602 struct cvmx_mio_boot_loc_cfgx_s cn56xx;
603 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
604 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
605 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
751c9f68 606 struct cvmx_mio_boot_loc_cfgx_s cn61xx;
aa32a955
DD		 607 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
608 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
751c9f68
DD		 609 struct cvmx_mio_boot_loc_cfgx_s cn66xx;
610 struct cvmx_mio_boot_loc_cfgx_s cn68xx;
611 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
c5aa59e8 612 struct cvmx_mio_boot_loc_cfgx_s cnf71xx;
54293ec3
DD		 613};
614
615union cvmx_mio_boot_loc_dat {
616 uint64_t u64;
617 struct cvmx_mio_boot_loc_dat_s {
c5aa59e8 618#ifdef __BIG_ENDIAN_BITFIELD
54293ec3 619 uint64_t data:64;
c5aa59e8
DD		 620#else
621 uint64_t data:64;
622#endif
54293ec3
DD		 623 } s;
624 struct cvmx_mio_boot_loc_dat_s cn30xx;
625 struct cvmx_mio_boot_loc_dat_s cn31xx;
626 struct cvmx_mio_boot_loc_dat_s cn38xx;
627 struct cvmx_mio_boot_loc_dat_s cn38xxp2;
628 struct cvmx_mio_boot_loc_dat_s cn50xx;
629 struct cvmx_mio_boot_loc_dat_s cn52xx;
630 struct cvmx_mio_boot_loc_dat_s cn52xxp1;
631 struct cvmx_mio_boot_loc_dat_s cn56xx;
632 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
633 struct cvmx_mio_boot_loc_dat_s cn58xx;
634 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
751c9f68 635 struct cvmx_mio_boot_loc_dat_s cn61xx;
aa32a955
DD		 636 struct cvmx_mio_boot_loc_dat_s cn63xx;
637 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
751c9f68
DD		 638 struct cvmx_mio_boot_loc_dat_s cn66xx;
639 struct cvmx_mio_boot_loc_dat_s cn68xx;
640 struct cvmx_mio_boot_loc_dat_s cn68xxp1;
c5aa59e8 641 struct cvmx_mio_boot_loc_dat_s cnf71xx;
54293ec3
DD		 642};
643
644union cvmx_mio_boot_pin_defs {
645 uint64_t u64;
646 struct cvmx_mio_boot_pin_defs_s {
c5aa59e8 647#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 648 uint64_t reserved_32_63:32;
649 uint64_t user1:16;
54293ec3
DD		 650 uint64_t ale:1;
651 uint64_t width:1;
652 uint64_t dmack_p2:1;
653 uint64_t dmack_p1:1;
654 uint64_t dmack_p0:1;
655 uint64_t term:2;
656 uint64_t nand:1;
751c9f68 657 uint64_t user0:8;
c5aa59e8
DD		 658#else
659 uint64_t user0:8;
660 uint64_t nand:1;
661 uint64_t term:2;
662 uint64_t dmack_p0:1;
663 uint64_t dmack_p1:1;
664 uint64_t dmack_p2:1;
665 uint64_t width:1;
666 uint64_t ale:1;
667 uint64_t user1:16;
668 uint64_t reserved_32_63:32;
669#endif
54293ec3
DD		 670 } s;
671 struct cvmx_mio_boot_pin_defs_cn52xx {
c5aa59e8 672#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 673 uint64_t reserved_16_63:48;
674 uint64_t ale:1;
675 uint64_t width:1;
676 uint64_t reserved_13_13:1;
677 uint64_t dmack_p1:1;
678 uint64_t dmack_p0:1;
679 uint64_t term:2;
680 uint64_t nand:1;
681 uint64_t reserved_0_7:8;
c5aa59e8
DD		 682#else
683 uint64_t reserved_0_7:8;
684 uint64_t nand:1;
685 uint64_t term:2;
686 uint64_t dmack_p0:1;
687 uint64_t dmack_p1:1;
688 uint64_t reserved_13_13:1;
689 uint64_t width:1;
690 uint64_t ale:1;
691 uint64_t reserved_16_63:48;
692#endif
54293ec3
DD		 693 } cn52xx;
694 struct cvmx_mio_boot_pin_defs_cn56xx {
c5aa59e8 695#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 696 uint64_t reserved_16_63:48;
697 uint64_t ale:1;
698 uint64_t width:1;
699 uint64_t dmack_p2:1;
700 uint64_t dmack_p1:1;
701 uint64_t dmack_p0:1;
702 uint64_t term:2;
703 uint64_t reserved_0_8:9;
c5aa59e8
DD		 704#else
705 uint64_t reserved_0_8:9;
706 uint64_t term:2;
707 uint64_t dmack_p0:1;
708 uint64_t dmack_p1:1;
709 uint64_t dmack_p2:1;
710 uint64_t width:1;
711 uint64_t ale:1;
712 uint64_t reserved_16_63:48;
713#endif
54293ec3 714 } cn56xx;
751c9f68 715 struct cvmx_mio_boot_pin_defs_cn61xx {
c5aa59e8 716#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 717 uint64_t reserved_32_63:32;
718 uint64_t user1:16;
719 uint64_t ale:1;
720 uint64_t width:1;
721 uint64_t reserved_13_13:1;
722 uint64_t dmack_p1:1;
723 uint64_t dmack_p0:1;
724 uint64_t term:2;
725 uint64_t nand:1;
726 uint64_t user0:8;
c5aa59e8
DD		 727#else
728 uint64_t user0:8;
729 uint64_t nand:1;
730 uint64_t term:2;
731 uint64_t dmack_p0:1;
732 uint64_t dmack_p1:1;
733 uint64_t reserved_13_13:1;
734 uint64_t width:1;
735 uint64_t ale:1;
736 uint64_t user1:16;
737 uint64_t reserved_32_63:32;
738#endif
751c9f68 739 } cn61xx;
aa32a955
DD		 740 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
741 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
751c9f68
DD		 742 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
743 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
744 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
c5aa59e8 745 struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx;
54293ec3
DD		 746};
747
748union cvmx_mio_boot_reg_cfgx {
749 uint64_t u64;
750 struct cvmx_mio_boot_reg_cfgx_s {
c5aa59e8 751#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 752 uint64_t reserved_44_63:20;
753 uint64_t dmack:2;
754 uint64_t tim_mult:2;
755 uint64_t rd_dly:3;
756 uint64_t sam:1;
757 uint64_t we_ext:2;
758 uint64_t oe_ext:2;
759 uint64_t en:1;
760 uint64_t orbit:1;
761 uint64_t ale:1;
762 uint64_t width:1;
763 uint64_t size:12;
764 uint64_t base:16;
c5aa59e8
DD		 765#else
766 uint64_t base:16;
767 uint64_t size:12;
768 uint64_t width:1;
769 uint64_t ale:1;
770 uint64_t orbit:1;
771 uint64_t en:1;
772 uint64_t oe_ext:2;
773 uint64_t we_ext:2;
774 uint64_t sam:1;
775 uint64_t rd_dly:3;
776 uint64_t tim_mult:2;
777 uint64_t dmack:2;
778 uint64_t reserved_44_63:20;
779#endif
54293ec3
DD		 780 } s;
781 struct cvmx_mio_boot_reg_cfgx_cn30xx {
c5aa59e8 782#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 783 uint64_t reserved_37_63:27;
784 uint64_t sam:1;
785 uint64_t we_ext:2;
786 uint64_t oe_ext:2;
787 uint64_t en:1;
788 uint64_t orbit:1;
789 uint64_t ale:1;
790 uint64_t width:1;
791 uint64_t size:12;
792 uint64_t base:16;
c5aa59e8
DD		 793#else
794 uint64_t base:16;
795 uint64_t size:12;
796 uint64_t width:1;
797 uint64_t ale:1;
798 uint64_t orbit:1;
799 uint64_t en:1;
800 uint64_t oe_ext:2;
801 uint64_t we_ext:2;
802 uint64_t sam:1;
803 uint64_t reserved_37_63:27;
804#endif
54293ec3
DD		 805 } cn30xx;
806 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
807 struct cvmx_mio_boot_reg_cfgx_cn38xx {
c5aa59e8 808#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 809 uint64_t reserved_32_63:32;
810 uint64_t en:1;
811 uint64_t orbit:1;
812 uint64_t reserved_28_29:2;
813 uint64_t size:12;
814 uint64_t base:16;
c5aa59e8
DD		 815#else
816 uint64_t base:16;
817 uint64_t size:12;
818 uint64_t reserved_28_29:2;
819 uint64_t orbit:1;
820 uint64_t en:1;
821 uint64_t reserved_32_63:32;
822#endif
54293ec3
DD		 823 } cn38xx;
824 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
825 struct cvmx_mio_boot_reg_cfgx_cn50xx {
c5aa59e8 826#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 827 uint64_t reserved_42_63:22;
828 uint64_t tim_mult:2;
829 uint64_t rd_dly:3;
830 uint64_t sam:1;
831 uint64_t we_ext:2;
832 uint64_t oe_ext:2;
833 uint64_t en:1;
834 uint64_t orbit:1;
835 uint64_t ale:1;
836 uint64_t width:1;
837 uint64_t size:12;
838 uint64_t base:16;
c5aa59e8
DD		 839#else
840 uint64_t base:16;
841 uint64_t size:12;
842 uint64_t width:1;
843 uint64_t ale:1;
844 uint64_t orbit:1;
845 uint64_t en:1;
846 uint64_t oe_ext:2;
847 uint64_t we_ext:2;
848 uint64_t sam:1;
849 uint64_t rd_dly:3;
850 uint64_t tim_mult:2;
851 uint64_t reserved_42_63:22;
852#endif
54293ec3
DD		 853 } cn50xx;
854 struct cvmx_mio_boot_reg_cfgx_s cn52xx;
855 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
856 struct cvmx_mio_boot_reg_cfgx_s cn56xx;
857 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
858 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
859 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
751c9f68 860 struct cvmx_mio_boot_reg_cfgx_s cn61xx;
aa32a955
DD		 861 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
862 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
751c9f68
DD		 863 struct cvmx_mio_boot_reg_cfgx_s cn66xx;
864 struct cvmx_mio_boot_reg_cfgx_s cn68xx;
865 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
c5aa59e8 866 struct cvmx_mio_boot_reg_cfgx_s cnf71xx;
54293ec3
DD		 867};
868
869union cvmx_mio_boot_reg_timx {
870 uint64_t u64;
871 struct cvmx_mio_boot_reg_timx_s {
c5aa59e8 872#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 873 uint64_t pagem:1;
874 uint64_t waitm:1;
875 uint64_t pages:2;
876 uint64_t ale:6;
877 uint64_t page:6;
878 uint64_t wait:6;
879 uint64_t pause:6;
880 uint64_t wr_hld:6;
881 uint64_t rd_hld:6;
882 uint64_t we:6;
883 uint64_t oe:6;
884 uint64_t ce:6;
885 uint64_t adr:6;
c5aa59e8
DD		 886#else
887 uint64_t adr:6;
888 uint64_t ce:6;
889 uint64_t oe:6;
890 uint64_t we:6;
891 uint64_t rd_hld:6;
892 uint64_t wr_hld:6;
893 uint64_t pause:6;
894 uint64_t wait:6;
895 uint64_t page:6;
896 uint64_t ale:6;
897 uint64_t pages:2;
898 uint64_t waitm:1;
899 uint64_t pagem:1;
900#endif
54293ec3
DD		 901 } s;
902 struct cvmx_mio_boot_reg_timx_s cn30xx;
903 struct cvmx_mio_boot_reg_timx_s cn31xx;
904 struct cvmx_mio_boot_reg_timx_cn38xx {
c5aa59e8 905#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 906 uint64_t pagem:1;
907 uint64_t waitm:1;
908 uint64_t pages:2;
909 uint64_t reserved_54_59:6;
910 uint64_t page:6;
911 uint64_t wait:6;
912 uint64_t pause:6;
913 uint64_t wr_hld:6;
914 uint64_t rd_hld:6;
915 uint64_t we:6;
916 uint64_t oe:6;
917 uint64_t ce:6;
918 uint64_t adr:6;
c5aa59e8
DD		 919#else
920 uint64_t adr:6;
921 uint64_t ce:6;
922 uint64_t oe:6;
923 uint64_t we:6;
924 uint64_t rd_hld:6;
925 uint64_t wr_hld:6;
926 uint64_t pause:6;
927 uint64_t wait:6;
928 uint64_t page:6;
929 uint64_t reserved_54_59:6;
930 uint64_t pages:2;
931 uint64_t waitm:1;
932 uint64_t pagem:1;
933#endif
54293ec3
DD		 934 } cn38xx;
935 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
936 struct cvmx_mio_boot_reg_timx_s cn50xx;
937 struct cvmx_mio_boot_reg_timx_s cn52xx;
938 struct cvmx_mio_boot_reg_timx_s cn52xxp1;
939 struct cvmx_mio_boot_reg_timx_s cn56xx;
940 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
941 struct cvmx_mio_boot_reg_timx_s cn58xx;
942 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
751c9f68 943 struct cvmx_mio_boot_reg_timx_s cn61xx;
aa32a955
DD		 944 struct cvmx_mio_boot_reg_timx_s cn63xx;
945 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
751c9f68
DD		 946 struct cvmx_mio_boot_reg_timx_s cn66xx;
947 struct cvmx_mio_boot_reg_timx_s cn68xx;
948 struct cvmx_mio_boot_reg_timx_s cn68xxp1;
c5aa59e8 949 struct cvmx_mio_boot_reg_timx_s cnf71xx;
54293ec3
DD		 950};
951
952union cvmx_mio_boot_thr {
953 uint64_t u64;
954 struct cvmx_mio_boot_thr_s {
c5aa59e8 955#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 956 uint64_t reserved_22_63:42;
957 uint64_t dma_thr:6;
958 uint64_t reserved_14_15:2;
959 uint64_t fif_cnt:6;
960 uint64_t reserved_6_7:2;
961 uint64_t fif_thr:6;
c5aa59e8
DD		 962#else
963 uint64_t fif_thr:6;
964 uint64_t reserved_6_7:2;
965 uint64_t fif_cnt:6;
966 uint64_t reserved_14_15:2;
967 uint64_t dma_thr:6;
968 uint64_t reserved_22_63:42;
969#endif
54293ec3
DD		 970 } s;
971 struct cvmx_mio_boot_thr_cn30xx {
c5aa59e8 972#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 973 uint64_t reserved_14_63:50;
974 uint64_t fif_cnt:6;
975 uint64_t reserved_6_7:2;
976 uint64_t fif_thr:6;
c5aa59e8
DD		 977#else
978 uint64_t fif_thr:6;
979 uint64_t reserved_6_7:2;
980 uint64_t fif_cnt:6;
981 uint64_t reserved_14_63:50;
982#endif
54293ec3
DD		 983 } cn30xx;
984 struct cvmx_mio_boot_thr_cn30xx cn31xx;
985 struct cvmx_mio_boot_thr_cn30xx cn38xx;
986 struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
987 struct cvmx_mio_boot_thr_cn30xx cn50xx;
988 struct cvmx_mio_boot_thr_s cn52xx;
989 struct cvmx_mio_boot_thr_s cn52xxp1;
990 struct cvmx_mio_boot_thr_s cn56xx;
991 struct cvmx_mio_boot_thr_s cn56xxp1;
992 struct cvmx_mio_boot_thr_cn30xx cn58xx;
993 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
751c9f68 994 struct cvmx_mio_boot_thr_s cn61xx;
aa32a955
DD		 995 struct cvmx_mio_boot_thr_s cn63xx;
996 struct cvmx_mio_boot_thr_s cn63xxp1;
751c9f68
DD		 997 struct cvmx_mio_boot_thr_s cn66xx;
998 struct cvmx_mio_boot_thr_s cn68xx;
999 struct cvmx_mio_boot_thr_s cn68xxp1;
c5aa59e8 1000 struct cvmx_mio_boot_thr_s cnf71xx;
751c9f68
DD		 1001};
1002
1003union cvmx_mio_emm_buf_dat {
1004 uint64_t u64;
1005 struct cvmx_mio_emm_buf_dat_s {
c5aa59e8 1006#ifdef __BIG_ENDIAN_BITFIELD
751c9f68 1007 uint64_t dat:64;
c5aa59e8
DD		 1008#else
1009 uint64_t dat:64;
1010#endif
751c9f68
DD		 1011 } s;
1012 struct cvmx_mio_emm_buf_dat_s cn61xx;
c5aa59e8 1013 struct cvmx_mio_emm_buf_dat_s cnf71xx;
751c9f68
DD		 1014};
1015
1016union cvmx_mio_emm_buf_idx {
1017 uint64_t u64;
1018 struct cvmx_mio_emm_buf_idx_s {
c5aa59e8 1019#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1020 uint64_t reserved_17_63:47;
1021 uint64_t inc:1;
1022 uint64_t reserved_7_15:9;
1023 uint64_t buf_num:1;
1024 uint64_t offset:6;
c5aa59e8
DD		 1025#else
1026 uint64_t offset:6;
1027 uint64_t buf_num:1;
1028 uint64_t reserved_7_15:9;
1029 uint64_t inc:1;
1030 uint64_t reserved_17_63:47;
1031#endif
751c9f68
DD		 1032 } s;
1033 struct cvmx_mio_emm_buf_idx_s cn61xx;
c5aa59e8 1034 struct cvmx_mio_emm_buf_idx_s cnf71xx;
751c9f68
DD		 1035};
1036
1037union cvmx_mio_emm_cfg {
1038 uint64_t u64;
1039 struct cvmx_mio_emm_cfg_s {
c5aa59e8 1040#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1041 uint64_t reserved_17_63:47;
1042 uint64_t boot_fail:1;
1043 uint64_t reserved_4_15:12;
1044 uint64_t bus_ena:4;
c5aa59e8
DD		 1045#else
1046 uint64_t bus_ena:4;
1047 uint64_t reserved_4_15:12;
1048 uint64_t boot_fail:1;
1049 uint64_t reserved_17_63:47;
1050#endif
751c9f68
DD		 1051 } s;
1052 struct cvmx_mio_emm_cfg_s cn61xx;
c5aa59e8 1053 struct cvmx_mio_emm_cfg_s cnf71xx;
751c9f68
DD		 1054};
1055
1056union cvmx_mio_emm_cmd {
1057 uint64_t u64;
1058 struct cvmx_mio_emm_cmd_s {
c5aa59e8 1059#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1060 uint64_t reserved_62_63:2;
1061 uint64_t bus_id:2;
1062 uint64_t cmd_val:1;
1063 uint64_t reserved_56_58:3;
1064 uint64_t dbuf:1;
1065 uint64_t offset:6;
1066 uint64_t reserved_43_48:6;
1067 uint64_t ctype_xor:2;
1068 uint64_t rtype_xor:3;
1069 uint64_t cmd_idx:6;
1070 uint64_t arg:32;
c5aa59e8
DD		 1071#else
1072 uint64_t arg:32;
1073 uint64_t cmd_idx:6;
1074 uint64_t rtype_xor:3;
1075 uint64_t ctype_xor:2;
1076 uint64_t reserved_43_48:6;
1077 uint64_t offset:6;
1078 uint64_t dbuf:1;
1079 uint64_t reserved_56_58:3;
1080 uint64_t cmd_val:1;
1081 uint64_t bus_id:2;
1082 uint64_t reserved_62_63:2;
1083#endif
1084 } s;
1085 struct cvmx_mio_emm_cmd_s cn61xx;
1086 struct cvmx_mio_emm_cmd_s cnf71xx;
1087};
1088
1089union cvmx_mio_emm_dma {
1090 uint64_t u64;
1091 struct cvmx_mio_emm_dma_s {
1092#ifdef __BIG_ENDIAN_BITFIELD
1093 uint64_t reserved_62_63:2;
1094 uint64_t bus_id:2;
751c9f68
DD		 1095 uint64_t dma_val:1;
1096 uint64_t sector:1;
1097 uint64_t dat_null:1;
1098 uint64_t thres:6;
1099 uint64_t rel_wr:1;
1100 uint64_t rw:1;
1101 uint64_t multi:1;
1102 uint64_t block_cnt:16;
1103 uint64_t card_addr:32;
c5aa59e8
DD		 1104#else
1105 uint64_t card_addr:32;
1106 uint64_t block_cnt:16;
1107 uint64_t multi:1;
1108 uint64_t rw:1;
1109 uint64_t rel_wr:1;
1110 uint64_t thres:6;
1111 uint64_t dat_null:1;
1112 uint64_t sector:1;
1113 uint64_t dma_val:1;
1114 uint64_t bus_id:2;
1115 uint64_t reserved_62_63:2;
1116#endif
751c9f68
DD		 1117 } s;
1118 struct cvmx_mio_emm_dma_s cn61xx;
c5aa59e8 1119 struct cvmx_mio_emm_dma_s cnf71xx;
751c9f68
DD		 1120};
1121
1122union cvmx_mio_emm_int {
1123 uint64_t u64;
1124 struct cvmx_mio_emm_int_s {
c5aa59e8 1125#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1126 uint64_t reserved_7_63:57;
1127 uint64_t switch_err:1;
1128 uint64_t switch_done:1;
1129 uint64_t dma_err:1;
1130 uint64_t cmd_err:1;
1131 uint64_t dma_done:1;
1132 uint64_t cmd_done:1;
1133 uint64_t buf_done:1;
c5aa59e8
DD		 1134#else
1135 uint64_t buf_done:1;
1136 uint64_t cmd_done:1;
1137 uint64_t dma_done:1;
1138 uint64_t cmd_err:1;
1139 uint64_t dma_err:1;
1140 uint64_t switch_done:1;
1141 uint64_t switch_err:1;
1142 uint64_t reserved_7_63:57;
1143#endif
751c9f68
DD		 1144 } s;
1145 struct cvmx_mio_emm_int_s cn61xx;
c5aa59e8 1146 struct cvmx_mio_emm_int_s cnf71xx;
751c9f68
DD		 1147};
1148
1149union cvmx_mio_emm_int_en {
1150 uint64_t u64;
1151 struct cvmx_mio_emm_int_en_s {
c5aa59e8 1152#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1153 uint64_t reserved_7_63:57;
1154 uint64_t switch_err:1;
1155 uint64_t switch_done:1;
1156 uint64_t dma_err:1;
1157 uint64_t cmd_err:1;
1158 uint64_t dma_done:1;
1159 uint64_t cmd_done:1;
1160 uint64_t buf_done:1;
c5aa59e8
DD		 1161#else
1162 uint64_t buf_done:1;
1163 uint64_t cmd_done:1;
1164 uint64_t dma_done:1;
1165 uint64_t cmd_err:1;
1166 uint64_t dma_err:1;
1167 uint64_t switch_done:1;
1168 uint64_t switch_err:1;
1169 uint64_t reserved_7_63:57;
1170#endif
751c9f68
DD		 1171 } s;
1172 struct cvmx_mio_emm_int_en_s cn61xx;
c5aa59e8 1173 struct cvmx_mio_emm_int_en_s cnf71xx;
751c9f68
DD		 1174};
1175
1176union cvmx_mio_emm_modex {
1177 uint64_t u64;
1178 struct cvmx_mio_emm_modex_s {
c5aa59e8 1179#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1180 uint64_t reserved_49_63:15;
1181 uint64_t hs_timing:1;
1182 uint64_t reserved_43_47:5;
1183 uint64_t bus_width:3;
1184 uint64_t reserved_36_39:4;
1185 uint64_t power_class:4;
1186 uint64_t clk_hi:16;
1187 uint64_t clk_lo:16;
c5aa59e8
DD		 1188#else
1189 uint64_t clk_lo:16;
1190 uint64_t clk_hi:16;
1191 uint64_t power_class:4;
1192 uint64_t reserved_36_39:4;
1193 uint64_t bus_width:3;
1194 uint64_t reserved_43_47:5;
1195 uint64_t hs_timing:1;
1196 uint64_t reserved_49_63:15;
1197#endif
751c9f68
DD		 1198 } s;
1199 struct cvmx_mio_emm_modex_s cn61xx;
c5aa59e8 1200 struct cvmx_mio_emm_modex_s cnf71xx;
751c9f68
DD		 1201};
1202
1203union cvmx_mio_emm_rca {
1204 uint64_t u64;
1205 struct cvmx_mio_emm_rca_s {
c5aa59e8 1206#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1207 uint64_t reserved_16_63:48;
1208 uint64_t card_rca:16;
c5aa59e8
DD		 1209#else
1210 uint64_t card_rca:16;
1211 uint64_t reserved_16_63:48;
1212#endif
751c9f68
DD		 1213 } s;
1214 struct cvmx_mio_emm_rca_s cn61xx;
c5aa59e8 1215 struct cvmx_mio_emm_rca_s cnf71xx;
751c9f68
DD		 1216};
1217
1218union cvmx_mio_emm_rsp_hi {
1219 uint64_t u64;
1220 struct cvmx_mio_emm_rsp_hi_s {
c5aa59e8
DD		 1221#ifdef __BIG_ENDIAN_BITFIELD
1222 uint64_t dat:64;
1223#else
751c9f68 1224 uint64_t dat:64;
c5aa59e8 1225#endif
751c9f68
DD		 1226 } s;
1227 struct cvmx_mio_emm_rsp_hi_s cn61xx;
c5aa59e8 1228 struct cvmx_mio_emm_rsp_hi_s cnf71xx;
751c9f68
DD		 1229};
1230
1231union cvmx_mio_emm_rsp_lo {
1232 uint64_t u64;
1233 struct cvmx_mio_emm_rsp_lo_s {
c5aa59e8
DD		 1234#ifdef __BIG_ENDIAN_BITFIELD
1235 uint64_t dat:64;
1236#else
751c9f68 1237 uint64_t dat:64;
c5aa59e8 1238#endif
751c9f68
DD		 1239 } s;
1240 struct cvmx_mio_emm_rsp_lo_s cn61xx;
c5aa59e8 1241 struct cvmx_mio_emm_rsp_lo_s cnf71xx;
751c9f68
DD		 1242};
1243
1244union cvmx_mio_emm_rsp_sts {
1245 uint64_t u64;
1246 struct cvmx_mio_emm_rsp_sts_s {
c5aa59e8 1247#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1248 uint64_t reserved_62_63:2;
1249 uint64_t bus_id:2;
1250 uint64_t cmd_val:1;
1251 uint64_t switch_val:1;
1252 uint64_t dma_val:1;
1253 uint64_t dma_pend:1;
1254 uint64_t reserved_29_55:27;
1255 uint64_t dbuf_err:1;
1256 uint64_t reserved_24_27:4;
1257 uint64_t dbuf:1;
1258 uint64_t blk_timeout:1;
1259 uint64_t blk_crc_err:1;
1260 uint64_t rsp_busybit:1;
1261 uint64_t stp_timeout:1;
1262 uint64_t stp_crc_err:1;
1263 uint64_t stp_bad_sts:1;
1264 uint64_t stp_val:1;
1265 uint64_t rsp_timeout:1;
1266 uint64_t rsp_crc_err:1;
1267 uint64_t rsp_bad_sts:1;
1268 uint64_t rsp_val:1;
1269 uint64_t rsp_type:3;
1270 uint64_t cmd_type:2;
1271 uint64_t cmd_idx:6;
1272 uint64_t cmd_done:1;
c5aa59e8
DD		 1273#else
1274 uint64_t cmd_done:1;
1275 uint64_t cmd_idx:6;
1276 uint64_t cmd_type:2;
1277 uint64_t rsp_type:3;
1278 uint64_t rsp_val:1;
1279 uint64_t rsp_bad_sts:1;
1280 uint64_t rsp_crc_err:1;
1281 uint64_t rsp_timeout:1;
1282 uint64_t stp_val:1;
1283 uint64_t stp_bad_sts:1;
1284 uint64_t stp_crc_err:1;
1285 uint64_t stp_timeout:1;
1286 uint64_t rsp_busybit:1;
1287 uint64_t blk_crc_err:1;
1288 uint64_t blk_timeout:1;
1289 uint64_t dbuf:1;
1290 uint64_t reserved_24_27:4;
1291 uint64_t dbuf_err:1;
1292 uint64_t reserved_29_55:27;
1293 uint64_t dma_pend:1;
1294 uint64_t dma_val:1;
1295 uint64_t switch_val:1;
1296 uint64_t cmd_val:1;
1297 uint64_t bus_id:2;
1298 uint64_t reserved_62_63:2;
1299#endif
751c9f68
DD		 1300 } s;
1301 struct cvmx_mio_emm_rsp_sts_s cn61xx;
c5aa59e8 1302 struct cvmx_mio_emm_rsp_sts_s cnf71xx;
751c9f68
DD		 1303};
1304
1305union cvmx_mio_emm_sample {
1306 uint64_t u64;
1307 struct cvmx_mio_emm_sample_s {
c5aa59e8 1308#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1309 uint64_t reserved_26_63:38;
1310 uint64_t cmd_cnt:10;
1311 uint64_t reserved_10_15:6;
1312 uint64_t dat_cnt:10;
c5aa59e8
DD		 1313#else
1314 uint64_t dat_cnt:10;
1315 uint64_t reserved_10_15:6;
1316 uint64_t cmd_cnt:10;
1317 uint64_t reserved_26_63:38;
1318#endif
751c9f68
DD		 1319 } s;
1320 struct cvmx_mio_emm_sample_s cn61xx;
c5aa59e8 1321 struct cvmx_mio_emm_sample_s cnf71xx;
751c9f68
DD		 1322};
1323
1324union cvmx_mio_emm_sts_mask {
1325 uint64_t u64;
1326 struct cvmx_mio_emm_sts_mask_s {
c5aa59e8 1327#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1328 uint64_t reserved_32_63:32;
1329 uint64_t sts_msk:32;
c5aa59e8
DD		 1330#else
1331 uint64_t sts_msk:32;
1332 uint64_t reserved_32_63:32;
1333#endif
751c9f68
DD		 1334 } s;
1335 struct cvmx_mio_emm_sts_mask_s cn61xx;
c5aa59e8 1336 struct cvmx_mio_emm_sts_mask_s cnf71xx;
751c9f68
DD		 1337};
1338
1339union cvmx_mio_emm_switch {
1340 uint64_t u64;
1341 struct cvmx_mio_emm_switch_s {
c5aa59e8 1342#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1343 uint64_t reserved_62_63:2;
1344 uint64_t bus_id:2;
1345 uint64_t switch_exe:1;
1346 uint64_t switch_err0:1;
1347 uint64_t switch_err1:1;
1348 uint64_t switch_err2:1;
1349 uint64_t reserved_49_55:7;
1350 uint64_t hs_timing:1;
1351 uint64_t reserved_43_47:5;
1352 uint64_t bus_width:3;
1353 uint64_t reserved_36_39:4;
1354 uint64_t power_class:4;
1355 uint64_t clk_hi:16;
1356 uint64_t clk_lo:16;
c5aa59e8
DD		 1357#else
1358 uint64_t clk_lo:16;
1359 uint64_t clk_hi:16;
1360 uint64_t power_class:4;
1361 uint64_t reserved_36_39:4;
1362 uint64_t bus_width:3;
1363 uint64_t reserved_43_47:5;
1364 uint64_t hs_timing:1;
1365 uint64_t reserved_49_55:7;
1366 uint64_t switch_err2:1;
1367 uint64_t switch_err1:1;
1368 uint64_t switch_err0:1;
1369 uint64_t switch_exe:1;
1370 uint64_t bus_id:2;
1371 uint64_t reserved_62_63:2;
1372#endif
751c9f68
DD		 1373 } s;
1374 struct cvmx_mio_emm_switch_s cn61xx;
c5aa59e8 1375 struct cvmx_mio_emm_switch_s cnf71xx;
751c9f68
DD		 1376};
1377
1378union cvmx_mio_emm_wdog {
1379 uint64_t u64;
1380 struct cvmx_mio_emm_wdog_s {
c5aa59e8 1381#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1382 uint64_t reserved_26_63:38;
1383 uint64_t clk_cnt:26;
c5aa59e8
DD		 1384#else
1385 uint64_t clk_cnt:26;
1386 uint64_t reserved_26_63:38;
1387#endif
751c9f68
DD		 1388 } s;
1389 struct cvmx_mio_emm_wdog_s cn61xx;
c5aa59e8 1390 struct cvmx_mio_emm_wdog_s cnf71xx;
54293ec3
DD		 1391};
1392
1393union cvmx_mio_fus_bnk_datx {
1394 uint64_t u64;
1395 struct cvmx_mio_fus_bnk_datx_s {
c5aa59e8
DD		 1396#ifdef __BIG_ENDIAN_BITFIELD
1397 uint64_t dat:64;
1398#else
54293ec3 1399 uint64_t dat:64;
c5aa59e8 1400#endif
54293ec3
DD		 1401 } s;
1402 struct cvmx_mio_fus_bnk_datx_s cn50xx;
1403 struct cvmx_mio_fus_bnk_datx_s cn52xx;
1404 struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
1405 struct cvmx_mio_fus_bnk_datx_s cn56xx;
1406 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
1407 struct cvmx_mio_fus_bnk_datx_s cn58xx;
1408 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
751c9f68 1409 struct cvmx_mio_fus_bnk_datx_s cn61xx;
aa32a955
DD		 1410 struct cvmx_mio_fus_bnk_datx_s cn63xx;
1411 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
751c9f68
DD		 1412 struct cvmx_mio_fus_bnk_datx_s cn66xx;
1413 struct cvmx_mio_fus_bnk_datx_s cn68xx;
1414 struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
c5aa59e8 1415 struct cvmx_mio_fus_bnk_datx_s cnf71xx;
54293ec3
DD		 1416};
1417
1418union cvmx_mio_fus_dat0 {
1419 uint64_t u64;
1420 struct cvmx_mio_fus_dat0_s {
c5aa59e8 1421#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1422 uint64_t reserved_32_63:32;
1423 uint64_t man_info:32;
c5aa59e8
DD		 1424#else
1425 uint64_t man_info:32;
1426 uint64_t reserved_32_63:32;
1427#endif
54293ec3
DD		 1428 } s;
1429 struct cvmx_mio_fus_dat0_s cn30xx;
1430 struct cvmx_mio_fus_dat0_s cn31xx;
1431 struct cvmx_mio_fus_dat0_s cn38xx;
1432 struct cvmx_mio_fus_dat0_s cn38xxp2;
1433 struct cvmx_mio_fus_dat0_s cn50xx;
1434 struct cvmx_mio_fus_dat0_s cn52xx;
1435 struct cvmx_mio_fus_dat0_s cn52xxp1;
1436 struct cvmx_mio_fus_dat0_s cn56xx;
1437 struct cvmx_mio_fus_dat0_s cn56xxp1;
1438 struct cvmx_mio_fus_dat0_s cn58xx;
1439 struct cvmx_mio_fus_dat0_s cn58xxp1;
751c9f68 1440 struct cvmx_mio_fus_dat0_s cn61xx;
aa32a955
DD		 1441 struct cvmx_mio_fus_dat0_s cn63xx;
1442 struct cvmx_mio_fus_dat0_s cn63xxp1;
751c9f68
DD		 1443 struct cvmx_mio_fus_dat0_s cn66xx;
1444 struct cvmx_mio_fus_dat0_s cn68xx;
1445 struct cvmx_mio_fus_dat0_s cn68xxp1;
c5aa59e8 1446 struct cvmx_mio_fus_dat0_s cnf71xx;
54293ec3
DD		 1447};
1448
1449union cvmx_mio_fus_dat1 {
1450 uint64_t u64;
1451 struct cvmx_mio_fus_dat1_s {
c5aa59e8 1452#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1453 uint64_t reserved_32_63:32;
1454 uint64_t man_info:32;
c5aa59e8
DD		 1455#else
1456 uint64_t man_info:32;
1457 uint64_t reserved_32_63:32;
1458#endif
54293ec3
DD		 1459 } s;
1460 struct cvmx_mio_fus_dat1_s cn30xx;
1461 struct cvmx_mio_fus_dat1_s cn31xx;
1462 struct cvmx_mio_fus_dat1_s cn38xx;
1463 struct cvmx_mio_fus_dat1_s cn38xxp2;
1464 struct cvmx_mio_fus_dat1_s cn50xx;
1465 struct cvmx_mio_fus_dat1_s cn52xx;
1466 struct cvmx_mio_fus_dat1_s cn52xxp1;
1467 struct cvmx_mio_fus_dat1_s cn56xx;
1468 struct cvmx_mio_fus_dat1_s cn56xxp1;
1469 struct cvmx_mio_fus_dat1_s cn58xx;
1470 struct cvmx_mio_fus_dat1_s cn58xxp1;
751c9f68 1471 struct cvmx_mio_fus_dat1_s cn61xx;
aa32a955
DD		 1472 struct cvmx_mio_fus_dat1_s cn63xx;
1473 struct cvmx_mio_fus_dat1_s cn63xxp1;
751c9f68
DD		 1474 struct cvmx_mio_fus_dat1_s cn66xx;
1475 struct cvmx_mio_fus_dat1_s cn68xx;
1476 struct cvmx_mio_fus_dat1_s cn68xxp1;
c5aa59e8 1477 struct cvmx_mio_fus_dat1_s cnf71xx;
54293ec3
DD		 1478};
1479
1480union cvmx_mio_fus_dat2 {
1481 uint64_t u64;
1482 struct cvmx_mio_fus_dat2_s {
c5aa59e8 1483#ifdef __BIG_ENDIAN_BITFIELD
2df11221
DD		 1484 uint64_t reserved_59_63:5;
1485 uint64_t run_platform:3;
1486 uint64_t gbl_pwr_throttle:8;
751c9f68
DD		 1487 uint64_t fus118:1;
1488 uint64_t rom_info:10;
1489 uint64_t power_limit:2;
aa32a955 1490 uint64_t dorm_crypto:1;
54293ec3
DD		 1491 uint64_t fus318:1;
1492 uint64_t raid_en:1;
1493 uint64_t reserved_30_31:2;
1494 uint64_t nokasu:1;
1495 uint64_t nodfa_cp2:1;
1496 uint64_t nomul:1;
1497 uint64_t nocrypto:1;
1498 uint64_t rst_sht:1;
1499 uint64_t bist_dis:1;
1500 uint64_t chip_id:8;
1501 uint64_t reserved_0_15:16;
c5aa59e8
DD		 1502#else
1503 uint64_t reserved_0_15:16;
1504 uint64_t chip_id:8;
1505 uint64_t bist_dis:1;
1506 uint64_t rst_sht:1;
1507 uint64_t nocrypto:1;
1508 uint64_t nomul:1;
1509 uint64_t nodfa_cp2:1;
1510 uint64_t nokasu:1;
1511 uint64_t reserved_30_31:2;
1512 uint64_t raid_en:1;
1513 uint64_t fus318:1;
1514 uint64_t dorm_crypto:1;
1515 uint64_t power_limit:2;
1516 uint64_t rom_info:10;
1517 uint64_t fus118:1;
2df11221
DD		 1518 uint64_t gbl_pwr_throttle:8;
1519 uint64_t run_platform:3;
1520 uint64_t reserved_59_63:5;
c5aa59e8 1521#endif
54293ec3
DD		 1522 } s;
1523 struct cvmx_mio_fus_dat2_cn30xx {
c5aa59e8 1524#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1525 uint64_t reserved_29_63:35;
1526 uint64_t nodfa_cp2:1;
1527 uint64_t nomul:1;
1528 uint64_t nocrypto:1;
1529 uint64_t rst_sht:1;
1530 uint64_t bist_dis:1;
1531 uint64_t chip_id:8;
1532 uint64_t pll_off:4;
1533 uint64_t reserved_1_11:11;
1534 uint64_t pp_dis:1;
c5aa59e8
DD		 1535#else
1536 uint64_t pp_dis:1;
1537 uint64_t reserved_1_11:11;
1538 uint64_t pll_off:4;
1539 uint64_t chip_id:8;
1540 uint64_t bist_dis:1;
1541 uint64_t rst_sht:1;
1542 uint64_t nocrypto:1;
1543 uint64_t nomul:1;
1544 uint64_t nodfa_cp2:1;
1545 uint64_t reserved_29_63:35;
1546#endif
54293ec3
DD		 1547 } cn30xx;
1548 struct cvmx_mio_fus_dat2_cn31xx {
c5aa59e8 1549#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1550 uint64_t reserved_29_63:35;
1551 uint64_t nodfa_cp2:1;
1552 uint64_t nomul:1;
1553 uint64_t nocrypto:1;
1554 uint64_t rst_sht:1;
1555 uint64_t bist_dis:1;
1556 uint64_t chip_id:8;
1557 uint64_t pll_off:4;
1558 uint64_t reserved_2_11:10;
1559 uint64_t pp_dis:2;
c5aa59e8
DD		 1560#else
1561 uint64_t pp_dis:2;
1562 uint64_t reserved_2_11:10;
1563 uint64_t pll_off:4;
1564 uint64_t chip_id:8;
1565 uint64_t bist_dis:1;
1566 uint64_t rst_sht:1;
1567 uint64_t nocrypto:1;
1568 uint64_t nomul:1;
1569 uint64_t nodfa_cp2:1;
1570 uint64_t reserved_29_63:35;
1571#endif
54293ec3
DD		 1572 } cn31xx;
1573 struct cvmx_mio_fus_dat2_cn38xx {
c5aa59e8 1574#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1575 uint64_t reserved_29_63:35;
1576 uint64_t nodfa_cp2:1;
1577 uint64_t nomul:1;
1578 uint64_t nocrypto:1;
1579 uint64_t rst_sht:1;
1580 uint64_t bist_dis:1;
1581 uint64_t chip_id:8;
1582 uint64_t pp_dis:16;
c5aa59e8
DD		 1583#else
1584 uint64_t pp_dis:16;
1585 uint64_t chip_id:8;
1586 uint64_t bist_dis:1;
1587 uint64_t rst_sht:1;
1588 uint64_t nocrypto:1;
1589 uint64_t nomul:1;
1590 uint64_t nodfa_cp2:1;
1591 uint64_t reserved_29_63:35;
1592#endif
54293ec3
DD		 1593 } cn38xx;
1594 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
1595 struct cvmx_mio_fus_dat2_cn50xx {
c5aa59e8 1596#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1597 uint64_t reserved_34_63:30;
1598 uint64_t fus318:1;
1599 uint64_t raid_en:1;
1600 uint64_t reserved_30_31:2;
1601 uint64_t nokasu:1;
1602 uint64_t nodfa_cp2:1;
1603 uint64_t nomul:1;
1604 uint64_t nocrypto:1;
1605 uint64_t rst_sht:1;
1606 uint64_t bist_dis:1;
1607 uint64_t chip_id:8;
1608 uint64_t reserved_2_15:14;
1609 uint64_t pp_dis:2;
c5aa59e8
DD		 1610#else
1611 uint64_t pp_dis:2;
1612 uint64_t reserved_2_15:14;
1613 uint64_t chip_id:8;
1614 uint64_t bist_dis:1;
1615 uint64_t rst_sht:1;
1616 uint64_t nocrypto:1;
1617 uint64_t nomul:1;
1618 uint64_t nodfa_cp2:1;
1619 uint64_t nokasu:1;
1620 uint64_t reserved_30_31:2;
1621 uint64_t raid_en:1;
1622 uint64_t fus318:1;
1623 uint64_t reserved_34_63:30;
1624#endif
54293ec3
DD		 1625 } cn50xx;
1626 struct cvmx_mio_fus_dat2_cn52xx {
c5aa59e8 1627#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1628 uint64_t reserved_34_63:30;
1629 uint64_t fus318:1;
1630 uint64_t raid_en:1;
1631 uint64_t reserved_30_31:2;
1632 uint64_t nokasu:1;
1633 uint64_t nodfa_cp2:1;
1634 uint64_t nomul:1;
1635 uint64_t nocrypto:1;
1636 uint64_t rst_sht:1;
1637 uint64_t bist_dis:1;
1638 uint64_t chip_id:8;
1639 uint64_t reserved_4_15:12;
1640 uint64_t pp_dis:4;
c5aa59e8
DD		 1641#else
1642 uint64_t pp_dis:4;
1643 uint64_t reserved_4_15:12;
1644 uint64_t chip_id:8;
1645 uint64_t bist_dis:1;
1646 uint64_t rst_sht:1;
1647 uint64_t nocrypto:1;
1648 uint64_t nomul:1;
1649 uint64_t nodfa_cp2:1;
1650 uint64_t nokasu:1;
1651 uint64_t reserved_30_31:2;
1652 uint64_t raid_en:1;
1653 uint64_t fus318:1;
1654 uint64_t reserved_34_63:30;
1655#endif
54293ec3
DD		 1656 } cn52xx;
1657 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
1658 struct cvmx_mio_fus_dat2_cn56xx {
c5aa59e8 1659#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1660 uint64_t reserved_34_63:30;
1661 uint64_t fus318:1;
1662 uint64_t raid_en:1;
1663 uint64_t reserved_30_31:2;
1664 uint64_t nokasu:1;
1665 uint64_t nodfa_cp2:1;
1666 uint64_t nomul:1;
1667 uint64_t nocrypto:1;
1668 uint64_t rst_sht:1;
1669 uint64_t bist_dis:1;
1670 uint64_t chip_id:8;
1671 uint64_t reserved_12_15:4;
1672 uint64_t pp_dis:12;
c5aa59e8
DD		 1673#else
1674 uint64_t pp_dis:12;
1675 uint64_t reserved_12_15:4;
1676 uint64_t chip_id:8;
1677 uint64_t bist_dis:1;
1678 uint64_t rst_sht:1;
1679 uint64_t nocrypto:1;
1680 uint64_t nomul:1;
1681 uint64_t nodfa_cp2:1;
1682 uint64_t nokasu:1;
1683 uint64_t reserved_30_31:2;
1684 uint64_t raid_en:1;
1685 uint64_t fus318:1;
1686 uint64_t reserved_34_63:30;
1687#endif
54293ec3
DD		 1688 } cn56xx;
1689 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
1690 struct cvmx_mio_fus_dat2_cn58xx {
c5aa59e8 1691#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 1692 uint64_t reserved_30_63:34;
1693 uint64_t nokasu:1;
1694 uint64_t nodfa_cp2:1;
1695 uint64_t nomul:1;
1696 uint64_t nocrypto:1;
1697 uint64_t rst_sht:1;
1698 uint64_t bist_dis:1;
1699 uint64_t chip_id:8;
1700 uint64_t pp_dis:16;
c5aa59e8
DD		 1701#else
1702 uint64_t pp_dis:16;
1703 uint64_t chip_id:8;
1704 uint64_t bist_dis:1;
1705 uint64_t rst_sht:1;
1706 uint64_t nocrypto:1;
1707 uint64_t nomul:1;
1708 uint64_t nodfa_cp2:1;
1709 uint64_t nokasu:1;
1710 uint64_t reserved_30_63:34;
1711#endif
54293ec3
DD		 1712 } cn58xx;
1713 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
751c9f68 1714 struct cvmx_mio_fus_dat2_cn61xx {
c5aa59e8 1715#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1716 uint64_t reserved_48_63:16;
1717 uint64_t fus118:1;
1718 uint64_t rom_info:10;
1719 uint64_t power_limit:2;
1720 uint64_t dorm_crypto:1;
1721 uint64_t fus318:1;
1722 uint64_t raid_en:1;
1723 uint64_t reserved_29_31:3;
1724 uint64_t nodfa_cp2:1;
1725 uint64_t nomul:1;
1726 uint64_t nocrypto:1;
1727 uint64_t reserved_24_25:2;
1728 uint64_t chip_id:8;
1729 uint64_t reserved_4_15:12;
1730 uint64_t pp_dis:4;
c5aa59e8
DD		 1731#else
1732 uint64_t pp_dis:4;
1733 uint64_t reserved_4_15:12;
1734 uint64_t chip_id:8;
1735 uint64_t reserved_24_25:2;
1736 uint64_t nocrypto:1;
1737 uint64_t nomul:1;
1738 uint64_t nodfa_cp2:1;
1739 uint64_t reserved_29_31:3;
1740 uint64_t raid_en:1;
1741 uint64_t fus318:1;
1742 uint64_t dorm_crypto:1;
1743 uint64_t power_limit:2;
1744 uint64_t rom_info:10;
1745 uint64_t fus118:1;
1746 uint64_t reserved_48_63:16;
1747#endif
751c9f68 1748 } cn61xx;
aa32a955 1749 struct cvmx_mio_fus_dat2_cn63xx {
c5aa59e8 1750#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 1751 uint64_t reserved_35_63:29;
1752 uint64_t dorm_crypto:1;
1753 uint64_t fus318:1;
1754 uint64_t raid_en:1;
1755 uint64_t reserved_29_31:3;
1756 uint64_t nodfa_cp2:1;
1757 uint64_t nomul:1;
1758 uint64_t nocrypto:1;
1759 uint64_t reserved_24_25:2;
1760 uint64_t chip_id:8;
1761 uint64_t reserved_6_15:10;
1762 uint64_t pp_dis:6;
c5aa59e8
DD		 1763#else
1764 uint64_t pp_dis:6;
1765 uint64_t reserved_6_15:10;
1766 uint64_t chip_id:8;
1767 uint64_t reserved_24_25:2;
1768 uint64_t nocrypto:1;
1769 uint64_t nomul:1;
1770 uint64_t nodfa_cp2:1;
1771 uint64_t reserved_29_31:3;
1772 uint64_t raid_en:1;
1773 uint64_t fus318:1;
1774 uint64_t dorm_crypto:1;
1775 uint64_t reserved_35_63:29;
1776#endif
aa32a955
DD		 1777 } cn63xx;
1778 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
751c9f68 1779 struct cvmx_mio_fus_dat2_cn66xx {
c5aa59e8 1780#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1781 uint64_t reserved_48_63:16;
1782 uint64_t fus118:1;
1783 uint64_t rom_info:10;
1784 uint64_t power_limit:2;
1785 uint64_t dorm_crypto:1;
1786 uint64_t fus318:1;
1787 uint64_t raid_en:1;
1788 uint64_t reserved_29_31:3;
1789 uint64_t nodfa_cp2:1;
1790 uint64_t nomul:1;
1791 uint64_t nocrypto:1;
1792 uint64_t reserved_24_25:2;
1793 uint64_t chip_id:8;
1794 uint64_t reserved_10_15:6;
1795 uint64_t pp_dis:10;
c5aa59e8
DD		 1796#else
1797 uint64_t pp_dis:10;
1798 uint64_t reserved_10_15:6;
1799 uint64_t chip_id:8;
1800 uint64_t reserved_24_25:2;
1801 uint64_t nocrypto:1;
1802 uint64_t nomul:1;
1803 uint64_t nodfa_cp2:1;
1804 uint64_t reserved_29_31:3;
1805 uint64_t raid_en:1;
1806 uint64_t fus318:1;
1807 uint64_t dorm_crypto:1;
1808 uint64_t power_limit:2;
1809 uint64_t rom_info:10;
1810 uint64_t fus118:1;
1811 uint64_t reserved_48_63:16;
1812#endif
751c9f68
DD		 1813 } cn66xx;
1814 struct cvmx_mio_fus_dat2_cn68xx {
c5aa59e8 1815#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 1816 uint64_t reserved_37_63:27;
1817 uint64_t power_limit:2;
1818 uint64_t dorm_crypto:1;
1819 uint64_t fus318:1;
1820 uint64_t raid_en:1;
1821 uint64_t reserved_29_31:3;
1822 uint64_t nodfa_cp2:1;
1823 uint64_t nomul:1;
1824 uint64_t nocrypto:1;
1825 uint64_t reserved_24_25:2;
1826 uint64_t chip_id:8;
1827 uint64_t reserved_0_15:16;
c5aa59e8
DD		 1828#else
1829 uint64_t reserved_0_15:16;
1830 uint64_t chip_id:8;
1831 uint64_t reserved_24_25:2;
1832 uint64_t nocrypto:1;
1833 uint64_t nomul:1;
1834 uint64_t nodfa_cp2:1;
1835 uint64_t reserved_29_31:3;
1836 uint64_t raid_en:1;
1837 uint64_t fus318:1;
1838 uint64_t dorm_crypto:1;
1839 uint64_t power_limit:2;
1840 uint64_t reserved_37_63:27;
1841#endif
751c9f68
DD		 1842 } cn68xx;
1843 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
2df11221
DD		 1844 struct cvmx_mio_fus_dat2_cn70xx {
1845#ifdef __BIG_ENDIAN_BITFIELD
1846 uint64_t reserved_48_63:16;
1847 uint64_t fus118:1;
1848 uint64_t rom_info:10;
1849 uint64_t power_limit:2;
1850 uint64_t dorm_crypto:1;
1851 uint64_t fus318:1;
1852 uint64_t raid_en:1;
1853 uint64_t reserved_31_29:3;
1854 uint64_t nodfa_cp2:1;
1855 uint64_t nomul:1;
1856 uint64_t nocrypto:1;
1857 uint64_t reserved_25_24:2;
1858 uint64_t chip_id:8;
1859 uint64_t reserved_15_0:16;
1860#else
1861 uint64_t reserved_15_0:16;
1862 uint64_t chip_id:8;
1863 uint64_t reserved_25_24:2;
1864 uint64_t nocrypto:1;
1865 uint64_t nomul:1;
1866 uint64_t nodfa_cp2:1;
1867 uint64_t reserved_31_29:3;
1868 uint64_t raid_en:1;
1869 uint64_t fus318:1;
1870 uint64_t dorm_crypto:1;
1871 uint64_t power_limit:2;
1872 uint64_t rom_info:10;
1873 uint64_t fus118:1;
1874 uint64_t reserved_48_63:16;
1875#endif
1876 } cn70xx;
1877 struct cvmx_mio_fus_dat2_cn70xx cn70xxp1;
1878 struct cvmx_mio_fus_dat2_cn73xx {
1879#ifdef __BIG_ENDIAN_BITFIELD
1880 uint64_t reserved_59_63:5;
1881 uint64_t run_platform:3;
1882 uint64_t gbl_pwr_throttle:8;
1883 uint64_t fus118:1;
1884 uint64_t rom_info:10;
1885 uint64_t power_limit:2;
1886 uint64_t dorm_crypto:1;
1887 uint64_t fus318:1;
1888 uint64_t raid_en:1;
1889 uint64_t reserved_31_29:3;
1890 uint64_t nodfa_cp2:1;
1891 uint64_t nomul:1;
1892 uint64_t nocrypto:1;
1893 uint64_t reserved_25_24:2;
1894 uint64_t chip_id:8;
1895 uint64_t reserved_15_0:16;
1896#else
1897 uint64_t reserved_15_0:16;
1898 uint64_t chip_id:8;
1899 uint64_t reserved_25_24:2;
1900 uint64_t nocrypto:1;
1901 uint64_t nomul:1;
1902 uint64_t nodfa_cp2:1;
1903 uint64_t reserved_31_29:3;
1904 uint64_t raid_en:1;
1905 uint64_t fus318:1;
1906 uint64_t dorm_crypto:1;
1907 uint64_t power_limit:2;
1908 uint64_t rom_info:10;
1909 uint64_t fus118:1;
1910 uint64_t gbl_pwr_throttle:8;
1911 uint64_t run_platform:3;
1912 uint64_t reserved_59_63:5;
1913#endif
1914 } cn73xx;
1915 struct cvmx_mio_fus_dat2_cn78xx {
1916#ifdef __BIG_ENDIAN_BITFIELD
1917 uint64_t reserved_59_63:5;
1918 uint64_t run_platform:3;
1919 uint64_t reserved_48_55:8;
1920 uint64_t fus118:1;
1921 uint64_t rom_info:10;
1922 uint64_t power_limit:2;
1923 uint64_t dorm_crypto:1;
1924 uint64_t fus318:1;
1925 uint64_t raid_en:1;
1926 uint64_t reserved_31_29:3;
1927 uint64_t nodfa_cp2:1;
1928 uint64_t nomul:1;
1929 uint64_t nocrypto:1;
1930 uint64_t reserved_25_24:2;
1931 uint64_t chip_id:8;
1932 uint64_t reserved_0_15:16;
1933#else
1934 uint64_t reserved_0_15:16;
1935 uint64_t chip_id:8;
1936 uint64_t reserved_25_24:2;
1937 uint64_t nocrypto:1;
1938 uint64_t nomul:1;
1939 uint64_t nodfa_cp2:1;
1940 uint64_t reserved_31_29:3;
1941 uint64_t raid_en:1;
1942 uint64_t fus318:1;
1943 uint64_t dorm_crypto:1;
1944 uint64_t power_limit:2;
1945 uint64_t rom_info:10;
1946 uint64_t fus118:1;
1947 uint64_t reserved_48_55:8;
1948 uint64_t run_platform:3;
1949 uint64_t reserved_59_63:5;
1950#endif
1951 } cn78xx;
1952 struct cvmx_mio_fus_dat2_cn78xxp2 {
1953#ifdef __BIG_ENDIAN_BITFIELD
1954 uint64_t reserved_59_63:5;
1955 uint64_t run_platform:3;
1956 uint64_t gbl_pwr_throttle:8;
1957 uint64_t fus118:1;
1958 uint64_t rom_info:10;
1959 uint64_t power_limit:2;
1960 uint64_t dorm_crypto:1;
1961 uint64_t fus318:1;
1962 uint64_t raid_en:1;
1963 uint64_t reserved_31_29:3;
1964 uint64_t nodfa_cp2:1;
1965 uint64_t nomul:1;
1966 uint64_t nocrypto:1;
1967 uint64_t reserved_25_24:2;
1968 uint64_t chip_id:8;
1969 uint64_t reserved_0_15:16;
1970#else
1971 uint64_t reserved_0_15:16;
1972 uint64_t chip_id:8;
1973 uint64_t reserved_25_24:2;
1974 uint64_t nocrypto:1;
1975 uint64_t nomul:1;
1976 uint64_t nodfa_cp2:1;
1977 uint64_t reserved_31_29:3;
1978 uint64_t raid_en:1;
1979 uint64_t fus318:1;
1980 uint64_t dorm_crypto:1;
1981 uint64_t power_limit:2;
1982 uint64_t rom_info:10;
1983 uint64_t fus118:1;
1984 uint64_t gbl_pwr_throttle:8;
1985 uint64_t run_platform:3;
1986 uint64_t reserved_59_63:5;
1987#endif
1988 } cn78xxp2;
c5aa59e8 1989 struct cvmx_mio_fus_dat2_cn61xx cnf71xx;
2df11221 1990 struct cvmx_mio_fus_dat2_cn73xx cnf75xx;
54293ec3
DD		 1991};
1992
1993union cvmx_mio_fus_dat3 {
1994 uint64_t u64;
1995 struct cvmx_mio_fus_dat3_s {
c5aa59e8 1996#ifdef __BIG_ENDIAN_BITFIELD
2df11221 1997 uint64_t ema0:6;
aa32a955
DD		 1998 uint64_t pll_ctl:10;
1999 uint64_t dfa_info_dte:3;
2000 uint64_t dfa_info_clm:4;
2df11221
DD		 2001 uint64_t pll_alt_matrix:1;
2002 uint64_t reserved_38_39:2;
aa32a955
DD		 2003 uint64_t efus_lck_rsv:1;
2004 uint64_t efus_lck_man:1;
2005 uint64_t pll_half_dis:1;
2006 uint64_t l2c_crip:3;
2df11221 2007 uint64_t reserved_28_31:4;
54293ec3
DD		 2008 uint64_t efus_lck:1;
2009 uint64_t efus_ign:1;
2010 uint64_t nozip:1;
2011 uint64_t nodfa_dte:1;
2df11221 2012 uint64_t reserved_0_23:24;
c5aa59e8 2013#else
2df11221 2014 uint64_t reserved_0_23:24;
c5aa59e8
DD		 2015 uint64_t nodfa_dte:1;
2016 uint64_t nozip:1;
2017 uint64_t efus_ign:1;
2018 uint64_t efus_lck:1;
2df11221 2019 uint64_t reserved_28_31:4;
c5aa59e8
DD		 2020 uint64_t l2c_crip:3;
2021 uint64_t pll_half_dis:1;
2022 uint64_t efus_lck_man:1;
2023 uint64_t efus_lck_rsv:1;
2df11221
DD		 2024 uint64_t reserved_38_39:2;
2025 uint64_t pll_alt_matrix:1;
c5aa59e8
DD		 2026 uint64_t dfa_info_clm:4;
2027 uint64_t dfa_info_dte:3;
2028 uint64_t pll_ctl:10;
2df11221 2029 uint64_t ema0:6;
c5aa59e8 2030#endif
54293ec3
DD		 2031 } s;
2032 struct cvmx_mio_fus_dat3_cn30xx {
c5aa59e8 2033#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2034 uint64_t reserved_32_63:32;
2035 uint64_t pll_div4:1;
2036 uint64_t reserved_29_30:2;
2037 uint64_t bar2_en:1;
2038 uint64_t efus_lck:1;
2039 uint64_t efus_ign:1;
2040 uint64_t nozip:1;
2041 uint64_t nodfa_dte:1;
2042 uint64_t icache:24;
c5aa59e8
DD		 2043#else
2044 uint64_t icache:24;
2045 uint64_t nodfa_dte:1;
2046 uint64_t nozip:1;
2047 uint64_t efus_ign:1;
2048 uint64_t efus_lck:1;
2049 uint64_t bar2_en:1;
2050 uint64_t reserved_29_30:2;
2051 uint64_t pll_div4:1;
2052 uint64_t reserved_32_63:32;
2053#endif
54293ec3 2054 } cn30xx;
aa32a955 2055 struct cvmx_mio_fus_dat3_cn31xx {
c5aa59e8 2056#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2057 uint64_t reserved_32_63:32;
2058 uint64_t pll_div4:1;
2059 uint64_t zip_crip:2;
2060 uint64_t bar2_en:1;
2061 uint64_t efus_lck:1;
2062 uint64_t efus_ign:1;
2063 uint64_t nozip:1;
2064 uint64_t nodfa_dte:1;
2065 uint64_t icache:24;
c5aa59e8
DD		 2066#else
2067 uint64_t icache:24;
2068 uint64_t nodfa_dte:1;
2069 uint64_t nozip:1;
2070 uint64_t efus_ign:1;
2071 uint64_t efus_lck:1;
2072 uint64_t bar2_en:1;
2073 uint64_t zip_crip:2;
2074 uint64_t pll_div4:1;
2075 uint64_t reserved_32_63:32;
2076#endif
aa32a955 2077 } cn31xx;
54293ec3 2078 struct cvmx_mio_fus_dat3_cn38xx {
c5aa59e8 2079#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2080 uint64_t reserved_31_63:33;
2081 uint64_t zip_crip:2;
2082 uint64_t bar2_en:1;
2083 uint64_t efus_lck:1;
2084 uint64_t efus_ign:1;
2085 uint64_t nozip:1;
2086 uint64_t nodfa_dte:1;
2087 uint64_t icache:24;
c5aa59e8
DD		 2088#else
2089 uint64_t icache:24;
2090 uint64_t nodfa_dte:1;
2091 uint64_t nozip:1;
2092 uint64_t efus_ign:1;
2093 uint64_t efus_lck:1;
2094 uint64_t bar2_en:1;
2095 uint64_t zip_crip:2;
2096 uint64_t reserved_31_63:33;
2097#endif
54293ec3
DD		 2098 } cn38xx;
2099 struct cvmx_mio_fus_dat3_cn38xxp2 {
c5aa59e8 2100#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2101 uint64_t reserved_29_63:35;
2102 uint64_t bar2_en:1;
2103 uint64_t efus_lck:1;
2104 uint64_t efus_ign:1;
2105 uint64_t nozip:1;
2106 uint64_t nodfa_dte:1;
2107 uint64_t icache:24;
c5aa59e8
DD		 2108#else
2109 uint64_t icache:24;
2110 uint64_t nodfa_dte:1;
2111 uint64_t nozip:1;
2112 uint64_t efus_ign:1;
2113 uint64_t efus_lck:1;
2114 uint64_t bar2_en:1;
2115 uint64_t reserved_29_63:35;
2116#endif
54293ec3
DD		 2117 } cn38xxp2;
2118 struct cvmx_mio_fus_dat3_cn38xx cn50xx;
2119 struct cvmx_mio_fus_dat3_cn38xx cn52xx;
2120 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
2121 struct cvmx_mio_fus_dat3_cn38xx cn56xx;
2122 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
2123 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
2124 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
751c9f68 2125 struct cvmx_mio_fus_dat3_cn61xx {
c5aa59e8 2126#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2127 uint64_t reserved_58_63:6;
2128 uint64_t pll_ctl:10;
2129 uint64_t dfa_info_dte:3;
2130 uint64_t dfa_info_clm:4;
2131 uint64_t reserved_40_40:1;
2132 uint64_t ema:2;
2133 uint64_t efus_lck_rsv:1;
2134 uint64_t efus_lck_man:1;
2135 uint64_t pll_half_dis:1;
2136 uint64_t l2c_crip:3;
2137 uint64_t reserved_31_31:1;
2138 uint64_t zip_info:2;
2139 uint64_t bar2_en:1;
2140 uint64_t efus_lck:1;
2141 uint64_t efus_ign:1;
2142 uint64_t nozip:1;
2143 uint64_t nodfa_dte:1;
2144 uint64_t reserved_0_23:24;
c5aa59e8
DD		 2145#else
2146 uint64_t reserved_0_23:24;
2147 uint64_t nodfa_dte:1;
2148 uint64_t nozip:1;
2149 uint64_t efus_ign:1;
2150 uint64_t efus_lck:1;
2151 uint64_t bar2_en:1;
2152 uint64_t zip_info:2;
2153 uint64_t reserved_31_31:1;
2154 uint64_t l2c_crip:3;
2155 uint64_t pll_half_dis:1;
2156 uint64_t efus_lck_man:1;
2157 uint64_t efus_lck_rsv:1;
2158 uint64_t ema:2;
2159 uint64_t reserved_40_40:1;
2160 uint64_t dfa_info_clm:4;
2161 uint64_t dfa_info_dte:3;
2162 uint64_t pll_ctl:10;
2163 uint64_t reserved_58_63:6;
2164#endif
751c9f68
DD		 2165 } cn61xx;
2166 struct cvmx_mio_fus_dat3_cn61xx cn63xx;
2167 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
2168 struct cvmx_mio_fus_dat3_cn61xx cn66xx;
2169 struct cvmx_mio_fus_dat3_cn61xx cn68xx;
2170 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
2df11221
DD		 2171 struct cvmx_mio_fus_dat3_cn70xx {
2172#ifdef __BIG_ENDIAN_BITFIELD
2173 uint64_t ema0:6;
2174 uint64_t pll_ctl:10;
2175 uint64_t dfa_info_dte:3;
2176 uint64_t dfa_info_clm:4;
2177 uint64_t pll_alt_matrix:1;
2178 uint64_t pll_bwadj_denom:2;
2179 uint64_t efus_lck_rsv:1;
2180 uint64_t efus_lck_man:1;
2181 uint64_t pll_half_dis:1;
2182 uint64_t l2c_crip:3;
2183 uint64_t use_int_refclk:1;
2184 uint64_t zip_info:2;
2185 uint64_t bar2_sz_conf:1;
2186 uint64_t efus_lck:1;
2187 uint64_t efus_ign:1;
2188 uint64_t nozip:1;
2189 uint64_t nodfa_dte:1;
2190 uint64_t ema1:6;
2191 uint64_t reserved_0_17:18;
2192#else
2193 uint64_t reserved_0_17:18;
2194 uint64_t ema1:6;
2195 uint64_t nodfa_dte:1;
2196 uint64_t nozip:1;
2197 uint64_t efus_ign:1;
2198 uint64_t efus_lck:1;
2199 uint64_t bar2_sz_conf:1;
2200 uint64_t zip_info:2;
2201 uint64_t use_int_refclk:1;
2202 uint64_t l2c_crip:3;
2203 uint64_t pll_half_dis:1;
2204 uint64_t efus_lck_man:1;
2205 uint64_t efus_lck_rsv:1;
2206 uint64_t pll_bwadj_denom:2;
2207 uint64_t pll_alt_matrix:1;
2208 uint64_t dfa_info_clm:4;
2209 uint64_t dfa_info_dte:3;
2210 uint64_t pll_ctl:10;
2211 uint64_t ema0:6;
2212#endif
2213 } cn70xx;
2214 struct cvmx_mio_fus_dat3_cn70xxp1 {
2215#ifdef __BIG_ENDIAN_BITFIELD
2216 uint64_t ema0:6;
2217 uint64_t pll_ctl:10;
2218 uint64_t dfa_info_dte:3;
2219 uint64_t dfa_info_clm:4;
2220 uint64_t reserved_38_40:3;
2221 uint64_t efus_lck_rsv:1;
2222 uint64_t efus_lck_man:1;
2223 uint64_t pll_half_dis:1;
2224 uint64_t l2c_crip:3;
2225 uint64_t reserved_31_31:1;
2226 uint64_t zip_info:2;
2227 uint64_t bar2_sz_conf:1;
2228 uint64_t efus_lck:1;
2229 uint64_t efus_ign:1;
2230 uint64_t nozip:1;
2231 uint64_t nodfa_dte:1;
2232 uint64_t ema1:6;
2233 uint64_t reserved_0_17:18;
2234#else
2235 uint64_t reserved_0_17:18;
2236 uint64_t ema1:6;
2237 uint64_t nodfa_dte:1;
2238 uint64_t nozip:1;
2239 uint64_t efus_ign:1;
2240 uint64_t efus_lck:1;
2241 uint64_t bar2_sz_conf:1;
2242 uint64_t zip_info:2;
2243 uint64_t reserved_31_31:1;
2244 uint64_t l2c_crip:3;
2245 uint64_t pll_half_dis:1;
2246 uint64_t efus_lck_man:1;
2247 uint64_t efus_lck_rsv:1;
2248 uint64_t reserved_38_40:3;
2249 uint64_t dfa_info_clm:4;
2250 uint64_t dfa_info_dte:3;
2251 uint64_t pll_ctl:10;
2252 uint64_t ema0:6;
2253#endif
2254 } cn70xxp1;
2255 struct cvmx_mio_fus_dat3_cn73xx {
2256#ifdef __BIG_ENDIAN_BITFIELD
2257 uint64_t ema0:6;
2258 uint64_t pll_ctl:10;
2259 uint64_t dfa_info_dte:3;
2260 uint64_t dfa_info_clm:4;
2261 uint64_t pll_alt_matrix:1;
2262 uint64_t pll_bwadj_denom:2;
2263 uint64_t efus_lck_rsv:1;
2264 uint64_t efus_lck_man:1;
2265 uint64_t pll_half_dis:1;
2266 uint64_t l2c_crip:3;
2267 uint64_t use_int_refclk:1;
2268 uint64_t zip_info:2;
2269 uint64_t bar2_sz_conf:1;
2270 uint64_t efus_lck:1;
2271 uint64_t efus_ign:1;
2272 uint64_t nozip:1;
2273 uint64_t nodfa_dte:1;
2274 uint64_t ema1:6;
2275 uint64_t nohna_dte:1;
2276 uint64_t hna_info_dte:3;
2277 uint64_t hna_info_clm:4;
2278 uint64_t reserved_9_9:1;
2279 uint64_t core_pll_mul:5;
2280 uint64_t pnr_pll_mul:4;
2281#else
2282 uint64_t pnr_pll_mul:4;
2283 uint64_t core_pll_mul:5;
2284 uint64_t reserved_9_9:1;
2285 uint64_t hna_info_clm:4;
2286 uint64_t hna_info_dte:3;
2287 uint64_t nohna_dte:1;
2288 uint64_t ema1:6;
2289 uint64_t nodfa_dte:1;
2290 uint64_t nozip:1;
2291 uint64_t efus_ign:1;
2292 uint64_t efus_lck:1;
2293 uint64_t bar2_sz_conf:1;
2294 uint64_t zip_info:2;
2295 uint64_t use_int_refclk:1;
2296 uint64_t l2c_crip:3;
2297 uint64_t pll_half_dis:1;
2298 uint64_t efus_lck_man:1;
2299 uint64_t efus_lck_rsv:1;
2300 uint64_t pll_bwadj_denom:2;
2301 uint64_t pll_alt_matrix:1;
2302 uint64_t dfa_info_clm:4;
2303 uint64_t dfa_info_dte:3;
2304 uint64_t pll_ctl:10;
2305 uint64_t ema0:6;
2306#endif
2307 } cn73xx;
2308 struct cvmx_mio_fus_dat3_cn78xx {
2309#ifdef __BIG_ENDIAN_BITFIELD
2310 uint64_t ema0:6;
2311 uint64_t pll_ctl:10;
2312 uint64_t dfa_info_dte:3;
2313 uint64_t dfa_info_clm:4;
2314 uint64_t reserved_38_40:3;
2315 uint64_t efus_lck_rsv:1;
2316 uint64_t efus_lck_man:1;
2317 uint64_t pll_half_dis:1;
2318 uint64_t l2c_crip:3;
2319 uint64_t reserved_31_31:1;
2320 uint64_t zip_info:2;
2321 uint64_t bar2_sz_conf:1;
2322 uint64_t efus_lck:1;
2323 uint64_t efus_ign:1;
2324 uint64_t nozip:1;
2325 uint64_t nodfa_dte:1;
2326 uint64_t ema1:6;
2327 uint64_t nohna_dte:1;
2328 uint64_t hna_info_dte:3;
2329 uint64_t hna_info_clm:4;
2330 uint64_t reserved_0_9:10;
2331#else
2332 uint64_t reserved_0_9:10;
2333 uint64_t hna_info_clm:4;
2334 uint64_t hna_info_dte:3;
2335 uint64_t nohna_dte:1;
2336 uint64_t ema1:6;
2337 uint64_t nodfa_dte:1;
2338 uint64_t nozip:1;
2339 uint64_t efus_ign:1;
2340 uint64_t efus_lck:1;
2341 uint64_t bar2_sz_conf:1;
2342 uint64_t zip_info:2;
2343 uint64_t reserved_31_31:1;
2344 uint64_t l2c_crip:3;
2345 uint64_t pll_half_dis:1;
2346 uint64_t efus_lck_man:1;
2347 uint64_t efus_lck_rsv:1;
2348 uint64_t reserved_38_40:3;
2349 uint64_t dfa_info_clm:4;
2350 uint64_t dfa_info_dte:3;
2351 uint64_t pll_ctl:10;
2352 uint64_t ema0:6;
2353#endif
2354 } cn78xx;
2355 struct cvmx_mio_fus_dat3_cn73xx cn78xxp2;
c5aa59e8 2356 struct cvmx_mio_fus_dat3_cn61xx cnf71xx;
2df11221
DD		 2357 struct cvmx_mio_fus_dat3_cnf75xx {
2358#ifdef __BIG_ENDIAN_BITFIELD
2359 uint64_t ema0:6;
2360 uint64_t pll_ctl:10;
2361 uint64_t dfa_info_dte:3;
2362 uint64_t dfa_info_clm:4;
2363 uint64_t pll_alt_matrix:1;
2364 uint64_t pll_bwadj_denom:2;
2365 uint64_t efus_lck_rsv:1;
2366 uint64_t efus_lck_man:1;
2367 uint64_t pll_half_dis:1;
2368 uint64_t l2c_crip:3;
2369 uint64_t use_int_refclk:1;
2370 uint64_t zip_info:2;
2371 uint64_t bar2_sz_conf:1;
2372 uint64_t efus_lck:1;
2373 uint64_t efus_ign:1;
2374 uint64_t nozip:1;
2375 uint64_t nodfa_dte:1;
2376 uint64_t ema1:6;
2377 uint64_t reserved_9_17:9;
2378 uint64_t core_pll_mul:5;
2379 uint64_t pnr_pll_mul:4;
2380#else
2381 uint64_t pnr_pll_mul:4;
2382 uint64_t core_pll_mul:5;
2383 uint64_t reserved_9_17:9;
2384 uint64_t ema1:6;
2385 uint64_t nodfa_dte:1;
2386 uint64_t nozip:1;
2387 uint64_t efus_ign:1;
2388 uint64_t efus_lck:1;
2389 uint64_t bar2_sz_conf:1;
2390 uint64_t zip_info:2;
2391 uint64_t use_int_refclk:1;
2392 uint64_t l2c_crip:3;
2393 uint64_t pll_half_dis:1;
2394 uint64_t efus_lck_man:1;
2395 uint64_t efus_lck_rsv:1;
2396 uint64_t pll_bwadj_denom:2;
2397 uint64_t pll_alt_matrix:1;
2398 uint64_t dfa_info_clm:4;
2399 uint64_t dfa_info_dte:3;
2400 uint64_t pll_ctl:10;
2401 uint64_t ema0:6;
2402#endif
2403 } cnf75xx;
54293ec3
DD		 2404};
2405
2406union cvmx_mio_fus_ema {
2407 uint64_t u64;
2408 struct cvmx_mio_fus_ema_s {
c5aa59e8 2409#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2410 uint64_t reserved_7_63:57;
2411 uint64_t eff_ema:3;
2412 uint64_t reserved_3_3:1;
2413 uint64_t ema:3;
c5aa59e8
DD		 2414#else
2415 uint64_t ema:3;
2416 uint64_t reserved_3_3:1;
2417 uint64_t eff_ema:3;
2418 uint64_t reserved_7_63:57;
2419#endif
54293ec3
DD		 2420 } s;
2421 struct cvmx_mio_fus_ema_s cn50xx;
2422 struct cvmx_mio_fus_ema_s cn52xx;
2423 struct cvmx_mio_fus_ema_s cn52xxp1;
2424 struct cvmx_mio_fus_ema_s cn56xx;
2425 struct cvmx_mio_fus_ema_s cn56xxp1;
2426 struct cvmx_mio_fus_ema_cn58xx {
c5aa59e8 2427#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2428 uint64_t reserved_2_63:62;
2429 uint64_t ema:2;
c5aa59e8
DD		 2430#else
2431 uint64_t ema:2;
2432 uint64_t reserved_2_63:62;
2433#endif
54293ec3
DD		 2434 } cn58xx;
2435 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
751c9f68 2436 struct cvmx_mio_fus_ema_s cn61xx;
aa32a955
DD		 2437 struct cvmx_mio_fus_ema_s cn63xx;
2438 struct cvmx_mio_fus_ema_s cn63xxp1;
751c9f68
DD		 2439 struct cvmx_mio_fus_ema_s cn66xx;
2440 struct cvmx_mio_fus_ema_s cn68xx;
2441 struct cvmx_mio_fus_ema_s cn68xxp1;
c5aa59e8 2442 struct cvmx_mio_fus_ema_s cnf71xx;
54293ec3
DD		 2443};
2444
2445union cvmx_mio_fus_pdf {
2446 uint64_t u64;
2447 struct cvmx_mio_fus_pdf_s {
c5aa59e8 2448#ifdef __BIG_ENDIAN_BITFIELD
54293ec3 2449 uint64_t pdf:64;
c5aa59e8
DD		 2450#else
2451 uint64_t pdf:64;
2452#endif
54293ec3
DD		 2453 } s;
2454 struct cvmx_mio_fus_pdf_s cn50xx;
2455 struct cvmx_mio_fus_pdf_s cn52xx;
2456 struct cvmx_mio_fus_pdf_s cn52xxp1;
2457 struct cvmx_mio_fus_pdf_s cn56xx;
2458 struct cvmx_mio_fus_pdf_s cn56xxp1;
2459 struct cvmx_mio_fus_pdf_s cn58xx;
751c9f68 2460 struct cvmx_mio_fus_pdf_s cn61xx;
aa32a955
DD		 2461 struct cvmx_mio_fus_pdf_s cn63xx;
2462 struct cvmx_mio_fus_pdf_s cn63xxp1;
751c9f68
DD		 2463 struct cvmx_mio_fus_pdf_s cn66xx;
2464 struct cvmx_mio_fus_pdf_s cn68xx;
2465 struct cvmx_mio_fus_pdf_s cn68xxp1;
c5aa59e8 2466 struct cvmx_mio_fus_pdf_s cnf71xx;
54293ec3
DD		 2467};
2468
2469union cvmx_mio_fus_pll {
2470 uint64_t u64;
2471 struct cvmx_mio_fus_pll_s {
c5aa59e8 2472#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 2473 uint64_t reserved_48_63:16;
2474 uint64_t rclk_align_r:8;
2475 uint64_t rclk_align_l:8;
2476 uint64_t reserved_8_31:24;
aa32a955
DD		 2477 uint64_t c_cout_rst:1;
2478 uint64_t c_cout_sel:2;
2479 uint64_t pnr_cout_rst:1;
2480 uint64_t pnr_cout_sel:2;
54293ec3
DD		 2481 uint64_t rfslip:1;
2482 uint64_t fbslip:1;
c5aa59e8
DD		 2483#else
2484 uint64_t fbslip:1;
2485 uint64_t rfslip:1;
2486 uint64_t pnr_cout_sel:2;
2487 uint64_t pnr_cout_rst:1;
2488 uint64_t c_cout_sel:2;
2489 uint64_t c_cout_rst:1;
2490 uint64_t reserved_8_31:24;
2491 uint64_t rclk_align_l:8;
2492 uint64_t rclk_align_r:8;
2493 uint64_t reserved_48_63:16;
2494#endif
54293ec3 2495 } s;
aa32a955 2496 struct cvmx_mio_fus_pll_cn50xx {
c5aa59e8 2497#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2498 uint64_t reserved_2_63:62;
2499 uint64_t rfslip:1;
2500 uint64_t fbslip:1;
c5aa59e8
DD		 2501#else
2502 uint64_t fbslip:1;
2503 uint64_t rfslip:1;
2504 uint64_t reserved_2_63:62;
2505#endif
aa32a955
DD		 2506 } cn50xx;
2507 struct cvmx_mio_fus_pll_cn50xx cn52xx;
2508 struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
2509 struct cvmx_mio_fus_pll_cn50xx cn56xx;
2510 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
2511 struct cvmx_mio_fus_pll_cn50xx cn58xx;
2512 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
751c9f68 2513 struct cvmx_mio_fus_pll_cn61xx {
c5aa59e8 2514#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 2515 uint64_t reserved_8_63:56;
2516 uint64_t c_cout_rst:1;
2517 uint64_t c_cout_sel:2;
2518 uint64_t pnr_cout_rst:1;
2519 uint64_t pnr_cout_sel:2;
2520 uint64_t rfslip:1;
2521 uint64_t fbslip:1;
c5aa59e8
DD		 2522#else
2523 uint64_t fbslip:1;
2524 uint64_t rfslip:1;
2525 uint64_t pnr_cout_sel:2;
2526 uint64_t pnr_cout_rst:1;
2527 uint64_t c_cout_sel:2;
2528 uint64_t c_cout_rst:1;
2529 uint64_t reserved_8_63:56;
2530#endif
751c9f68
DD		 2531 } cn61xx;
2532 struct cvmx_mio_fus_pll_cn61xx cn63xx;
2533 struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
2534 struct cvmx_mio_fus_pll_cn61xx cn66xx;
2535 struct cvmx_mio_fus_pll_s cn68xx;
2536 struct cvmx_mio_fus_pll_s cn68xxp1;
c5aa59e8 2537 struct cvmx_mio_fus_pll_cn61xx cnf71xx;
54293ec3
DD		 2538};
2539
2540union cvmx_mio_fus_prog {
2541 uint64_t u64;
2542 struct cvmx_mio_fus_prog_s {
c5aa59e8 2543#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2544 uint64_t reserved_2_63:62;
2545 uint64_t soft:1;
54293ec3 2546 uint64_t prog:1;
c5aa59e8
DD		 2547#else
2548 uint64_t prog:1;
2549 uint64_t soft:1;
2550 uint64_t reserved_2_63:62;
2551#endif
54293ec3 2552 } s;
aa32a955 2553 struct cvmx_mio_fus_prog_cn30xx {
c5aa59e8 2554#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2555 uint64_t reserved_1_63:63;
2556 uint64_t prog:1;
c5aa59e8
DD		 2557#else
2558 uint64_t prog:1;
2559 uint64_t reserved_1_63:63;
2560#endif
aa32a955
DD		 2561 } cn30xx;
2562 struct cvmx_mio_fus_prog_cn30xx cn31xx;
2563 struct cvmx_mio_fus_prog_cn30xx cn38xx;
2564 struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
2565 struct cvmx_mio_fus_prog_cn30xx cn50xx;
2566 struct cvmx_mio_fus_prog_cn30xx cn52xx;
2567 struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
2568 struct cvmx_mio_fus_prog_cn30xx cn56xx;
2569 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
2570 struct cvmx_mio_fus_prog_cn30xx cn58xx;
2571 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
751c9f68 2572 struct cvmx_mio_fus_prog_s cn61xx;
aa32a955
DD		 2573 struct cvmx_mio_fus_prog_s cn63xx;
2574 struct cvmx_mio_fus_prog_s cn63xxp1;
751c9f68
DD		 2575 struct cvmx_mio_fus_prog_s cn66xx;
2576 struct cvmx_mio_fus_prog_s cn68xx;
2577 struct cvmx_mio_fus_prog_s cn68xxp1;
c5aa59e8 2578 struct cvmx_mio_fus_prog_s cnf71xx;
54293ec3
DD		 2579};
2580
2581union cvmx_mio_fus_prog_times {
2582 uint64_t u64;
2583 struct cvmx_mio_fus_prog_times_s {
c5aa59e8 2584#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2585 uint64_t reserved_35_63:29;
2586 uint64_t vgate_pin:1;
2587 uint64_t fsrc_pin:1;
2588 uint64_t prog_pin:1;
2589 uint64_t reserved_6_31:26;
2590 uint64_t setup:6;
c5aa59e8
DD		 2591#else
2592 uint64_t setup:6;
2593 uint64_t reserved_6_31:26;
2594 uint64_t prog_pin:1;
2595 uint64_t fsrc_pin:1;
2596 uint64_t vgate_pin:1;
2597 uint64_t reserved_35_63:29;
2598#endif
aa32a955
DD		 2599 } s;
2600 struct cvmx_mio_fus_prog_times_cn50xx {
c5aa59e8 2601#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2602 uint64_t reserved_33_63:31;
2603 uint64_t prog_pin:1;
2604 uint64_t out:8;
2605 uint64_t sclk_lo:4;
2606 uint64_t sclk_hi:12;
2607 uint64_t setup:8;
c5aa59e8
DD		 2608#else
2609 uint64_t setup:8;
2610 uint64_t sclk_hi:12;
2611 uint64_t sclk_lo:4;
2612 uint64_t out:8;
2613 uint64_t prog_pin:1;
2614 uint64_t reserved_33_63:31;
2615#endif
aa32a955
DD		 2616 } cn50xx;
2617 struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
2618 struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
2619 struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
2620 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
2621 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
2622 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
751c9f68 2623 struct cvmx_mio_fus_prog_times_cn61xx {
c5aa59e8 2624#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2625 uint64_t reserved_35_63:29;
2626 uint64_t vgate_pin:1;
2627 uint64_t fsrc_pin:1;
2628 uint64_t prog_pin:1;
2629 uint64_t out:7;
2630 uint64_t sclk_lo:4;
2631 uint64_t sclk_hi:15;
2632 uint64_t setup:6;
c5aa59e8
DD		 2633#else
2634 uint64_t setup:6;
2635 uint64_t sclk_hi:15;
2636 uint64_t sclk_lo:4;
2637 uint64_t out:7;
2638 uint64_t prog_pin:1;
2639 uint64_t fsrc_pin:1;
2640 uint64_t vgate_pin:1;
2641 uint64_t reserved_35_63:29;
2642#endif
751c9f68
DD		 2643 } cn61xx;
2644 struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
2645 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
2646 struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
2647 struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
2648 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
c5aa59e8 2649 struct cvmx_mio_fus_prog_times_cn61xx cnf71xx;
54293ec3
DD		 2650};
2651
2652union cvmx_mio_fus_rcmd {
2653 uint64_t u64;
2654 struct cvmx_mio_fus_rcmd_s {
c5aa59e8 2655#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2656 uint64_t reserved_24_63:40;
2657 uint64_t dat:8;
2658 uint64_t reserved_13_15:3;
2659 uint64_t pend:1;
2660 uint64_t reserved_9_11:3;
2661 uint64_t efuse:1;
2662 uint64_t addr:8;
c5aa59e8
DD		 2663#else
2664 uint64_t addr:8;
2665 uint64_t efuse:1;
2666 uint64_t reserved_9_11:3;
2667 uint64_t pend:1;
2668 uint64_t reserved_13_15:3;
2669 uint64_t dat:8;
2670 uint64_t reserved_24_63:40;
2671#endif
54293ec3
DD		 2672 } s;
2673 struct cvmx_mio_fus_rcmd_cn30xx {
c5aa59e8 2674#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2675 uint64_t reserved_24_63:40;
2676 uint64_t dat:8;
2677 uint64_t reserved_13_15:3;
2678 uint64_t pend:1;
2679 uint64_t reserved_9_11:3;
2680 uint64_t efuse:1;
2681 uint64_t reserved_7_7:1;
2682 uint64_t addr:7;
c5aa59e8
DD		 2683#else
2684 uint64_t addr:7;
2685 uint64_t reserved_7_7:1;
2686 uint64_t efuse:1;
2687 uint64_t reserved_9_11:3;
2688 uint64_t pend:1;
2689 uint64_t reserved_13_15:3;
2690 uint64_t dat:8;
2691 uint64_t reserved_24_63:40;
2692#endif
54293ec3
DD		 2693 } cn30xx;
2694 struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
2695 struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
2696 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
2697 struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
2698 struct cvmx_mio_fus_rcmd_s cn52xx;
2699 struct cvmx_mio_fus_rcmd_s cn52xxp1;
2700 struct cvmx_mio_fus_rcmd_s cn56xx;
2701 struct cvmx_mio_fus_rcmd_s cn56xxp1;
2702 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
2703 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
751c9f68 2704 struct cvmx_mio_fus_rcmd_s cn61xx;
aa32a955
DD		 2705 struct cvmx_mio_fus_rcmd_s cn63xx;
2706 struct cvmx_mio_fus_rcmd_s cn63xxp1;
751c9f68
DD		 2707 struct cvmx_mio_fus_rcmd_s cn66xx;
2708 struct cvmx_mio_fus_rcmd_s cn68xx;
2709 struct cvmx_mio_fus_rcmd_s cn68xxp1;
c5aa59e8 2710 struct cvmx_mio_fus_rcmd_s cnf71xx;
aa32a955
DD		 2711};
2712
2713union cvmx_mio_fus_read_times {
2714 uint64_t u64;
2715 struct cvmx_mio_fus_read_times_s {
c5aa59e8 2716#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2717 uint64_t reserved_26_63:38;
2718 uint64_t sch:4;
2719 uint64_t fsh:4;
2720 uint64_t prh:4;
2721 uint64_t sdh:4;
2722 uint64_t setup:10;
c5aa59e8
DD		 2723#else
2724 uint64_t setup:10;
2725 uint64_t sdh:4;
2726 uint64_t prh:4;
2727 uint64_t fsh:4;
2728 uint64_t sch:4;
2729 uint64_t reserved_26_63:38;
2730#endif
aa32a955 2731 } s;
751c9f68 2732 struct cvmx_mio_fus_read_times_s cn61xx;
aa32a955
DD		 2733 struct cvmx_mio_fus_read_times_s cn63xx;
2734 struct cvmx_mio_fus_read_times_s cn63xxp1;
751c9f68
DD		 2735 struct cvmx_mio_fus_read_times_s cn66xx;
2736 struct cvmx_mio_fus_read_times_s cn68xx;
2737 struct cvmx_mio_fus_read_times_s cn68xxp1;
c5aa59e8 2738 struct cvmx_mio_fus_read_times_s cnf71xx;
aa32a955
DD		 2739};
2740
2741union cvmx_mio_fus_repair_res0 {
2742 uint64_t u64;
2743 struct cvmx_mio_fus_repair_res0_s {
c5aa59e8 2744#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2745 uint64_t reserved_55_63:9;
2746 uint64_t too_many:1;
2747 uint64_t repair2:18;
2748 uint64_t repair1:18;
2749 uint64_t repair0:18;
c5aa59e8
DD		 2750#else
2751 uint64_t repair0:18;
2752 uint64_t repair1:18;
2753 uint64_t repair2:18;
2754 uint64_t too_many:1;
2755 uint64_t reserved_55_63:9;
2756#endif
aa32a955 2757 } s;
751c9f68 2758 struct cvmx_mio_fus_repair_res0_s cn61xx;
aa32a955
DD		 2759 struct cvmx_mio_fus_repair_res0_s cn63xx;
2760 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
751c9f68
DD		 2761 struct cvmx_mio_fus_repair_res0_s cn66xx;
2762 struct cvmx_mio_fus_repair_res0_s cn68xx;
2763 struct cvmx_mio_fus_repair_res0_s cn68xxp1;
c5aa59e8 2764 struct cvmx_mio_fus_repair_res0_s cnf71xx;
aa32a955
DD		 2765};
2766
2767union cvmx_mio_fus_repair_res1 {
2768 uint64_t u64;
2769 struct cvmx_mio_fus_repair_res1_s {
c5aa59e8 2770#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2771 uint64_t reserved_54_63:10;
2772 uint64_t repair5:18;
2773 uint64_t repair4:18;
2774 uint64_t repair3:18;
c5aa59e8
DD		 2775#else
2776 uint64_t repair3:18;
2777 uint64_t repair4:18;
2778 uint64_t repair5:18;
2779 uint64_t reserved_54_63:10;
2780#endif
aa32a955 2781 } s;
751c9f68 2782 struct cvmx_mio_fus_repair_res1_s cn61xx;
aa32a955
DD		 2783 struct cvmx_mio_fus_repair_res1_s cn63xx;
2784 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
751c9f68
DD		 2785 struct cvmx_mio_fus_repair_res1_s cn66xx;
2786 struct cvmx_mio_fus_repair_res1_s cn68xx;
2787 struct cvmx_mio_fus_repair_res1_s cn68xxp1;
c5aa59e8 2788 struct cvmx_mio_fus_repair_res1_s cnf71xx;
aa32a955
DD		 2789};
2790
2791union cvmx_mio_fus_repair_res2 {
2792 uint64_t u64;
2793 struct cvmx_mio_fus_repair_res2_s {
c5aa59e8 2794#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2795 uint64_t reserved_18_63:46;
2796 uint64_t repair6:18;
c5aa59e8
DD		 2797#else
2798 uint64_t repair6:18;
2799 uint64_t reserved_18_63:46;
2800#endif
aa32a955 2801 } s;
751c9f68 2802 struct cvmx_mio_fus_repair_res2_s cn61xx;
aa32a955
DD		 2803 struct cvmx_mio_fus_repair_res2_s cn63xx;
2804 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
751c9f68
DD		 2805 struct cvmx_mio_fus_repair_res2_s cn66xx;
2806 struct cvmx_mio_fus_repair_res2_s cn68xx;
2807 struct cvmx_mio_fus_repair_res2_s cn68xxp1;
c5aa59e8 2808 struct cvmx_mio_fus_repair_res2_s cnf71xx;
54293ec3
DD		 2809};
2810
2811union cvmx_mio_fus_spr_repair_res {
2812 uint64_t u64;
2813 struct cvmx_mio_fus_spr_repair_res_s {
c5aa59e8 2814#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2815 uint64_t reserved_42_63:22;
2816 uint64_t repair2:14;
2817 uint64_t repair1:14;
2818 uint64_t repair0:14;
c5aa59e8
DD		 2819#else
2820 uint64_t repair0:14;
2821 uint64_t repair1:14;
2822 uint64_t repair2:14;
2823 uint64_t reserved_42_63:22;
2824#endif
54293ec3
DD		 2825 } s;
2826 struct cvmx_mio_fus_spr_repair_res_s cn30xx;
2827 struct cvmx_mio_fus_spr_repair_res_s cn31xx;
2828 struct cvmx_mio_fus_spr_repair_res_s cn38xx;
2829 struct cvmx_mio_fus_spr_repair_res_s cn50xx;
2830 struct cvmx_mio_fus_spr_repair_res_s cn52xx;
2831 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
2832 struct cvmx_mio_fus_spr_repair_res_s cn56xx;
2833 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
2834 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
2835 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
751c9f68 2836 struct cvmx_mio_fus_spr_repair_res_s cn61xx;
aa32a955
DD		 2837 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
2838 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
751c9f68
DD		 2839 struct cvmx_mio_fus_spr_repair_res_s cn66xx;
2840 struct cvmx_mio_fus_spr_repair_res_s cn68xx;
2841 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
c5aa59e8 2842 struct cvmx_mio_fus_spr_repair_res_s cnf71xx;
54293ec3
DD		 2843};
2844
2845union cvmx_mio_fus_spr_repair_sum {
2846 uint64_t u64;
2847 struct cvmx_mio_fus_spr_repair_sum_s {
c5aa59e8 2848#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2849 uint64_t reserved_1_63:63;
2850 uint64_t too_many:1;
c5aa59e8
DD		 2851#else
2852 uint64_t too_many:1;
2853 uint64_t reserved_1_63:63;
2854#endif
54293ec3
DD		 2855 } s;
2856 struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
2857 struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
2858 struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
2859 struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
2860 struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
2861 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
2862 struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
2863 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
2864 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
2865 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
751c9f68 2866 struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
aa32a955
DD		 2867 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
2868 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
751c9f68
DD		 2869 struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
2870 struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
2871 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
c5aa59e8 2872 struct cvmx_mio_fus_spr_repair_sum_s cnf71xx;
751c9f68
DD		 2873};
2874
2875union cvmx_mio_fus_tgg {
2876 uint64_t u64;
2877 struct cvmx_mio_fus_tgg_s {
c5aa59e8 2878#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 2879 uint64_t val:1;
2880 uint64_t dat:63;
c5aa59e8
DD		 2881#else
2882 uint64_t dat:63;
2883 uint64_t val:1;
2884#endif
751c9f68
DD		 2885 } s;
2886 struct cvmx_mio_fus_tgg_s cn61xx;
2887 struct cvmx_mio_fus_tgg_s cn66xx;
c5aa59e8 2888 struct cvmx_mio_fus_tgg_s cnf71xx;
54293ec3
DD		 2889};
2890
2891union cvmx_mio_fus_unlock {
2892 uint64_t u64;
2893 struct cvmx_mio_fus_unlock_s {
c5aa59e8 2894#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2895 uint64_t reserved_24_63:40;
2896 uint64_t key:24;
c5aa59e8
DD		 2897#else
2898 uint64_t key:24;
2899 uint64_t reserved_24_63:40;
2900#endif
54293ec3
DD		 2901 } s;
2902 struct cvmx_mio_fus_unlock_s cn30xx;
2903 struct cvmx_mio_fus_unlock_s cn31xx;
2904};
2905
2906union cvmx_mio_fus_wadr {
2907 uint64_t u64;
2908 struct cvmx_mio_fus_wadr_s {
c5aa59e8 2909#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2910 uint64_t reserved_10_63:54;
2911 uint64_t addr:10;
c5aa59e8
DD		 2912#else
2913 uint64_t addr:10;
2914 uint64_t reserved_10_63:54;
2915#endif
54293ec3
DD		 2916 } s;
2917 struct cvmx_mio_fus_wadr_s cn30xx;
2918 struct cvmx_mio_fus_wadr_s cn31xx;
2919 struct cvmx_mio_fus_wadr_s cn38xx;
2920 struct cvmx_mio_fus_wadr_s cn38xxp2;
2921 struct cvmx_mio_fus_wadr_cn50xx {
c5aa59e8 2922#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2923 uint64_t reserved_2_63:62;
2924 uint64_t addr:2;
c5aa59e8
DD		 2925#else
2926 uint64_t addr:2;
2927 uint64_t reserved_2_63:62;
2928#endif
54293ec3
DD		 2929 } cn50xx;
2930 struct cvmx_mio_fus_wadr_cn52xx {
c5aa59e8 2931#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2932 uint64_t reserved_3_63:61;
2933 uint64_t addr:3;
c5aa59e8
DD		 2934#else
2935 uint64_t addr:3;
2936 uint64_t reserved_3_63:61;
2937#endif
54293ec3
DD		 2938 } cn52xx;
2939 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
2940 struct cvmx_mio_fus_wadr_cn52xx cn56xx;
2941 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
2942 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
2943 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
751c9f68 2944 struct cvmx_mio_fus_wadr_cn61xx {
c5aa59e8 2945#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2946 uint64_t reserved_4_63:60;
2947 uint64_t addr:4;
c5aa59e8
DD		 2948#else
2949 uint64_t addr:4;
2950 uint64_t reserved_4_63:60;
2951#endif
751c9f68
DD		 2952 } cn61xx;
2953 struct cvmx_mio_fus_wadr_cn61xx cn63xx;
2954 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
2955 struct cvmx_mio_fus_wadr_cn61xx cn66xx;
2956 struct cvmx_mio_fus_wadr_cn61xx cn68xx;
2957 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
c5aa59e8 2958 struct cvmx_mio_fus_wadr_cn61xx cnf71xx;
aa32a955
DD		 2959};
2960
2961union cvmx_mio_gpio_comp {
2962 uint64_t u64;
2963 struct cvmx_mio_gpio_comp_s {
c5aa59e8 2964#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 2965 uint64_t reserved_12_63:52;
2966 uint64_t pctl:6;
2967 uint64_t nctl:6;
c5aa59e8
DD		 2968#else
2969 uint64_t nctl:6;
2970 uint64_t pctl:6;
2971 uint64_t reserved_12_63:52;
2972#endif
aa32a955 2973 } s;
751c9f68 2974 struct cvmx_mio_gpio_comp_s cn61xx;
aa32a955
DD		 2975 struct cvmx_mio_gpio_comp_s cn63xx;
2976 struct cvmx_mio_gpio_comp_s cn63xxp1;
751c9f68
DD		 2977 struct cvmx_mio_gpio_comp_s cn66xx;
2978 struct cvmx_mio_gpio_comp_s cn68xx;
2979 struct cvmx_mio_gpio_comp_s cn68xxp1;
c5aa59e8 2980 struct cvmx_mio_gpio_comp_s cnf71xx;
54293ec3
DD		 2981};
2982
2983union cvmx_mio_ndf_dma_cfg {
2984 uint64_t u64;
2985 struct cvmx_mio_ndf_dma_cfg_s {
c5aa59e8 2986#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 2987 uint64_t en:1;
2988 uint64_t rw:1;
2989 uint64_t clr:1;
2990 uint64_t reserved_60_60:1;
2991 uint64_t swap32:1;
2992 uint64_t swap16:1;
2993 uint64_t swap8:1;
2994 uint64_t endian:1;
2995 uint64_t size:20;
2996 uint64_t adr:36;
c5aa59e8
DD		 2997#else
2998 uint64_t adr:36;
2999 uint64_t size:20;
3000 uint64_t endian:1;
3001 uint64_t swap8:1;
3002 uint64_t swap16:1;
3003 uint64_t swap32:1;
3004 uint64_t reserved_60_60:1;
3005 uint64_t clr:1;
3006 uint64_t rw:1;
3007 uint64_t en:1;
3008#endif
54293ec3
DD		 3009 } s;
3010 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
751c9f68 3011 struct cvmx_mio_ndf_dma_cfg_s cn61xx;
aa32a955
DD		 3012 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
3013 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
751c9f68
DD		 3014 struct cvmx_mio_ndf_dma_cfg_s cn66xx;
3015 struct cvmx_mio_ndf_dma_cfg_s cn68xx;
3016 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
c5aa59e8 3017 struct cvmx_mio_ndf_dma_cfg_s cnf71xx;
54293ec3
DD		 3018};
3019
3020union cvmx_mio_ndf_dma_int {
3021 uint64_t u64;
3022 struct cvmx_mio_ndf_dma_int_s {
c5aa59e8 3023#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 3024 uint64_t reserved_1_63:63;
3025 uint64_t done:1;
c5aa59e8
DD		 3026#else
3027 uint64_t done:1;
3028 uint64_t reserved_1_63:63;
3029#endif
54293ec3
DD		 3030 } s;
3031 struct cvmx_mio_ndf_dma_int_s cn52xx;
751c9f68 3032 struct cvmx_mio_ndf_dma_int_s cn61xx;
aa32a955
DD		 3033 struct cvmx_mio_ndf_dma_int_s cn63xx;
3034 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
751c9f68
DD		 3035 struct cvmx_mio_ndf_dma_int_s cn66xx;
3036 struct cvmx_mio_ndf_dma_int_s cn68xx;
3037 struct cvmx_mio_ndf_dma_int_s cn68xxp1;
c5aa59e8 3038 struct cvmx_mio_ndf_dma_int_s cnf71xx;
54293ec3
DD		 3039};
3040
3041union cvmx_mio_ndf_dma_int_en {
3042 uint64_t u64;
3043 struct cvmx_mio_ndf_dma_int_en_s {
c5aa59e8 3044#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 3045 uint64_t reserved_1_63:63;
3046 uint64_t done:1;
c5aa59e8
DD		 3047#else
3048 uint64_t done:1;
3049 uint64_t reserved_1_63:63;
3050#endif
54293ec3
DD		 3051 } s;
3052 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
751c9f68 3053 struct cvmx_mio_ndf_dma_int_en_s cn61xx;
aa32a955
DD		 3054 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
3055 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
751c9f68
DD		 3056 struct cvmx_mio_ndf_dma_int_en_s cn66xx;
3057 struct cvmx_mio_ndf_dma_int_en_s cn68xx;
3058 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
c5aa59e8 3059 struct cvmx_mio_ndf_dma_int_en_s cnf71xx;
54293ec3
DD		 3060};
3061
3062union cvmx_mio_pll_ctl {
3063 uint64_t u64;
3064 struct cvmx_mio_pll_ctl_s {
c5aa59e8 3065#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 3066 uint64_t reserved_5_63:59;
3067 uint64_t bw_ctl:5;
c5aa59e8
DD		 3068#else
3069 uint64_t bw_ctl:5;
3070 uint64_t reserved_5_63:59;
3071#endif
54293ec3
DD		 3072 } s;
3073 struct cvmx_mio_pll_ctl_s cn30xx;
3074 struct cvmx_mio_pll_ctl_s cn31xx;
3075};
3076
3077union cvmx_mio_pll_setting {
3078 uint64_t u64;
3079 struct cvmx_mio_pll_setting_s {
c5aa59e8 3080#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 3081 uint64_t reserved_17_63:47;
3082 uint64_t setting:17;
c5aa59e8
DD		 3083#else
3084 uint64_t setting:17;
3085 uint64_t reserved_17_63:47;
3086#endif
3087 } s;
54293ec3
DD		 3088 struct cvmx_mio_pll_setting_s cn30xx;
3089 struct cvmx_mio_pll_setting_s cn31xx;
3090};
3091
751c9f68
DD		 3092union cvmx_mio_ptp_ckout_hi_incr {
3093 uint64_t u64;
3094 struct cvmx_mio_ptp_ckout_hi_incr_s {
c5aa59e8 3095#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3096 uint64_t nanosec:32;
3097 uint64_t frnanosec:32;
c5aa59e8
DD		 3098#else
3099 uint64_t frnanosec:32;
3100 uint64_t nanosec:32;
3101#endif
751c9f68
DD		 3102 } s;
3103 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
3104 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
3105 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
c5aa59e8 3106 struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx;
751c9f68
DD		 3107};
3108
3109union cvmx_mio_ptp_ckout_lo_incr {
3110 uint64_t u64;
3111 struct cvmx_mio_ptp_ckout_lo_incr_s {
c5aa59e8 3112#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3113 uint64_t nanosec:32;
3114 uint64_t frnanosec:32;
c5aa59e8
DD		 3115#else
3116 uint64_t frnanosec:32;
3117 uint64_t nanosec:32;
3118#endif
751c9f68
DD		 3119 } s;
3120 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
3121 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
3122 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
c5aa59e8 3123 struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx;
751c9f68
DD		 3124};
3125
3126union cvmx_mio_ptp_ckout_thresh_hi {
3127 uint64_t u64;
3128 struct cvmx_mio_ptp_ckout_thresh_hi_s {
c5aa59e8
DD		 3129#ifdef __BIG_ENDIAN_BITFIELD
3130 uint64_t nanosec:64;
3131#else
751c9f68 3132 uint64_t nanosec:64;
c5aa59e8 3133#endif
751c9f68
DD		 3134 } s;
3135 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
3136 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
3137 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
c5aa59e8 3138 struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx;
751c9f68
DD		 3139};
3140
3141union cvmx_mio_ptp_ckout_thresh_lo {
3142 uint64_t u64;
3143 struct cvmx_mio_ptp_ckout_thresh_lo_s {
c5aa59e8 3144#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3145 uint64_t reserved_32_63:32;
3146 uint64_t frnanosec:32;
c5aa59e8
DD		 3147#else
3148 uint64_t frnanosec:32;
3149 uint64_t reserved_32_63:32;
3150#endif
751c9f68
DD		 3151 } s;
3152 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
3153 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
3154 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
c5aa59e8 3155 struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx;
751c9f68
DD		 3156};
3157
aa32a955
DD		 3158union cvmx_mio_ptp_clock_cfg {
3159 uint64_t u64;
3160 struct cvmx_mio_ptp_clock_cfg_s {
c5aa59e8 3161#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3162 uint64_t reserved_42_63:22;
3163 uint64_t pps:1;
3164 uint64_t ckout:1;
3165 uint64_t ext_clk_edge:2;
3166 uint64_t ckout_out4:1;
3167 uint64_t pps_out:5;
3168 uint64_t pps_inv:1;
3169 uint64_t pps_en:1;
3170 uint64_t ckout_out:4;
3171 uint64_t ckout_inv:1;
3172 uint64_t ckout_en:1;
aa32a955
DD		 3173 uint64_t evcnt_in:6;
3174 uint64_t evcnt_edge:1;
3175 uint64_t evcnt_en:1;
3176 uint64_t tstmp_in:6;
3177 uint64_t tstmp_edge:1;
3178 uint64_t tstmp_en:1;
3179 uint64_t ext_clk_in:6;
3180 uint64_t ext_clk_en:1;
3181 uint64_t ptp_en:1;
c5aa59e8
DD		 3182#else
3183 uint64_t ptp_en:1;
3184 uint64_t ext_clk_en:1;
3185 uint64_t ext_clk_in:6;
3186 uint64_t tstmp_en:1;
3187 uint64_t tstmp_edge:1;
3188 uint64_t tstmp_in:6;
3189 uint64_t evcnt_en:1;
3190 uint64_t evcnt_edge:1;
3191 uint64_t evcnt_in:6;
3192 uint64_t ckout_en:1;
3193 uint64_t ckout_inv:1;
3194 uint64_t ckout_out:4;
3195 uint64_t pps_en:1;
3196 uint64_t pps_inv:1;
3197 uint64_t pps_out:5;
3198 uint64_t ckout_out4:1;
3199 uint64_t ext_clk_edge:2;
3200 uint64_t ckout:1;
3201 uint64_t pps:1;
3202 uint64_t reserved_42_63:22;
3203#endif
aa32a955 3204 } s;
751c9f68
DD		 3205 struct cvmx_mio_ptp_clock_cfg_s cn61xx;
3206 struct cvmx_mio_ptp_clock_cfg_cn63xx {
c5aa59e8 3207#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3208 uint64_t reserved_24_63:40;
3209 uint64_t evcnt_in:6;
3210 uint64_t evcnt_edge:1;
3211 uint64_t evcnt_en:1;
3212 uint64_t tstmp_in:6;
3213 uint64_t tstmp_edge:1;
3214 uint64_t tstmp_en:1;
3215 uint64_t ext_clk_in:6;
3216 uint64_t ext_clk_en:1;
3217 uint64_t ptp_en:1;
c5aa59e8
DD		 3218#else
3219 uint64_t ptp_en:1;
3220 uint64_t ext_clk_en:1;
3221 uint64_t ext_clk_in:6;
3222 uint64_t tstmp_en:1;
3223 uint64_t tstmp_edge:1;
3224 uint64_t tstmp_in:6;
3225 uint64_t evcnt_en:1;
3226 uint64_t evcnt_edge:1;
3227 uint64_t evcnt_in:6;
3228 uint64_t reserved_24_63:40;
3229#endif
751c9f68
DD		 3230 } cn63xx;
3231 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
3232 struct cvmx_mio_ptp_clock_cfg_cn66xx {
c5aa59e8 3233#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3234 uint64_t reserved_40_63:24;
3235 uint64_t ext_clk_edge:2;
3236 uint64_t ckout_out4:1;
3237 uint64_t pps_out:5;
3238 uint64_t pps_inv:1;
3239 uint64_t pps_en:1;
3240 uint64_t ckout_out:4;
3241 uint64_t ckout_inv:1;
3242 uint64_t ckout_en:1;
3243 uint64_t evcnt_in:6;
3244 uint64_t evcnt_edge:1;
3245 uint64_t evcnt_en:1;
3246 uint64_t tstmp_in:6;
3247 uint64_t tstmp_edge:1;
3248 uint64_t tstmp_en:1;
3249 uint64_t ext_clk_in:6;
3250 uint64_t ext_clk_en:1;
3251 uint64_t ptp_en:1;
c5aa59e8
DD		 3252#else
3253 uint64_t ptp_en:1;
3254 uint64_t ext_clk_en:1;
3255 uint64_t ext_clk_in:6;
3256 uint64_t tstmp_en:1;
3257 uint64_t tstmp_edge:1;
3258 uint64_t tstmp_in:6;
3259 uint64_t evcnt_en:1;
3260 uint64_t evcnt_edge:1;
3261 uint64_t evcnt_in:6;
3262 uint64_t ckout_en:1;
3263 uint64_t ckout_inv:1;
3264 uint64_t ckout_out:4;
3265 uint64_t pps_en:1;
3266 uint64_t pps_inv:1;
3267 uint64_t pps_out:5;
3268 uint64_t ckout_out4:1;
3269 uint64_t ext_clk_edge:2;
3270 uint64_t reserved_40_63:24;
3271#endif
751c9f68
DD		 3272 } cn66xx;
3273 struct cvmx_mio_ptp_clock_cfg_s cn68xx;
3274 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
c5aa59e8 3275 struct cvmx_mio_ptp_clock_cfg_s cnf71xx;
aa32a955
DD		 3276};
3277
3278union cvmx_mio_ptp_clock_comp {
3279 uint64_t u64;
3280 struct cvmx_mio_ptp_clock_comp_s {
c5aa59e8 3281#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3282 uint64_t nanosec:32;
3283 uint64_t frnanosec:32;
c5aa59e8
DD		 3284#else
3285 uint64_t frnanosec:32;
3286 uint64_t nanosec:32;
3287#endif
aa32a955 3288 } s;
751c9f68 3289 struct cvmx_mio_ptp_clock_comp_s cn61xx;
aa32a955
DD		 3290 struct cvmx_mio_ptp_clock_comp_s cn63xx;
3291 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
751c9f68
DD		 3292 struct cvmx_mio_ptp_clock_comp_s cn66xx;
3293 struct cvmx_mio_ptp_clock_comp_s cn68xx;
3294 struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
c5aa59e8 3295 struct cvmx_mio_ptp_clock_comp_s cnf71xx;
aa32a955
DD		 3296};
3297
3298union cvmx_mio_ptp_clock_hi {
3299 uint64_t u64;
3300 struct cvmx_mio_ptp_clock_hi_s {
c5aa59e8 3301#ifdef __BIG_ENDIAN_BITFIELD
aa32a955 3302 uint64_t nanosec:64;
c5aa59e8
DD		 3303#else
3304 uint64_t nanosec:64;
3305#endif
aa32a955 3306 } s;
751c9f68 3307 struct cvmx_mio_ptp_clock_hi_s cn61xx;
aa32a955
DD		 3308 struct cvmx_mio_ptp_clock_hi_s cn63xx;
3309 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
751c9f68
DD		 3310 struct cvmx_mio_ptp_clock_hi_s cn66xx;
3311 struct cvmx_mio_ptp_clock_hi_s cn68xx;
3312 struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
c5aa59e8 3313 struct cvmx_mio_ptp_clock_hi_s cnf71xx;
aa32a955
DD		 3314};
3315
3316union cvmx_mio_ptp_clock_lo {
3317 uint64_t u64;
3318 struct cvmx_mio_ptp_clock_lo_s {
c5aa59e8 3319#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3320 uint64_t reserved_32_63:32;
3321 uint64_t frnanosec:32;
c5aa59e8
DD		 3322#else
3323 uint64_t frnanosec:32;
3324 uint64_t reserved_32_63:32;
3325#endif
aa32a955 3326 } s;
751c9f68 3327 struct cvmx_mio_ptp_clock_lo_s cn61xx;
aa32a955
DD		 3328 struct cvmx_mio_ptp_clock_lo_s cn63xx;
3329 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
751c9f68
DD		 3330 struct cvmx_mio_ptp_clock_lo_s cn66xx;
3331 struct cvmx_mio_ptp_clock_lo_s cn68xx;
3332 struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
c5aa59e8 3333 struct cvmx_mio_ptp_clock_lo_s cnf71xx;
aa32a955
DD		 3334};
3335
3336union cvmx_mio_ptp_evt_cnt {
3337 uint64_t u64;
3338 struct cvmx_mio_ptp_evt_cnt_s {
c5aa59e8
DD		 3339#ifdef __BIG_ENDIAN_BITFIELD
3340 uint64_t cntr:64;
3341#else
aa32a955 3342 uint64_t cntr:64;
c5aa59e8 3343#endif
aa32a955 3344 } s;
751c9f68 3345 struct cvmx_mio_ptp_evt_cnt_s cn61xx;
aa32a955
DD		 3346 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
3347 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
751c9f68
DD		 3348 struct cvmx_mio_ptp_evt_cnt_s cn66xx;
3349 struct cvmx_mio_ptp_evt_cnt_s cn68xx;
3350 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
c5aa59e8
DD		 3351 struct cvmx_mio_ptp_evt_cnt_s cnf71xx;
3352};
3353
3354union cvmx_mio_ptp_phy_1pps_in {
3355 uint64_t u64;
3356 struct cvmx_mio_ptp_phy_1pps_in_s {
3357#ifdef __BIG_ENDIAN_BITFIELD
3358 uint64_t reserved_5_63:59;
3359 uint64_t sel:5;
3360#else
3361 uint64_t sel:5;
3362 uint64_t reserved_5_63:59;
3363#endif
3364 } s;
3365 struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx;
751c9f68
DD		 3366};
3367
3368union cvmx_mio_ptp_pps_hi_incr {
3369 uint64_t u64;
3370 struct cvmx_mio_ptp_pps_hi_incr_s {
c5aa59e8 3371#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3372 uint64_t nanosec:32;
3373 uint64_t frnanosec:32;
c5aa59e8
DD		 3374#else
3375 uint64_t frnanosec:32;
3376 uint64_t nanosec:32;
3377#endif
751c9f68
DD		 3378 } s;
3379 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
3380 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
3381 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
c5aa59e8 3382 struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx;
751c9f68
DD		 3383};
3384
3385union cvmx_mio_ptp_pps_lo_incr {
3386 uint64_t u64;
3387 struct cvmx_mio_ptp_pps_lo_incr_s {
c5aa59e8 3388#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3389 uint64_t nanosec:32;
3390 uint64_t frnanosec:32;
c5aa59e8
DD		 3391#else
3392 uint64_t frnanosec:32;
3393 uint64_t nanosec:32;
3394#endif
751c9f68
DD		 3395 } s;
3396 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
3397 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
3398 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
c5aa59e8 3399 struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx;
751c9f68
DD		 3400};
3401
3402union cvmx_mio_ptp_pps_thresh_hi {
3403 uint64_t u64;
3404 struct cvmx_mio_ptp_pps_thresh_hi_s {
c5aa59e8 3405#ifdef __BIG_ENDIAN_BITFIELD
751c9f68 3406 uint64_t nanosec:64;
c5aa59e8
DD		 3407#else
3408 uint64_t nanosec:64;
3409#endif
751c9f68
DD		 3410 } s;
3411 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
3412 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
3413 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
c5aa59e8 3414 struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx;
751c9f68
DD		 3415};
3416
3417union cvmx_mio_ptp_pps_thresh_lo {
3418 uint64_t u64;
3419 struct cvmx_mio_ptp_pps_thresh_lo_s {
c5aa59e8 3420#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3421 uint64_t reserved_32_63:32;
3422 uint64_t frnanosec:32;
c5aa59e8
DD		 3423#else
3424 uint64_t frnanosec:32;
3425 uint64_t reserved_32_63:32;
3426#endif
751c9f68
DD		 3427 } s;
3428 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
3429 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
3430 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
c5aa59e8 3431 struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx;
aa32a955
DD		 3432};
3433
3434union cvmx_mio_ptp_timestamp {
3435 uint64_t u64;
3436 struct cvmx_mio_ptp_timestamp_s {
c5aa59e8 3437#ifdef __BIG_ENDIAN_BITFIELD
aa32a955 3438 uint64_t nanosec:64;
c5aa59e8
DD		 3439#else
3440 uint64_t nanosec:64;
3441#endif
aa32a955 3442 } s;
751c9f68 3443 struct cvmx_mio_ptp_timestamp_s cn61xx;
aa32a955
DD		 3444 struct cvmx_mio_ptp_timestamp_s cn63xx;
3445 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
751c9f68
DD		 3446 struct cvmx_mio_ptp_timestamp_s cn66xx;
3447 struct cvmx_mio_ptp_timestamp_s cn68xx;
3448 struct cvmx_mio_ptp_timestamp_s cn68xxp1;
c5aa59e8 3449 struct cvmx_mio_ptp_timestamp_s cnf71xx;
751c9f68
DD		 3450};
3451
3452union cvmx_mio_qlmx_cfg {
3453 uint64_t u64;
3454 struct cvmx_mio_qlmx_cfg_s {
c5aa59e8
DD		 3455#ifdef __BIG_ENDIAN_BITFIELD
3456 uint64_t reserved_15_63:49;
3457 uint64_t prtmode:1;
3458 uint64_t reserved_12_13:2;
751c9f68
DD		 3459 uint64_t qlm_spd:4;
3460 uint64_t reserved_4_7:4;
3461 uint64_t qlm_cfg:4;
c5aa59e8
DD		 3462#else
3463 uint64_t qlm_cfg:4;
3464 uint64_t reserved_4_7:4;
3465 uint64_t qlm_spd:4;
3466 uint64_t reserved_12_13:2;
3467 uint64_t prtmode:1;
3468 uint64_t reserved_15_63:49;
3469#endif
751c9f68
DD		 3470 } s;
3471 struct cvmx_mio_qlmx_cfg_cn61xx {
c5aa59e8
DD		 3472#ifdef __BIG_ENDIAN_BITFIELD
3473 uint64_t reserved_15_63:49;
3474 uint64_t prtmode:1;
3475 uint64_t reserved_12_13:2;
751c9f68
DD		 3476 uint64_t qlm_spd:4;
3477 uint64_t reserved_2_7:6;
3478 uint64_t qlm_cfg:2;
c5aa59e8
DD		 3479#else
3480 uint64_t qlm_cfg:2;
3481 uint64_t reserved_2_7:6;
3482 uint64_t qlm_spd:4;
3483 uint64_t reserved_12_13:2;
3484 uint64_t prtmode:1;
3485 uint64_t reserved_15_63:49;
3486#endif
751c9f68 3487 } cn61xx;
c5aa59e8
DD		 3488 struct cvmx_mio_qlmx_cfg_cn66xx {
3489#ifdef __BIG_ENDIAN_BITFIELD
3490 uint64_t reserved_12_63:52;
3491 uint64_t qlm_spd:4;
3492 uint64_t reserved_4_7:4;
3493 uint64_t qlm_cfg:4;
3494#else
3495 uint64_t qlm_cfg:4;
3496 uint64_t reserved_4_7:4;
3497 uint64_t qlm_spd:4;
3498 uint64_t reserved_12_63:52;
3499#endif
3500 } cn66xx;
751c9f68 3501 struct cvmx_mio_qlmx_cfg_cn68xx {
c5aa59e8 3502#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3503 uint64_t reserved_12_63:52;
3504 uint64_t qlm_spd:4;
3505 uint64_t reserved_3_7:5;
3506 uint64_t qlm_cfg:3;
c5aa59e8
DD		 3507#else
3508 uint64_t qlm_cfg:3;
3509 uint64_t reserved_3_7:5;
3510 uint64_t qlm_spd:4;
3511 uint64_t reserved_12_63:52;
3512#endif
751c9f68
DD		 3513 } cn68xx;
3514 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
c5aa59e8 3515 struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx;
aa32a955
DD		 3516};
3517
3518union cvmx_mio_rst_boot {
3519 uint64_t u64;
3520 struct cvmx_mio_rst_boot_s {
c5aa59e8 3521#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3522 uint64_t chipkill:1;
3523 uint64_t jtcsrdis:1;
3524 uint64_t ejtagdis:1;
3525 uint64_t romen:1;
3526 uint64_t ckill_ppdis:1;
3527 uint64_t jt_tstmode:1;
3528 uint64_t reserved_50_57:8;
3529 uint64_t lboot_ext:2;
3530 uint64_t reserved_44_47:4;
3531 uint64_t qlm4_spd:4;
3532 uint64_t qlm3_spd:4;
aa32a955
DD		 3533 uint64_t c_mul:6;
3534 uint64_t pnr_mul:6;
3535 uint64_t qlm2_spd:4;
3536 uint64_t qlm1_spd:4;
3537 uint64_t qlm0_spd:4;
3538 uint64_t lboot:10;
3539 uint64_t rboot:1;
3540 uint64_t rboot_pin:1;
c5aa59e8
DD		 3541#else
3542 uint64_t rboot_pin:1;
3543 uint64_t rboot:1;
3544 uint64_t lboot:10;
3545 uint64_t qlm0_spd:4;
3546 uint64_t qlm1_spd:4;
3547 uint64_t qlm2_spd:4;
3548 uint64_t pnr_mul:6;
3549 uint64_t c_mul:6;
3550 uint64_t qlm3_spd:4;
3551 uint64_t qlm4_spd:4;
3552 uint64_t reserved_44_47:4;
3553 uint64_t lboot_ext:2;
3554 uint64_t reserved_50_57:8;
3555 uint64_t jt_tstmode:1;
3556 uint64_t ckill_ppdis:1;
3557 uint64_t romen:1;
3558 uint64_t ejtagdis:1;
3559 uint64_t jtcsrdis:1;
3560 uint64_t chipkill:1;
3561#endif
aa32a955 3562 } s;
751c9f68 3563 struct cvmx_mio_rst_boot_cn61xx {
c5aa59e8 3564#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3565 uint64_t chipkill:1;
3566 uint64_t jtcsrdis:1;
3567 uint64_t ejtagdis:1;
3568 uint64_t romen:1;
3569 uint64_t ckill_ppdis:1;
3570 uint64_t jt_tstmode:1;
3571 uint64_t reserved_50_57:8;
3572 uint64_t lboot_ext:2;
3573 uint64_t reserved_36_47:12;
3574 uint64_t c_mul:6;
3575 uint64_t pnr_mul:6;
3576 uint64_t qlm2_spd:4;
3577 uint64_t qlm1_spd:4;
3578 uint64_t qlm0_spd:4;
3579 uint64_t lboot:10;
3580 uint64_t rboot:1;
3581 uint64_t rboot_pin:1;
c5aa59e8
DD		 3582#else
3583 uint64_t rboot_pin:1;
3584 uint64_t rboot:1;
3585 uint64_t lboot:10;
3586 uint64_t qlm0_spd:4;
3587 uint64_t qlm1_spd:4;
3588 uint64_t qlm2_spd:4;
3589 uint64_t pnr_mul:6;
3590 uint64_t c_mul:6;
3591 uint64_t reserved_36_47:12;
3592 uint64_t lboot_ext:2;
3593 uint64_t reserved_50_57:8;
3594 uint64_t jt_tstmode:1;
3595 uint64_t ckill_ppdis:1;
3596 uint64_t romen:1;
3597 uint64_t ejtagdis:1;
3598 uint64_t jtcsrdis:1;
3599 uint64_t chipkill:1;
3600#endif
751c9f68
DD		 3601 } cn61xx;
3602 struct cvmx_mio_rst_boot_cn63xx {
c5aa59e8 3603#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3604 uint64_t reserved_36_63:28;
3605 uint64_t c_mul:6;
3606 uint64_t pnr_mul:6;
3607 uint64_t qlm2_spd:4;
3608 uint64_t qlm1_spd:4;
3609 uint64_t qlm0_spd:4;
3610 uint64_t lboot:10;
3611 uint64_t rboot:1;
3612 uint64_t rboot_pin:1;
c5aa59e8
DD		 3613#else
3614 uint64_t rboot_pin:1;
3615 uint64_t rboot:1;
3616 uint64_t lboot:10;
3617 uint64_t qlm0_spd:4;
3618 uint64_t qlm1_spd:4;
3619 uint64_t qlm2_spd:4;
3620 uint64_t pnr_mul:6;
3621 uint64_t c_mul:6;
3622 uint64_t reserved_36_63:28;
3623#endif
751c9f68
DD		 3624 } cn63xx;
3625 struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
3626 struct cvmx_mio_rst_boot_cn66xx {
c5aa59e8 3627#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3628 uint64_t chipkill:1;
3629 uint64_t jtcsrdis:1;
3630 uint64_t ejtagdis:1;
3631 uint64_t romen:1;
3632 uint64_t ckill_ppdis:1;
3633 uint64_t reserved_50_58:9;
3634 uint64_t lboot_ext:2;
3635 uint64_t reserved_36_47:12;
3636 uint64_t c_mul:6;
3637 uint64_t pnr_mul:6;
3638 uint64_t qlm2_spd:4;
3639 uint64_t qlm1_spd:4;
3640 uint64_t qlm0_spd:4;
3641 uint64_t lboot:10;
3642 uint64_t rboot:1;
3643 uint64_t rboot_pin:1;
c5aa59e8
DD		 3644#else
3645 uint64_t rboot_pin:1;
3646 uint64_t rboot:1;
3647 uint64_t lboot:10;
3648 uint64_t qlm0_spd:4;
3649 uint64_t qlm1_spd:4;
3650 uint64_t qlm2_spd:4;
3651 uint64_t pnr_mul:6;
3652 uint64_t c_mul:6;
3653 uint64_t reserved_36_47:12;
3654 uint64_t lboot_ext:2;
3655 uint64_t reserved_50_58:9;
3656 uint64_t ckill_ppdis:1;
3657 uint64_t romen:1;
3658 uint64_t ejtagdis:1;
3659 uint64_t jtcsrdis:1;
3660 uint64_t chipkill:1;
3661#endif
751c9f68
DD		 3662 } cn66xx;
3663 struct cvmx_mio_rst_boot_cn68xx {
c5aa59e8 3664#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3665 uint64_t reserved_59_63:5;
3666 uint64_t jt_tstmode:1;
3667 uint64_t reserved_44_57:14;
3668 uint64_t qlm4_spd:4;
3669 uint64_t qlm3_spd:4;
3670 uint64_t c_mul:6;
3671 uint64_t pnr_mul:6;
3672 uint64_t qlm2_spd:4;
3673 uint64_t qlm1_spd:4;
3674 uint64_t qlm0_spd:4;
3675 uint64_t lboot:10;
3676 uint64_t rboot:1;
3677 uint64_t rboot_pin:1;
c5aa59e8
DD		 3678#else
3679 uint64_t rboot_pin:1;
3680 uint64_t rboot:1;
3681 uint64_t lboot:10;
3682 uint64_t qlm0_spd:4;
3683 uint64_t qlm1_spd:4;
3684 uint64_t qlm2_spd:4;
3685 uint64_t pnr_mul:6;
3686 uint64_t c_mul:6;
3687 uint64_t qlm3_spd:4;
3688 uint64_t qlm4_spd:4;
3689 uint64_t reserved_44_57:14;
3690 uint64_t jt_tstmode:1;
3691 uint64_t reserved_59_63:5;
3692#endif
751c9f68
DD		 3693 } cn68xx;
3694 struct cvmx_mio_rst_boot_cn68xxp1 {
c5aa59e8 3695#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3696 uint64_t reserved_44_63:20;
3697 uint64_t qlm4_spd:4;
3698 uint64_t qlm3_spd:4;
3699 uint64_t c_mul:6;
3700 uint64_t pnr_mul:6;
3701 uint64_t qlm2_spd:4;
3702 uint64_t qlm1_spd:4;
3703 uint64_t qlm0_spd:4;
3704 uint64_t lboot:10;
3705 uint64_t rboot:1;
3706 uint64_t rboot_pin:1;
c5aa59e8
DD		 3707#else
3708 uint64_t rboot_pin:1;
3709 uint64_t rboot:1;
3710 uint64_t lboot:10;
3711 uint64_t qlm0_spd:4;
3712 uint64_t qlm1_spd:4;
3713 uint64_t qlm2_spd:4;
3714 uint64_t pnr_mul:6;
3715 uint64_t c_mul:6;
3716 uint64_t qlm3_spd:4;
3717 uint64_t qlm4_spd:4;
3718 uint64_t reserved_44_63:20;
3719#endif
751c9f68 3720 } cn68xxp1;
c5aa59e8 3721 struct cvmx_mio_rst_boot_cn61xx cnf71xx;
aa32a955
DD		 3722};
3723
3724union cvmx_mio_rst_cfg {
3725 uint64_t u64;
3726 struct cvmx_mio_rst_cfg_s {
c5aa59e8 3727#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3728 uint64_t reserved_3_63:61;
3729 uint64_t cntl_clr_bist:1;
3730 uint64_t warm_clr_bist:1;
3731 uint64_t soft_clr_bist:1;
c5aa59e8
DD		 3732#else
3733 uint64_t soft_clr_bist:1;
3734 uint64_t warm_clr_bist:1;
3735 uint64_t cntl_clr_bist:1;
3736 uint64_t reserved_3_63:61;
3737#endif
751c9f68
DD		 3738 } s;
3739 struct cvmx_mio_rst_cfg_cn61xx {
c5aa59e8 3740#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3741 uint64_t bist_delay:58;
3742 uint64_t reserved_3_5:3;
3743 uint64_t cntl_clr_bist:1;
3744 uint64_t warm_clr_bist:1;
3745 uint64_t soft_clr_bist:1;
c5aa59e8
DD		 3746#else
3747 uint64_t soft_clr_bist:1;
3748 uint64_t warm_clr_bist:1;
3749 uint64_t cntl_clr_bist:1;
3750 uint64_t reserved_3_5:3;
3751 uint64_t bist_delay:58;
3752#endif
751c9f68
DD		 3753 } cn61xx;
3754 struct cvmx_mio_rst_cfg_cn61xx cn63xx;
aa32a955 3755 struct cvmx_mio_rst_cfg_cn63xxp1 {
c5aa59e8 3756#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3757 uint64_t bist_delay:58;
3758 uint64_t reserved_2_5:4;
3759 uint64_t warm_clr_bist:1;
3760 uint64_t soft_clr_bist:1;
c5aa59e8
DD		 3761#else
3762 uint64_t soft_clr_bist:1;
3763 uint64_t warm_clr_bist:1;
3764 uint64_t reserved_2_5:4;
3765 uint64_t bist_delay:58;
3766#endif
aa32a955 3767 } cn63xxp1;
751c9f68
DD		 3768 struct cvmx_mio_rst_cfg_cn61xx cn66xx;
3769 struct cvmx_mio_rst_cfg_cn68xx {
c5aa59e8 3770#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3771 uint64_t bist_delay:56;
3772 uint64_t reserved_3_7:5;
3773 uint64_t cntl_clr_bist:1;
3774 uint64_t warm_clr_bist:1;
3775 uint64_t soft_clr_bist:1;
c5aa59e8
DD		 3776#else
3777 uint64_t soft_clr_bist:1;
3778 uint64_t warm_clr_bist:1;
3779 uint64_t cntl_clr_bist:1;
3780 uint64_t reserved_3_7:5;
3781 uint64_t bist_delay:56;
3782#endif
751c9f68
DD		 3783 } cn68xx;
3784 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
c5aa59e8 3785 struct cvmx_mio_rst_cfg_cn61xx cnf71xx;
751c9f68
DD		 3786};
3787
3788union cvmx_mio_rst_ckill {
3789 uint64_t u64;
3790 struct cvmx_mio_rst_ckill_s {
c5aa59e8 3791#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3792 uint64_t reserved_47_63:17;
3793 uint64_t timer:47;
c5aa59e8
DD		 3794#else
3795 uint64_t timer:47;
3796 uint64_t reserved_47_63:17;
3797#endif
751c9f68
DD		 3798 } s;
3799 struct cvmx_mio_rst_ckill_s cn61xx;
3800 struct cvmx_mio_rst_ckill_s cn66xx;
c5aa59e8 3801 struct cvmx_mio_rst_ckill_s cnf71xx;
751c9f68
DD		 3802};
3803
3804union cvmx_mio_rst_cntlx {
3805 uint64_t u64;
3806 struct cvmx_mio_rst_cntlx_s {
c5aa59e8 3807#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3808 uint64_t reserved_13_63:51;
3809 uint64_t in_rev_ln:1;
3810 uint64_t rev_lanes:1;
3811 uint64_t gen1_only:1;
3812 uint64_t prst_link:1;
3813 uint64_t rst_done:1;
3814 uint64_t rst_link:1;
3815 uint64_t host_mode:1;
3816 uint64_t prtmode:2;
3817 uint64_t rst_drv:1;
3818 uint64_t rst_rcv:1;
3819 uint64_t rst_chip:1;
3820 uint64_t rst_val:1;
c5aa59e8
DD		 3821#else
3822 uint64_t rst_val:1;
3823 uint64_t rst_chip:1;
3824 uint64_t rst_rcv:1;
3825 uint64_t rst_drv:1;
3826 uint64_t prtmode:2;
3827 uint64_t host_mode:1;
3828 uint64_t rst_link:1;
3829 uint64_t rst_done:1;
3830 uint64_t prst_link:1;
3831 uint64_t gen1_only:1;
3832 uint64_t rev_lanes:1;
3833 uint64_t in_rev_ln:1;
3834 uint64_t reserved_13_63:51;
3835#endif
751c9f68
DD		 3836 } s;
3837 struct cvmx_mio_rst_cntlx_s cn61xx;
3838 struct cvmx_mio_rst_cntlx_cn66xx {
c5aa59e8 3839#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3840 uint64_t reserved_10_63:54;
3841 uint64_t prst_link:1;
3842 uint64_t rst_done:1;
3843 uint64_t rst_link:1;
3844 uint64_t host_mode:1;
3845 uint64_t prtmode:2;
3846 uint64_t rst_drv:1;
3847 uint64_t rst_rcv:1;
3848 uint64_t rst_chip:1;
3849 uint64_t rst_val:1;
c5aa59e8
DD		 3850#else
3851 uint64_t rst_val:1;
3852 uint64_t rst_chip:1;
3853 uint64_t rst_rcv:1;
3854 uint64_t rst_drv:1;
3855 uint64_t prtmode:2;
3856 uint64_t host_mode:1;
3857 uint64_t rst_link:1;
3858 uint64_t rst_done:1;
3859 uint64_t prst_link:1;
3860 uint64_t reserved_10_63:54;
3861#endif
751c9f68
DD		 3862 } cn66xx;
3863 struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
c5aa59e8 3864 struct cvmx_mio_rst_cntlx_s cnf71xx;
aa32a955
DD		 3865};
3866
3867union cvmx_mio_rst_ctlx {
3868 uint64_t u64;
3869 struct cvmx_mio_rst_ctlx_s {
c5aa59e8 3870#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3871 uint64_t reserved_13_63:51;
3872 uint64_t in_rev_ln:1;
3873 uint64_t rev_lanes:1;
3874 uint64_t gen1_only:1;
aa32a955
DD		 3875 uint64_t prst_link:1;
3876 uint64_t rst_done:1;
3877 uint64_t rst_link:1;
3878 uint64_t host_mode:1;
3879 uint64_t prtmode:2;
3880 uint64_t rst_drv:1;
3881 uint64_t rst_rcv:1;
3882 uint64_t rst_chip:1;
3883 uint64_t rst_val:1;
c5aa59e8
DD		 3884#else
3885 uint64_t rst_val:1;
3886 uint64_t rst_chip:1;
3887 uint64_t rst_rcv:1;
3888 uint64_t rst_drv:1;
3889 uint64_t prtmode:2;
3890 uint64_t host_mode:1;
3891 uint64_t rst_link:1;
3892 uint64_t rst_done:1;
3893 uint64_t prst_link:1;
3894 uint64_t gen1_only:1;
3895 uint64_t rev_lanes:1;
3896 uint64_t in_rev_ln:1;
3897 uint64_t reserved_13_63:51;
3898#endif
aa32a955 3899 } s;
751c9f68
DD		 3900 struct cvmx_mio_rst_ctlx_s cn61xx;
3901 struct cvmx_mio_rst_ctlx_cn63xx {
c5aa59e8 3902#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 3903 uint64_t reserved_10_63:54;
3904 uint64_t prst_link:1;
3905 uint64_t rst_done:1;
3906 uint64_t rst_link:1;
3907 uint64_t host_mode:1;
3908 uint64_t prtmode:2;
3909 uint64_t rst_drv:1;
3910 uint64_t rst_rcv:1;
3911 uint64_t rst_chip:1;
3912 uint64_t rst_val:1;
c5aa59e8
DD		 3913#else
3914 uint64_t rst_val:1;
3915 uint64_t rst_chip:1;
3916 uint64_t rst_rcv:1;
3917 uint64_t rst_drv:1;
3918 uint64_t prtmode:2;
3919 uint64_t host_mode:1;
3920 uint64_t rst_link:1;
3921 uint64_t rst_done:1;
3922 uint64_t prst_link:1;
3923 uint64_t reserved_10_63:54;
3924#endif
751c9f68 3925 } cn63xx;
aa32a955 3926 struct cvmx_mio_rst_ctlx_cn63xxp1 {
c5aa59e8 3927#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3928 uint64_t reserved_9_63:55;
3929 uint64_t rst_done:1;
3930 uint64_t rst_link:1;
3931 uint64_t host_mode:1;
3932 uint64_t prtmode:2;
3933 uint64_t rst_drv:1;
3934 uint64_t rst_rcv:1;
3935 uint64_t rst_chip:1;
3936 uint64_t rst_val:1;
c5aa59e8
DD		 3937#else
3938 uint64_t rst_val:1;
3939 uint64_t rst_chip:1;
3940 uint64_t rst_rcv:1;
3941 uint64_t rst_drv:1;
3942 uint64_t prtmode:2;
3943 uint64_t host_mode:1;
3944 uint64_t rst_link:1;
3945 uint64_t rst_done:1;
3946 uint64_t reserved_9_63:55;
3947#endif
aa32a955 3948 } cn63xxp1;
751c9f68
DD		 3949 struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
3950 struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
3951 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
c5aa59e8 3952 struct cvmx_mio_rst_ctlx_s cnf71xx;
aa32a955
DD		 3953};
3954
3955union cvmx_mio_rst_delay {
3956 uint64_t u64;
3957 struct cvmx_mio_rst_delay_s {
c5aa59e8 3958#ifdef __BIG_ENDIAN_BITFIELD
aa32a955 3959 uint64_t reserved_32_63:32;
aa32a955 3960 uint64_t warm_rst_dly:16;
751c9f68 3961 uint64_t soft_rst_dly:16;
c5aa59e8
DD		 3962#else
3963 uint64_t soft_rst_dly:16;
3964 uint64_t warm_rst_dly:16;
3965 uint64_t reserved_32_63:32;
3966#endif
aa32a955 3967 } s;
751c9f68 3968 struct cvmx_mio_rst_delay_s cn61xx;
aa32a955
DD		 3969 struct cvmx_mio_rst_delay_s cn63xx;
3970 struct cvmx_mio_rst_delay_s cn63xxp1;
751c9f68
DD		 3971 struct cvmx_mio_rst_delay_s cn66xx;
3972 struct cvmx_mio_rst_delay_s cn68xx;
3973 struct cvmx_mio_rst_delay_s cn68xxp1;
c5aa59e8 3974 struct cvmx_mio_rst_delay_s cnf71xx;
aa32a955
DD		 3975};
3976
3977union cvmx_mio_rst_int {
3978 uint64_t u64;
3979 struct cvmx_mio_rst_int_s {
c5aa59e8 3980#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 3981 uint64_t reserved_10_63:54;
3982 uint64_t perst1:1;
3983 uint64_t perst0:1;
751c9f68
DD		 3984 uint64_t reserved_4_7:4;
3985 uint64_t rst_link3:1;
3986 uint64_t rst_link2:1;
aa32a955
DD		 3987 uint64_t rst_link1:1;
3988 uint64_t rst_link0:1;
c5aa59e8
DD		 3989#else
3990 uint64_t rst_link0:1;
3991 uint64_t rst_link1:1;
3992 uint64_t rst_link2:1;
3993 uint64_t rst_link3:1;
3994 uint64_t reserved_4_7:4;
3995 uint64_t perst0:1;
3996 uint64_t perst1:1;
3997 uint64_t reserved_10_63:54;
3998#endif
aa32a955 3999 } s;
751c9f68 4000 struct cvmx_mio_rst_int_cn61xx {
c5aa59e8 4001#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 4002 uint64_t reserved_10_63:54;
4003 uint64_t perst1:1;
4004 uint64_t perst0:1;
4005 uint64_t reserved_2_7:6;
4006 uint64_t rst_link1:1;
4007 uint64_t rst_link0:1;
c5aa59e8
DD		 4008#else
4009 uint64_t rst_link0:1;
4010 uint64_t rst_link1:1;
4011 uint64_t reserved_2_7:6;
4012 uint64_t perst0:1;
4013 uint64_t perst1:1;
4014 uint64_t reserved_10_63:54;
4015#endif
751c9f68
DD		 4016 } cn61xx;
4017 struct cvmx_mio_rst_int_cn61xx cn63xx;
4018 struct cvmx_mio_rst_int_cn61xx cn63xxp1;
4019 struct cvmx_mio_rst_int_s cn66xx;
4020 struct cvmx_mio_rst_int_cn61xx cn68xx;
4021 struct cvmx_mio_rst_int_cn61xx cn68xxp1;
c5aa59e8 4022 struct cvmx_mio_rst_int_cn61xx cnf71xx;
aa32a955
DD		 4023};
4024
4025union cvmx_mio_rst_int_en {
4026 uint64_t u64;
4027 struct cvmx_mio_rst_int_en_s {
c5aa59e8 4028#ifdef __BIG_ENDIAN_BITFIELD
aa32a955
DD		 4029 uint64_t reserved_10_63:54;
4030 uint64_t perst1:1;
4031 uint64_t perst0:1;
751c9f68
DD		 4032 uint64_t reserved_4_7:4;
4033 uint64_t rst_link3:1;
4034 uint64_t rst_link2:1;
aa32a955
DD		 4035 uint64_t rst_link1:1;
4036 uint64_t rst_link0:1;
c5aa59e8
DD		 4037#else
4038 uint64_t rst_link0:1;
4039 uint64_t rst_link1:1;
4040 uint64_t rst_link2:1;
4041 uint64_t rst_link3:1;
4042 uint64_t reserved_4_7:4;
4043 uint64_t perst0:1;
4044 uint64_t perst1:1;
4045 uint64_t reserved_10_63:54;
4046#endif
aa32a955 4047 } s;
751c9f68 4048 struct cvmx_mio_rst_int_en_cn61xx {
c5aa59e8 4049#ifdef __BIG_ENDIAN_BITFIELD
751c9f68
DD		 4050 uint64_t reserved_10_63:54;
4051 uint64_t perst1:1;
4052 uint64_t perst0:1;
4053 uint64_t reserved_2_7:6;
4054 uint64_t rst_link1:1;
4055 uint64_t rst_link0:1;
c5aa59e8
DD		 4056#else
4057 uint64_t rst_link0:1;
4058 uint64_t rst_link1:1;
4059 uint64_t reserved_2_7:6;
4060 uint64_t perst0:1;
4061 uint64_t perst1:1;
4062 uint64_t reserved_10_63:54;
4063#endif
751c9f68
DD		 4064 } cn61xx;
4065 struct cvmx_mio_rst_int_en_cn61xx cn63xx;
4066 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
4067 struct cvmx_mio_rst_int_en_s cn66xx;
4068 struct cvmx_mio_rst_int_en_cn61xx cn68xx;
4069 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
c5aa59e8 4070 struct cvmx_mio_rst_int_en_cn61xx cnf71xx;
aa32a955
DD		 4071};
4072
54293ec3
DD		 4073union cvmx_mio_twsx_int {
4074 uint64_t u64;
4075 struct cvmx_mio_twsx_int_s {
c5aa59e8 4076#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4077 uint64_t reserved_12_63:52;
4078 uint64_t scl:1;
4079 uint64_t sda:1;
4080 uint64_t scl_ovr:1;
4081 uint64_t sda_ovr:1;
4082 uint64_t reserved_7_7:1;
4083 uint64_t core_en:1;
4084 uint64_t ts_en:1;
4085 uint64_t st_en:1;
4086 uint64_t reserved_3_3:1;
4087 uint64_t core_int:1;
4088 uint64_t ts_int:1;
4089 uint64_t st_int:1;
c5aa59e8
DD		 4090#else
4091 uint64_t st_int:1;
4092 uint64_t ts_int:1;
4093 uint64_t core_int:1;
4094 uint64_t reserved_3_3:1;
4095 uint64_t st_en:1;
4096 uint64_t ts_en:1;
4097 uint64_t core_en:1;
4098 uint64_t reserved_7_7:1;
4099 uint64_t sda_ovr:1;
4100 uint64_t scl_ovr:1;
4101 uint64_t sda:1;
4102 uint64_t scl:1;
4103 uint64_t reserved_12_63:52;
4104#endif
54293ec3
DD		 4105 } s;
4106 struct cvmx_mio_twsx_int_s cn30xx;
4107 struct cvmx_mio_twsx_int_s cn31xx;
4108 struct cvmx_mio_twsx_int_s cn38xx;
4109 struct cvmx_mio_twsx_int_cn38xxp2 {
c5aa59e8 4110#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4111 uint64_t reserved_7_63:57;
4112 uint64_t core_en:1;
4113 uint64_t ts_en:1;
4114 uint64_t st_en:1;
4115 uint64_t reserved_3_3:1;
4116 uint64_t core_int:1;
4117 uint64_t ts_int:1;
4118 uint64_t st_int:1;
c5aa59e8
DD		 4119#else
4120 uint64_t st_int:1;
4121 uint64_t ts_int:1;
4122 uint64_t core_int:1;
4123 uint64_t reserved_3_3:1;
4124 uint64_t st_en:1;
4125 uint64_t ts_en:1;
4126 uint64_t core_en:1;
4127 uint64_t reserved_7_63:57;
4128#endif
54293ec3
DD		 4129 } cn38xxp2;
4130 struct cvmx_mio_twsx_int_s cn50xx;
4131 struct cvmx_mio_twsx_int_s cn52xx;
4132 struct cvmx_mio_twsx_int_s cn52xxp1;
4133 struct cvmx_mio_twsx_int_s cn56xx;
4134 struct cvmx_mio_twsx_int_s cn56xxp1;
4135 struct cvmx_mio_twsx_int_s cn58xx;
4136 struct cvmx_mio_twsx_int_s cn58xxp1;
751c9f68 4137 struct cvmx_mio_twsx_int_s cn61xx;
aa32a955
DD		 4138 struct cvmx_mio_twsx_int_s cn63xx;
4139 struct cvmx_mio_twsx_int_s cn63xxp1;
751c9f68
DD		 4140 struct cvmx_mio_twsx_int_s cn66xx;
4141 struct cvmx_mio_twsx_int_s cn68xx;
4142 struct cvmx_mio_twsx_int_s cn68xxp1;
c5aa59e8 4143 struct cvmx_mio_twsx_int_s cnf71xx;
54293ec3
DD		 4144};
4145
4146union cvmx_mio_twsx_sw_twsi {
4147 uint64_t u64;
4148 struct cvmx_mio_twsx_sw_twsi_s {
c5aa59e8 4149#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4150 uint64_t v:1;
4151 uint64_t slonly:1;
4152 uint64_t eia:1;
4153 uint64_t op:4;
4154 uint64_t r:1;
4155 uint64_t sovr:1;
4156 uint64_t size:3;
4157 uint64_t scr:2;
4158 uint64_t a:10;
4159 uint64_t ia:5;
4160 uint64_t eop_ia:3;
4161 uint64_t d:32;
c5aa59e8
DD		 4162#else
4163 uint64_t d:32;
4164 uint64_t eop_ia:3;
4165 uint64_t ia:5;
4166 uint64_t a:10;
4167 uint64_t scr:2;
4168 uint64_t size:3;
4169 uint64_t sovr:1;
4170 uint64_t r:1;
4171 uint64_t op:4;
4172 uint64_t eia:1;
4173 uint64_t slonly:1;
4174 uint64_t v:1;
4175#endif
54293ec3
DD		 4176 } s;
4177 struct cvmx_mio_twsx_sw_twsi_s cn30xx;
4178 struct cvmx_mio_twsx_sw_twsi_s cn31xx;
4179 struct cvmx_mio_twsx_sw_twsi_s cn38xx;
4180 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
4181 struct cvmx_mio_twsx_sw_twsi_s cn50xx;
4182 struct cvmx_mio_twsx_sw_twsi_s cn52xx;
4183 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
4184 struct cvmx_mio_twsx_sw_twsi_s cn56xx;
4185 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
4186 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
4187 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
751c9f68 4188 struct cvmx_mio_twsx_sw_twsi_s cn61xx;
aa32a955
DD		 4189 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
4190 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
751c9f68
DD		 4191 struct cvmx_mio_twsx_sw_twsi_s cn66xx;
4192 struct cvmx_mio_twsx_sw_twsi_s cn68xx;
4193 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
c5aa59e8 4194 struct cvmx_mio_twsx_sw_twsi_s cnf71xx;
54293ec3
DD		 4195};
4196
4197union cvmx_mio_twsx_sw_twsi_ext {
4198 uint64_t u64;
4199 struct cvmx_mio_twsx_sw_twsi_ext_s {
c5aa59e8 4200#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4201 uint64_t reserved_40_63:24;
4202 uint64_t ia:8;
4203 uint64_t d:32;
c5aa59e8
DD		 4204#else
4205 uint64_t d:32;
4206 uint64_t ia:8;
4207 uint64_t reserved_40_63:24;
4208#endif
54293ec3
DD		 4209 } s;
4210 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
4211 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
4212 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
4213 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
4214 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
4215 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
4216 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
4217 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
4218 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
4219 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
4220 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
751c9f68 4221 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
aa32a955
DD		 4222 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
4223 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
751c9f68
DD		 4224 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
4225 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
4226 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
c5aa59e8 4227 struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx;
54293ec3
DD		 4228};
4229
4230union cvmx_mio_twsx_twsi_sw {
4231 uint64_t u64;
4232 struct cvmx_mio_twsx_twsi_sw_s {
c5aa59e8 4233#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4234 uint64_t v:2;
4235 uint64_t reserved_32_61:30;
4236 uint64_t d:32;
c5aa59e8
DD		 4237#else
4238 uint64_t d:32;
4239 uint64_t reserved_32_61:30;
4240 uint64_t v:2;
4241#endif
54293ec3
DD		 4242 } s;
4243 struct cvmx_mio_twsx_twsi_sw_s cn30xx;
4244 struct cvmx_mio_twsx_twsi_sw_s cn31xx;
4245 struct cvmx_mio_twsx_twsi_sw_s cn38xx;
4246 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
4247 struct cvmx_mio_twsx_twsi_sw_s cn50xx;
4248 struct cvmx_mio_twsx_twsi_sw_s cn52xx;
4249 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
4250 struct cvmx_mio_twsx_twsi_sw_s cn56xx;
4251 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
4252 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
4253 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
751c9f68 4254 struct cvmx_mio_twsx_twsi_sw_s cn61xx;
aa32a955
DD		 4255 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
4256 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
751c9f68
DD		 4257 struct cvmx_mio_twsx_twsi_sw_s cn66xx;
4258 struct cvmx_mio_twsx_twsi_sw_s cn68xx;
4259 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
c5aa59e8 4260 struct cvmx_mio_twsx_twsi_sw_s cnf71xx;
54293ec3
DD		 4261};
4262
4263union cvmx_mio_uartx_dlh {
4264 uint64_t u64;
4265 struct cvmx_mio_uartx_dlh_s {
c5aa59e8 4266#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4267 uint64_t reserved_8_63:56;
4268 uint64_t dlh:8;
c5aa59e8
DD		 4269#else
4270 uint64_t dlh:8;
4271 uint64_t reserved_8_63:56;
4272#endif
54293ec3
DD		 4273 } s;
4274 struct cvmx_mio_uartx_dlh_s cn30xx;
4275 struct cvmx_mio_uartx_dlh_s cn31xx;
4276 struct cvmx_mio_uartx_dlh_s cn38xx;
4277 struct cvmx_mio_uartx_dlh_s cn38xxp2;
4278 struct cvmx_mio_uartx_dlh_s cn50xx;
4279 struct cvmx_mio_uartx_dlh_s cn52xx;
4280 struct cvmx_mio_uartx_dlh_s cn52xxp1;
4281 struct cvmx_mio_uartx_dlh_s cn56xx;
4282 struct cvmx_mio_uartx_dlh_s cn56xxp1;
4283 struct cvmx_mio_uartx_dlh_s cn58xx;
4284 struct cvmx_mio_uartx_dlh_s cn58xxp1;
751c9f68 4285 struct cvmx_mio_uartx_dlh_s cn61xx;
aa32a955
DD		 4286 struct cvmx_mio_uartx_dlh_s cn63xx;
4287 struct cvmx_mio_uartx_dlh_s cn63xxp1;
751c9f68
DD		 4288 struct cvmx_mio_uartx_dlh_s cn66xx;
4289 struct cvmx_mio_uartx_dlh_s cn68xx;
4290 struct cvmx_mio_uartx_dlh_s cn68xxp1;
c5aa59e8 4291 struct cvmx_mio_uartx_dlh_s cnf71xx;
54293ec3
DD		 4292};
4293
4294union cvmx_mio_uartx_dll {
4295 uint64_t u64;
4296 struct cvmx_mio_uartx_dll_s {
c5aa59e8 4297#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4298 uint64_t reserved_8_63:56;
4299 uint64_t dll:8;
c5aa59e8
DD		 4300#else
4301 uint64_t dll:8;
4302 uint64_t reserved_8_63:56;
4303#endif
54293ec3
DD		 4304 } s;
4305 struct cvmx_mio_uartx_dll_s cn30xx;
4306 struct cvmx_mio_uartx_dll_s cn31xx;
4307 struct cvmx_mio_uartx_dll_s cn38xx;
4308 struct cvmx_mio_uartx_dll_s cn38xxp2;
4309 struct cvmx_mio_uartx_dll_s cn50xx;
4310 struct cvmx_mio_uartx_dll_s cn52xx;
4311 struct cvmx_mio_uartx_dll_s cn52xxp1;
4312 struct cvmx_mio_uartx_dll_s cn56xx;
4313 struct cvmx_mio_uartx_dll_s cn56xxp1;
4314 struct cvmx_mio_uartx_dll_s cn58xx;
4315 struct cvmx_mio_uartx_dll_s cn58xxp1;
751c9f68 4316 struct cvmx_mio_uartx_dll_s cn61xx;
aa32a955
DD		 4317 struct cvmx_mio_uartx_dll_s cn63xx;
4318 struct cvmx_mio_uartx_dll_s cn63xxp1;
751c9f68
DD		 4319 struct cvmx_mio_uartx_dll_s cn66xx;
4320 struct cvmx_mio_uartx_dll_s cn68xx;
4321 struct cvmx_mio_uartx_dll_s cn68xxp1;
c5aa59e8 4322 struct cvmx_mio_uartx_dll_s cnf71xx;
54293ec3
DD		 4323};
4324
4325union cvmx_mio_uartx_far {
4326 uint64_t u64;
4327 struct cvmx_mio_uartx_far_s {
c5aa59e8 4328#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4329 uint64_t reserved_1_63:63;
4330 uint64_t far:1;
c5aa59e8
DD		 4331#else
4332 uint64_t far:1;
4333 uint64_t reserved_1_63:63;
4334#endif
54293ec3
DD		 4335 } s;
4336 struct cvmx_mio_uartx_far_s cn30xx;
4337 struct cvmx_mio_uartx_far_s cn31xx;
4338 struct cvmx_mio_uartx_far_s cn38xx;
4339 struct cvmx_mio_uartx_far_s cn38xxp2;
4340 struct cvmx_mio_uartx_far_s cn50xx;
4341 struct cvmx_mio_uartx_far_s cn52xx;
4342 struct cvmx_mio_uartx_far_s cn52xxp1;
4343 struct cvmx_mio_uartx_far_s cn56xx;
4344 struct cvmx_mio_uartx_far_s cn56xxp1;
4345 struct cvmx_mio_uartx_far_s cn58xx;
4346 struct cvmx_mio_uartx_far_s cn58xxp1;
751c9f68 4347 struct cvmx_mio_uartx_far_s cn61xx;
aa32a955
DD		 4348 struct cvmx_mio_uartx_far_s cn63xx;
4349 struct cvmx_mio_uartx_far_s cn63xxp1;
751c9f68
DD		 4350 struct cvmx_mio_uartx_far_s cn66xx;
4351 struct cvmx_mio_uartx_far_s cn68xx;
4352 struct cvmx_mio_uartx_far_s cn68xxp1;
c5aa59e8 4353 struct cvmx_mio_uartx_far_s cnf71xx;
54293ec3
DD		 4354};
4355
4356union cvmx_mio_uartx_fcr {
4357 uint64_t u64;
4358 struct cvmx_mio_uartx_fcr_s {
c5aa59e8 4359#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4360 uint64_t reserved_8_63:56;
4361 uint64_t rxtrig:2;
4362 uint64_t txtrig:2;
4363 uint64_t reserved_3_3:1;
4364 uint64_t txfr:1;
4365 uint64_t rxfr:1;
4366 uint64_t en:1;
c5aa59e8
DD		 4367#else
4368 uint64_t en:1;
4369 uint64_t rxfr:1;
4370 uint64_t txfr:1;
4371 uint64_t reserved_3_3:1;
4372 uint64_t txtrig:2;
4373 uint64_t rxtrig:2;
4374 uint64_t reserved_8_63:56;
4375#endif
54293ec3
DD		 4376 } s;
4377 struct cvmx_mio_uartx_fcr_s cn30xx;
4378 struct cvmx_mio_uartx_fcr_s cn31xx;
4379 struct cvmx_mio_uartx_fcr_s cn38xx;
4380 struct cvmx_mio_uartx_fcr_s cn38xxp2;
4381 struct cvmx_mio_uartx_fcr_s cn50xx;
4382 struct cvmx_mio_uartx_fcr_s cn52xx;
4383 struct cvmx_mio_uartx_fcr_s cn52xxp1;
4384 struct cvmx_mio_uartx_fcr_s cn56xx;
4385 struct cvmx_mio_uartx_fcr_s cn56xxp1;
4386 struct cvmx_mio_uartx_fcr_s cn58xx;
4387 struct cvmx_mio_uartx_fcr_s cn58xxp1;
751c9f68 4388 struct cvmx_mio_uartx_fcr_s cn61xx;
aa32a955
DD		 4389 struct cvmx_mio_uartx_fcr_s cn63xx;
4390 struct cvmx_mio_uartx_fcr_s cn63xxp1;
751c9f68
DD		 4391 struct cvmx_mio_uartx_fcr_s cn66xx;
4392 struct cvmx_mio_uartx_fcr_s cn68xx;
4393 struct cvmx_mio_uartx_fcr_s cn68xxp1;
c5aa59e8 4394 struct cvmx_mio_uartx_fcr_s cnf71xx;
54293ec3
DD		 4395};
4396
4397union cvmx_mio_uartx_htx {
4398 uint64_t u64;
4399 struct cvmx_mio_uartx_htx_s {
c5aa59e8 4400#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4401 uint64_t reserved_1_63:63;
4402 uint64_t htx:1;
c5aa59e8
DD		 4403#else
4404 uint64_t htx:1;
4405 uint64_t reserved_1_63:63;
4406#endif
54293ec3
DD		 4407 } s;
4408 struct cvmx_mio_uartx_htx_s cn30xx;
4409 struct cvmx_mio_uartx_htx_s cn31xx;
4410 struct cvmx_mio_uartx_htx_s cn38xx;
4411 struct cvmx_mio_uartx_htx_s cn38xxp2;
4412 struct cvmx_mio_uartx_htx_s cn50xx;
4413 struct cvmx_mio_uartx_htx_s cn52xx;
4414 struct cvmx_mio_uartx_htx_s cn52xxp1;
4415 struct cvmx_mio_uartx_htx_s cn56xx;
4416 struct cvmx_mio_uartx_htx_s cn56xxp1;
4417 struct cvmx_mio_uartx_htx_s cn58xx;
4418 struct cvmx_mio_uartx_htx_s cn58xxp1;
751c9f68 4419 struct cvmx_mio_uartx_htx_s cn61xx;
aa32a955
DD		 4420 struct cvmx_mio_uartx_htx_s cn63xx;
4421 struct cvmx_mio_uartx_htx_s cn63xxp1;
751c9f68
DD		 4422 struct cvmx_mio_uartx_htx_s cn66xx;
4423 struct cvmx_mio_uartx_htx_s cn68xx;
4424 struct cvmx_mio_uartx_htx_s cn68xxp1;
c5aa59e8 4425 struct cvmx_mio_uartx_htx_s cnf71xx;
54293ec3
DD		 4426};
4427
4428union cvmx_mio_uartx_ier {
4429 uint64_t u64;
4430 struct cvmx_mio_uartx_ier_s {
c5aa59e8 4431#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4432 uint64_t reserved_8_63:56;
4433 uint64_t ptime:1;
4434 uint64_t reserved_4_6:3;
4435 uint64_t edssi:1;
4436 uint64_t elsi:1;
4437 uint64_t etbei:1;
4438 uint64_t erbfi:1;
c5aa59e8
DD		 4439#else
4440 uint64_t erbfi:1;
4441 uint64_t etbei:1;
4442 uint64_t elsi:1;
4443 uint64_t edssi:1;
4444 uint64_t reserved_4_6:3;
4445 uint64_t ptime:1;
4446 uint64_t reserved_8_63:56;
4447#endif
54293ec3
DD		 4448 } s;
4449 struct cvmx_mio_uartx_ier_s cn30xx;
4450 struct cvmx_mio_uartx_ier_s cn31xx;
4451 struct cvmx_mio_uartx_ier_s cn38xx;
4452 struct cvmx_mio_uartx_ier_s cn38xxp2;
4453 struct cvmx_mio_uartx_ier_s cn50xx;
4454 struct cvmx_mio_uartx_ier_s cn52xx;
4455 struct cvmx_mio_uartx_ier_s cn52xxp1;
4456 struct cvmx_mio_uartx_ier_s cn56xx;
4457 struct cvmx_mio_uartx_ier_s cn56xxp1;
4458 struct cvmx_mio_uartx_ier_s cn58xx;
4459 struct cvmx_mio_uartx_ier_s cn58xxp1;
751c9f68 4460 struct cvmx_mio_uartx_ier_s cn61xx;
aa32a955
DD		 4461 struct cvmx_mio_uartx_ier_s cn63xx;
4462 struct cvmx_mio_uartx_ier_s cn63xxp1;
751c9f68
DD		 4463 struct cvmx_mio_uartx_ier_s cn66xx;
4464 struct cvmx_mio_uartx_ier_s cn68xx;
4465 struct cvmx_mio_uartx_ier_s cn68xxp1;
c5aa59e8 4466 struct cvmx_mio_uartx_ier_s cnf71xx;
54293ec3
DD		 4467};
4468
4469union cvmx_mio_uartx_iir {
4470 uint64_t u64;
4471 struct cvmx_mio_uartx_iir_s {
c5aa59e8 4472#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4473 uint64_t reserved_8_63:56;
4474 uint64_t fen:2;
4475 uint64_t reserved_4_5:2;
4476 uint64_t iid:4;
c5aa59e8
DD		 4477#else
4478 uint64_t iid:4;
4479 uint64_t reserved_4_5:2;
4480 uint64_t fen:2;
4481 uint64_t reserved_8_63:56;
4482#endif
54293ec3
DD		 4483 } s;
4484 struct cvmx_mio_uartx_iir_s cn30xx;
4485 struct cvmx_mio_uartx_iir_s cn31xx;
4486 struct cvmx_mio_uartx_iir_s cn38xx;
4487 struct cvmx_mio_uartx_iir_s cn38xxp2;
4488 struct cvmx_mio_uartx_iir_s cn50xx;
4489 struct cvmx_mio_uartx_iir_s cn52xx;
4490 struct cvmx_mio_uartx_iir_s cn52xxp1;
4491 struct cvmx_mio_uartx_iir_s cn56xx;
4492 struct cvmx_mio_uartx_iir_s cn56xxp1;
4493 struct cvmx_mio_uartx_iir_s cn58xx;
4494 struct cvmx_mio_uartx_iir_s cn58xxp1;
751c9f68 4495 struct cvmx_mio_uartx_iir_s cn61xx;
aa32a955
DD		 4496 struct cvmx_mio_uartx_iir_s cn63xx;
4497 struct cvmx_mio_uartx_iir_s cn63xxp1;
751c9f68
DD		 4498 struct cvmx_mio_uartx_iir_s cn66xx;
4499 struct cvmx_mio_uartx_iir_s cn68xx;
4500 struct cvmx_mio_uartx_iir_s cn68xxp1;
c5aa59e8 4501 struct cvmx_mio_uartx_iir_s cnf71xx;
54293ec3
DD		 4502};
4503
4504union cvmx_mio_uartx_lcr {
4505 uint64_t u64;
4506 struct cvmx_mio_uartx_lcr_s {
c5aa59e8 4507#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4508 uint64_t reserved_8_63:56;
4509 uint64_t dlab:1;
4510 uint64_t brk:1;
4511 uint64_t reserved_5_5:1;
4512 uint64_t eps:1;
4513 uint64_t pen:1;
4514 uint64_t stop:1;
4515 uint64_t cls:2;
c5aa59e8
DD		 4516#else
4517 uint64_t cls:2;
4518 uint64_t stop:1;
4519 uint64_t pen:1;
4520 uint64_t eps:1;
4521 uint64_t reserved_5_5:1;
4522 uint64_t brk:1;
4523 uint64_t dlab:1;
4524 uint64_t reserved_8_63:56;
4525#endif
54293ec3
DD		 4526 } s;
4527 struct cvmx_mio_uartx_lcr_s cn30xx;
4528 struct cvmx_mio_uartx_lcr_s cn31xx;
4529 struct cvmx_mio_uartx_lcr_s cn38xx;
4530 struct cvmx_mio_uartx_lcr_s cn38xxp2;
4531 struct cvmx_mio_uartx_lcr_s cn50xx;
4532 struct cvmx_mio_uartx_lcr_s cn52xx;
4533 struct cvmx_mio_uartx_lcr_s cn52xxp1;
4534 struct cvmx_mio_uartx_lcr_s cn56xx;
4535 struct cvmx_mio_uartx_lcr_s cn56xxp1;
4536 struct cvmx_mio_uartx_lcr_s cn58xx;
4537 struct cvmx_mio_uartx_lcr_s cn58xxp1;
751c9f68 4538 struct cvmx_mio_uartx_lcr_s cn61xx;
aa32a955
DD		 4539 struct cvmx_mio_uartx_lcr_s cn63xx;
4540 struct cvmx_mio_uartx_lcr_s cn63xxp1;
751c9f68
DD		 4541 struct cvmx_mio_uartx_lcr_s cn66xx;
4542 struct cvmx_mio_uartx_lcr_s cn68xx;
4543 struct cvmx_mio_uartx_lcr_s cn68xxp1;
c5aa59e8 4544 struct cvmx_mio_uartx_lcr_s cnf71xx;
54293ec3
DD		 4545};
4546
4547union cvmx_mio_uartx_lsr {
4548 uint64_t u64;
4549 struct cvmx_mio_uartx_lsr_s {
c5aa59e8 4550#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4551 uint64_t reserved_8_63:56;
4552 uint64_t ferr:1;
4553 uint64_t temt:1;
4554 uint64_t thre:1;
4555 uint64_t bi:1;
4556 uint64_t fe:1;
4557 uint64_t pe:1;
4558 uint64_t oe:1;
4559 uint64_t dr:1;
c5aa59e8
DD		 4560#else
4561 uint64_t dr:1;
4562 uint64_t oe:1;
4563 uint64_t pe:1;
4564 uint64_t fe:1;
4565 uint64_t bi:1;
4566 uint64_t thre:1;
4567 uint64_t temt:1;
4568 uint64_t ferr:1;
4569 uint64_t reserved_8_63:56;
4570#endif
54293ec3
DD		 4571 } s;
4572 struct cvmx_mio_uartx_lsr_s cn30xx;
4573 struct cvmx_mio_uartx_lsr_s cn31xx;
4574 struct cvmx_mio_uartx_lsr_s cn38xx;
4575 struct cvmx_mio_uartx_lsr_s cn38xxp2;
4576 struct cvmx_mio_uartx_lsr_s cn50xx;
4577 struct cvmx_mio_uartx_lsr_s cn52xx;
4578 struct cvmx_mio_uartx_lsr_s cn52xxp1;
4579 struct cvmx_mio_uartx_lsr_s cn56xx;
4580 struct cvmx_mio_uartx_lsr_s cn56xxp1;
4581 struct cvmx_mio_uartx_lsr_s cn58xx;
4582 struct cvmx_mio_uartx_lsr_s cn58xxp1;
751c9f68 4583 struct cvmx_mio_uartx_lsr_s cn61xx;
aa32a955
DD		 4584 struct cvmx_mio_uartx_lsr_s cn63xx;
4585 struct cvmx_mio_uartx_lsr_s cn63xxp1;
751c9f68
DD		 4586 struct cvmx_mio_uartx_lsr_s cn66xx;
4587 struct cvmx_mio_uartx_lsr_s cn68xx;
4588 struct cvmx_mio_uartx_lsr_s cn68xxp1;
c5aa59e8 4589 struct cvmx_mio_uartx_lsr_s cnf71xx;
54293ec3
DD		 4590};
4591
4592union cvmx_mio_uartx_mcr {
4593 uint64_t u64;
4594 struct cvmx_mio_uartx_mcr_s {
c5aa59e8 4595#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4596 uint64_t reserved_6_63:58;
4597 uint64_t afce:1;
4598 uint64_t loop:1;
4599 uint64_t out2:1;
4600 uint64_t out1:1;
4601 uint64_t rts:1;
4602 uint64_t dtr:1;
c5aa59e8
DD		 4603#else
4604 uint64_t dtr:1;
4605 uint64_t rts:1;
4606 uint64_t out1:1;
4607 uint64_t out2:1;
4608 uint64_t loop:1;
4609 uint64_t afce:1;
4610 uint64_t reserved_6_63:58;
4611#endif
54293ec3
DD		 4612 } s;
4613 struct cvmx_mio_uartx_mcr_s cn30xx;
4614 struct cvmx_mio_uartx_mcr_s cn31xx;
4615 struct cvmx_mio_uartx_mcr_s cn38xx;
4616 struct cvmx_mio_uartx_mcr_s cn38xxp2;
4617 struct cvmx_mio_uartx_mcr_s cn50xx;
4618 struct cvmx_mio_uartx_mcr_s cn52xx;
4619 struct cvmx_mio_uartx_mcr_s cn52xxp1;
4620 struct cvmx_mio_uartx_mcr_s cn56xx;
4621 struct cvmx_mio_uartx_mcr_s cn56xxp1;
4622 struct cvmx_mio_uartx_mcr_s cn58xx;
4623 struct cvmx_mio_uartx_mcr_s cn58xxp1;
751c9f68 4624 struct cvmx_mio_uartx_mcr_s cn61xx;
aa32a955
DD		 4625 struct cvmx_mio_uartx_mcr_s cn63xx;
4626 struct cvmx_mio_uartx_mcr_s cn63xxp1;
751c9f68
DD		 4627 struct cvmx_mio_uartx_mcr_s cn66xx;
4628 struct cvmx_mio_uartx_mcr_s cn68xx;
4629 struct cvmx_mio_uartx_mcr_s cn68xxp1;
c5aa59e8 4630 struct cvmx_mio_uartx_mcr_s cnf71xx;
54293ec3
DD		 4631};
4632
4633union cvmx_mio_uartx_msr {
4634 uint64_t u64;
4635 struct cvmx_mio_uartx_msr_s {
c5aa59e8 4636#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4637 uint64_t reserved_8_63:56;
4638 uint64_t dcd:1;
4639 uint64_t ri:1;
4640 uint64_t dsr:1;
4641 uint64_t cts:1;
4642 uint64_t ddcd:1;
4643 uint64_t teri:1;
4644 uint64_t ddsr:1;
4645 uint64_t dcts:1;
c5aa59e8
DD		 4646#else
4647 uint64_t dcts:1;
4648 uint64_t ddsr:1;
4649 uint64_t teri:1;
4650 uint64_t ddcd:1;
4651 uint64_t cts:1;
4652 uint64_t dsr:1;
4653 uint64_t ri:1;
4654 uint64_t dcd:1;
4655 uint64_t reserved_8_63:56;
4656#endif
54293ec3
DD		 4657 } s;
4658 struct cvmx_mio_uartx_msr_s cn30xx;
4659 struct cvmx_mio_uartx_msr_s cn31xx;
4660 struct cvmx_mio_uartx_msr_s cn38xx;
4661 struct cvmx_mio_uartx_msr_s cn38xxp2;
4662 struct cvmx_mio_uartx_msr_s cn50xx;
4663 struct cvmx_mio_uartx_msr_s cn52xx;
4664 struct cvmx_mio_uartx_msr_s cn52xxp1;
4665 struct cvmx_mio_uartx_msr_s cn56xx;
4666 struct cvmx_mio_uartx_msr_s cn56xxp1;
4667 struct cvmx_mio_uartx_msr_s cn58xx;
4668 struct cvmx_mio_uartx_msr_s cn58xxp1;
751c9f68 4669 struct cvmx_mio_uartx_msr_s cn61xx;
aa32a955
DD		 4670 struct cvmx_mio_uartx_msr_s cn63xx;
4671 struct cvmx_mio_uartx_msr_s cn63xxp1;
751c9f68
DD		 4672 struct cvmx_mio_uartx_msr_s cn66xx;
4673 struct cvmx_mio_uartx_msr_s cn68xx;
4674 struct cvmx_mio_uartx_msr_s cn68xxp1;
c5aa59e8 4675 struct cvmx_mio_uartx_msr_s cnf71xx;
54293ec3
DD		 4676};
4677
4678union cvmx_mio_uartx_rbr {
4679 uint64_t u64;
4680 struct cvmx_mio_uartx_rbr_s {
c5aa59e8 4681#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4682 uint64_t reserved_8_63:56;
4683 uint64_t rbr:8;
c5aa59e8
DD		 4684#else
4685 uint64_t rbr:8;
4686 uint64_t reserved_8_63:56;
4687#endif
54293ec3
DD		 4688 } s;
4689 struct cvmx_mio_uartx_rbr_s cn30xx;
4690 struct cvmx_mio_uartx_rbr_s cn31xx;
4691 struct cvmx_mio_uartx_rbr_s cn38xx;
4692 struct cvmx_mio_uartx_rbr_s cn38xxp2;
4693 struct cvmx_mio_uartx_rbr_s cn50xx;
4694 struct cvmx_mio_uartx_rbr_s cn52xx;
4695 struct cvmx_mio_uartx_rbr_s cn52xxp1;
4696 struct cvmx_mio_uartx_rbr_s cn56xx;
4697 struct cvmx_mio_uartx_rbr_s cn56xxp1;
4698 struct cvmx_mio_uartx_rbr_s cn58xx;
4699 struct cvmx_mio_uartx_rbr_s cn58xxp1;
751c9f68 4700 struct cvmx_mio_uartx_rbr_s cn61xx;
aa32a955
DD		 4701 struct cvmx_mio_uartx_rbr_s cn63xx;
4702 struct cvmx_mio_uartx_rbr_s cn63xxp1;
751c9f68
DD		 4703 struct cvmx_mio_uartx_rbr_s cn66xx;
4704 struct cvmx_mio_uartx_rbr_s cn68xx;
4705 struct cvmx_mio_uartx_rbr_s cn68xxp1;
c5aa59e8 4706 struct cvmx_mio_uartx_rbr_s cnf71xx;
54293ec3
DD		 4707};
4708
4709union cvmx_mio_uartx_rfl {
4710 uint64_t u64;
4711 struct cvmx_mio_uartx_rfl_s {
c5aa59e8 4712#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4713 uint64_t reserved_7_63:57;
4714 uint64_t rfl:7;
c5aa59e8
DD		 4715#else
4716 uint64_t rfl:7;
4717 uint64_t reserved_7_63:57;
4718#endif
54293ec3
DD		 4719 } s;
4720 struct cvmx_mio_uartx_rfl_s cn30xx;
4721 struct cvmx_mio_uartx_rfl_s cn31xx;
4722 struct cvmx_mio_uartx_rfl_s cn38xx;
4723 struct cvmx_mio_uartx_rfl_s cn38xxp2;
4724 struct cvmx_mio_uartx_rfl_s cn50xx;
4725 struct cvmx_mio_uartx_rfl_s cn52xx;
4726 struct cvmx_mio_uartx_rfl_s cn52xxp1;
4727 struct cvmx_mio_uartx_rfl_s cn56xx;
4728 struct cvmx_mio_uartx_rfl_s cn56xxp1;
4729 struct cvmx_mio_uartx_rfl_s cn58xx;
4730 struct cvmx_mio_uartx_rfl_s cn58xxp1;
751c9f68 4731 struct cvmx_mio_uartx_rfl_s cn61xx;
aa32a955
DD		 4732 struct cvmx_mio_uartx_rfl_s cn63xx;
4733 struct cvmx_mio_uartx_rfl_s cn63xxp1;
751c9f68
DD		 4734 struct cvmx_mio_uartx_rfl_s cn66xx;
4735 struct cvmx_mio_uartx_rfl_s cn68xx;
4736 struct cvmx_mio_uartx_rfl_s cn68xxp1;
c5aa59e8 4737 struct cvmx_mio_uartx_rfl_s cnf71xx;
54293ec3
DD		 4738};
4739
4740union cvmx_mio_uartx_rfw {
4741 uint64_t u64;
4742 struct cvmx_mio_uartx_rfw_s {
c5aa59e8 4743#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4744 uint64_t reserved_10_63:54;
4745 uint64_t rffe:1;
4746 uint64_t rfpe:1;
4747 uint64_t rfwd:8;
c5aa59e8
DD		 4748#else
4749 uint64_t rfwd:8;
4750 uint64_t rfpe:1;
4751 uint64_t rffe:1;
4752 uint64_t reserved_10_63:54;
4753#endif
54293ec3
DD		 4754 } s;
4755 struct cvmx_mio_uartx_rfw_s cn30xx;
4756 struct cvmx_mio_uartx_rfw_s cn31xx;
4757 struct cvmx_mio_uartx_rfw_s cn38xx;
4758 struct cvmx_mio_uartx_rfw_s cn38xxp2;
4759 struct cvmx_mio_uartx_rfw_s cn50xx;
4760 struct cvmx_mio_uartx_rfw_s cn52xx;
4761 struct cvmx_mio_uartx_rfw_s cn52xxp1;
4762 struct cvmx_mio_uartx_rfw_s cn56xx;
4763 struct cvmx_mio_uartx_rfw_s cn56xxp1;
4764 struct cvmx_mio_uartx_rfw_s cn58xx;
4765 struct cvmx_mio_uartx_rfw_s cn58xxp1;
751c9f68 4766 struct cvmx_mio_uartx_rfw_s cn61xx;
aa32a955
DD		 4767 struct cvmx_mio_uartx_rfw_s cn63xx;
4768 struct cvmx_mio_uartx_rfw_s cn63xxp1;
751c9f68
DD		 4769 struct cvmx_mio_uartx_rfw_s cn66xx;
4770 struct cvmx_mio_uartx_rfw_s cn68xx;
4771 struct cvmx_mio_uartx_rfw_s cn68xxp1;
c5aa59e8 4772 struct cvmx_mio_uartx_rfw_s cnf71xx;
54293ec3
DD		 4773};
4774
4775union cvmx_mio_uartx_sbcr {
4776 uint64_t u64;
4777 struct cvmx_mio_uartx_sbcr_s {
c5aa59e8 4778#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4779 uint64_t reserved_1_63:63;
4780 uint64_t sbcr:1;
c5aa59e8
DD		 4781#else
4782 uint64_t sbcr:1;
4783 uint64_t reserved_1_63:63;
4784#endif
54293ec3
DD		 4785 } s;
4786 struct cvmx_mio_uartx_sbcr_s cn30xx;
4787 struct cvmx_mio_uartx_sbcr_s cn31xx;
4788 struct cvmx_mio_uartx_sbcr_s cn38xx;
4789 struct cvmx_mio_uartx_sbcr_s cn38xxp2;
4790 struct cvmx_mio_uartx_sbcr_s cn50xx;
4791 struct cvmx_mio_uartx_sbcr_s cn52xx;
4792 struct cvmx_mio_uartx_sbcr_s cn52xxp1;
4793 struct cvmx_mio_uartx_sbcr_s cn56xx;
4794 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
4795 struct cvmx_mio_uartx_sbcr_s cn58xx;
4796 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
751c9f68 4797 struct cvmx_mio_uartx_sbcr_s cn61xx;
aa32a955
DD		 4798 struct cvmx_mio_uartx_sbcr_s cn63xx;
4799 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
751c9f68
DD		 4800 struct cvmx_mio_uartx_sbcr_s cn66xx;
4801 struct cvmx_mio_uartx_sbcr_s cn68xx;
4802 struct cvmx_mio_uartx_sbcr_s cn68xxp1;
c5aa59e8 4803 struct cvmx_mio_uartx_sbcr_s cnf71xx;
54293ec3
DD		 4804};
4805
4806union cvmx_mio_uartx_scr {
4807 uint64_t u64;
4808 struct cvmx_mio_uartx_scr_s {
c5aa59e8 4809#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4810 uint64_t reserved_8_63:56;
4811 uint64_t scr:8;
c5aa59e8
DD		 4812#else
4813 uint64_t scr:8;
4814 uint64_t reserved_8_63:56;
4815#endif
54293ec3
DD		 4816 } s;
4817 struct cvmx_mio_uartx_scr_s cn30xx;
4818 struct cvmx_mio_uartx_scr_s cn31xx;
4819 struct cvmx_mio_uartx_scr_s cn38xx;
4820 struct cvmx_mio_uartx_scr_s cn38xxp2;
4821 struct cvmx_mio_uartx_scr_s cn50xx;
4822 struct cvmx_mio_uartx_scr_s cn52xx;
4823 struct cvmx_mio_uartx_scr_s cn52xxp1;
4824 struct cvmx_mio_uartx_scr_s cn56xx;
4825 struct cvmx_mio_uartx_scr_s cn56xxp1;
4826 struct cvmx_mio_uartx_scr_s cn58xx;
4827 struct cvmx_mio_uartx_scr_s cn58xxp1;
751c9f68 4828 struct cvmx_mio_uartx_scr_s cn61xx;
aa32a955
DD		 4829 struct cvmx_mio_uartx_scr_s cn63xx;
4830 struct cvmx_mio_uartx_scr_s cn63xxp1;
751c9f68
DD		 4831 struct cvmx_mio_uartx_scr_s cn66xx;
4832 struct cvmx_mio_uartx_scr_s cn68xx;
4833 struct cvmx_mio_uartx_scr_s cn68xxp1;
c5aa59e8 4834 struct cvmx_mio_uartx_scr_s cnf71xx;
54293ec3
DD		 4835};
4836
4837union cvmx_mio_uartx_sfe {
4838 uint64_t u64;
4839 struct cvmx_mio_uartx_sfe_s {
c5aa59e8 4840#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4841 uint64_t reserved_1_63:63;
4842 uint64_t sfe:1;
c5aa59e8
DD		 4843#else
4844 uint64_t sfe:1;
4845 uint64_t reserved_1_63:63;
4846#endif
54293ec3
DD		 4847 } s;
4848 struct cvmx_mio_uartx_sfe_s cn30xx;
4849 struct cvmx_mio_uartx_sfe_s cn31xx;
4850 struct cvmx_mio_uartx_sfe_s cn38xx;
4851 struct cvmx_mio_uartx_sfe_s cn38xxp2;
4852 struct cvmx_mio_uartx_sfe_s cn50xx;
4853 struct cvmx_mio_uartx_sfe_s cn52xx;
4854 struct cvmx_mio_uartx_sfe_s cn52xxp1;
4855 struct cvmx_mio_uartx_sfe_s cn56xx;
4856 struct cvmx_mio_uartx_sfe_s cn56xxp1;
4857 struct cvmx_mio_uartx_sfe_s cn58xx;
4858 struct cvmx_mio_uartx_sfe_s cn58xxp1;
751c9f68 4859 struct cvmx_mio_uartx_sfe_s cn61xx;
aa32a955
DD		 4860 struct cvmx_mio_uartx_sfe_s cn63xx;
4861 struct cvmx_mio_uartx_sfe_s cn63xxp1;
751c9f68
DD		 4862 struct cvmx_mio_uartx_sfe_s cn66xx;
4863 struct cvmx_mio_uartx_sfe_s cn68xx;
4864 struct cvmx_mio_uartx_sfe_s cn68xxp1;
c5aa59e8 4865 struct cvmx_mio_uartx_sfe_s cnf71xx;
54293ec3
DD		 4866};
4867
4868union cvmx_mio_uartx_srr {
4869 uint64_t u64;
4870 struct cvmx_mio_uartx_srr_s {
c5aa59e8 4871#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4872 uint64_t reserved_3_63:61;
4873 uint64_t stfr:1;
4874 uint64_t srfr:1;
4875 uint64_t usr:1;
c5aa59e8
DD		 4876#else
4877 uint64_t usr:1;
4878 uint64_t srfr:1;
4879 uint64_t stfr:1;
4880 uint64_t reserved_3_63:61;
4881#endif
54293ec3
DD		 4882 } s;
4883 struct cvmx_mio_uartx_srr_s cn30xx;
4884 struct cvmx_mio_uartx_srr_s cn31xx;
4885 struct cvmx_mio_uartx_srr_s cn38xx;
4886 struct cvmx_mio_uartx_srr_s cn38xxp2;
4887 struct cvmx_mio_uartx_srr_s cn50xx;
4888 struct cvmx_mio_uartx_srr_s cn52xx;
4889 struct cvmx_mio_uartx_srr_s cn52xxp1;
4890 struct cvmx_mio_uartx_srr_s cn56xx;
4891 struct cvmx_mio_uartx_srr_s cn56xxp1;
4892 struct cvmx_mio_uartx_srr_s cn58xx;
4893 struct cvmx_mio_uartx_srr_s cn58xxp1;
751c9f68 4894 struct cvmx_mio_uartx_srr_s cn61xx;
aa32a955
DD		 4895 struct cvmx_mio_uartx_srr_s cn63xx;
4896 struct cvmx_mio_uartx_srr_s cn63xxp1;
751c9f68
DD		 4897 struct cvmx_mio_uartx_srr_s cn66xx;
4898 struct cvmx_mio_uartx_srr_s cn68xx;
4899 struct cvmx_mio_uartx_srr_s cn68xxp1;
c5aa59e8 4900 struct cvmx_mio_uartx_srr_s cnf71xx;
54293ec3
DD		 4901};
4902
4903union cvmx_mio_uartx_srt {
4904 uint64_t u64;
4905 struct cvmx_mio_uartx_srt_s {
c5aa59e8 4906#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4907 uint64_t reserved_2_63:62;
4908 uint64_t srt:2;
c5aa59e8
DD		 4909#else
4910 uint64_t srt:2;
4911 uint64_t reserved_2_63:62;
4912#endif
54293ec3
DD		 4913 } s;
4914 struct cvmx_mio_uartx_srt_s cn30xx;
4915 struct cvmx_mio_uartx_srt_s cn31xx;
4916 struct cvmx_mio_uartx_srt_s cn38xx;
4917 struct cvmx_mio_uartx_srt_s cn38xxp2;
4918 struct cvmx_mio_uartx_srt_s cn50xx;
4919 struct cvmx_mio_uartx_srt_s cn52xx;
4920 struct cvmx_mio_uartx_srt_s cn52xxp1;
4921 struct cvmx_mio_uartx_srt_s cn56xx;
4922 struct cvmx_mio_uartx_srt_s cn56xxp1;
4923 struct cvmx_mio_uartx_srt_s cn58xx;
4924 struct cvmx_mio_uartx_srt_s cn58xxp1;
751c9f68 4925 struct cvmx_mio_uartx_srt_s cn61xx;
aa32a955
DD		 4926 struct cvmx_mio_uartx_srt_s cn63xx;
4927 struct cvmx_mio_uartx_srt_s cn63xxp1;
751c9f68
DD		 4928 struct cvmx_mio_uartx_srt_s cn66xx;
4929 struct cvmx_mio_uartx_srt_s cn68xx;
4930 struct cvmx_mio_uartx_srt_s cn68xxp1;
c5aa59e8 4931 struct cvmx_mio_uartx_srt_s cnf71xx;
54293ec3
DD		 4932};
4933
4934union cvmx_mio_uartx_srts {
4935 uint64_t u64;
4936 struct cvmx_mio_uartx_srts_s {
c5aa59e8 4937#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4938 uint64_t reserved_1_63:63;
4939 uint64_t srts:1;
c5aa59e8
DD		 4940#else
4941 uint64_t srts:1;
4942 uint64_t reserved_1_63:63;
4943#endif
54293ec3
DD		 4944 } s;
4945 struct cvmx_mio_uartx_srts_s cn30xx;
4946 struct cvmx_mio_uartx_srts_s cn31xx;
4947 struct cvmx_mio_uartx_srts_s cn38xx;
4948 struct cvmx_mio_uartx_srts_s cn38xxp2;
4949 struct cvmx_mio_uartx_srts_s cn50xx;
4950 struct cvmx_mio_uartx_srts_s cn52xx;
4951 struct cvmx_mio_uartx_srts_s cn52xxp1;
4952 struct cvmx_mio_uartx_srts_s cn56xx;
4953 struct cvmx_mio_uartx_srts_s cn56xxp1;
4954 struct cvmx_mio_uartx_srts_s cn58xx;
4955 struct cvmx_mio_uartx_srts_s cn58xxp1;
751c9f68 4956 struct cvmx_mio_uartx_srts_s cn61xx;
aa32a955
DD		 4957 struct cvmx_mio_uartx_srts_s cn63xx;
4958 struct cvmx_mio_uartx_srts_s cn63xxp1;
751c9f68
DD		 4959 struct cvmx_mio_uartx_srts_s cn66xx;
4960 struct cvmx_mio_uartx_srts_s cn68xx;
4961 struct cvmx_mio_uartx_srts_s cn68xxp1;
c5aa59e8 4962 struct cvmx_mio_uartx_srts_s cnf71xx;
54293ec3
DD		 4963};
4964
4965union cvmx_mio_uartx_stt {
4966 uint64_t u64;
4967 struct cvmx_mio_uartx_stt_s {
c5aa59e8 4968#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 4969 uint64_t reserved_2_63:62;
4970 uint64_t stt:2;
c5aa59e8
DD		 4971#else
4972 uint64_t stt:2;
4973 uint64_t reserved_2_63:62;
4974#endif
54293ec3
DD		 4975 } s;
4976 struct cvmx_mio_uartx_stt_s cn30xx;
4977 struct cvmx_mio_uartx_stt_s cn31xx;
4978 struct cvmx_mio_uartx_stt_s cn38xx;
4979 struct cvmx_mio_uartx_stt_s cn38xxp2;
4980 struct cvmx_mio_uartx_stt_s cn50xx;
4981 struct cvmx_mio_uartx_stt_s cn52xx;
4982 struct cvmx_mio_uartx_stt_s cn52xxp1;
4983 struct cvmx_mio_uartx_stt_s cn56xx;
4984 struct cvmx_mio_uartx_stt_s cn56xxp1;
4985 struct cvmx_mio_uartx_stt_s cn58xx;
4986 struct cvmx_mio_uartx_stt_s cn58xxp1;
751c9f68 4987 struct cvmx_mio_uartx_stt_s cn61xx;
aa32a955
DD		 4988 struct cvmx_mio_uartx_stt_s cn63xx;
4989 struct cvmx_mio_uartx_stt_s cn63xxp1;
751c9f68
DD		 4990 struct cvmx_mio_uartx_stt_s cn66xx;
4991 struct cvmx_mio_uartx_stt_s cn68xx;
4992 struct cvmx_mio_uartx_stt_s cn68xxp1;
c5aa59e8 4993 struct cvmx_mio_uartx_stt_s cnf71xx;
54293ec3
DD		 4994};
4995
4996union cvmx_mio_uartx_tfl {
4997 uint64_t u64;
4998 struct cvmx_mio_uartx_tfl_s {
c5aa59e8 4999#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5000 uint64_t reserved_7_63:57;
5001 uint64_t tfl:7;
c5aa59e8
DD		 5002#else
5003 uint64_t tfl:7;
5004 uint64_t reserved_7_63:57;
5005#endif
54293ec3
DD		 5006 } s;
5007 struct cvmx_mio_uartx_tfl_s cn30xx;
5008 struct cvmx_mio_uartx_tfl_s cn31xx;
5009 struct cvmx_mio_uartx_tfl_s cn38xx;
5010 struct cvmx_mio_uartx_tfl_s cn38xxp2;
5011 struct cvmx_mio_uartx_tfl_s cn50xx;
5012 struct cvmx_mio_uartx_tfl_s cn52xx;
5013 struct cvmx_mio_uartx_tfl_s cn52xxp1;
5014 struct cvmx_mio_uartx_tfl_s cn56xx;
5015 struct cvmx_mio_uartx_tfl_s cn56xxp1;
5016 struct cvmx_mio_uartx_tfl_s cn58xx;
5017 struct cvmx_mio_uartx_tfl_s cn58xxp1;
751c9f68 5018 struct cvmx_mio_uartx_tfl_s cn61xx;
aa32a955
DD		 5019 struct cvmx_mio_uartx_tfl_s cn63xx;
5020 struct cvmx_mio_uartx_tfl_s cn63xxp1;
751c9f68
DD		 5021 struct cvmx_mio_uartx_tfl_s cn66xx;
5022 struct cvmx_mio_uartx_tfl_s cn68xx;
5023 struct cvmx_mio_uartx_tfl_s cn68xxp1;
c5aa59e8 5024 struct cvmx_mio_uartx_tfl_s cnf71xx;
54293ec3
DD		 5025};
5026
5027union cvmx_mio_uartx_tfr {
5028 uint64_t u64;
5029 struct cvmx_mio_uartx_tfr_s {
c5aa59e8 5030#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5031 uint64_t reserved_8_63:56;
5032 uint64_t tfr:8;
c5aa59e8
DD		 5033#else
5034 uint64_t tfr:8;
5035 uint64_t reserved_8_63:56;
5036#endif
54293ec3
DD		 5037 } s;
5038 struct cvmx_mio_uartx_tfr_s cn30xx;
5039 struct cvmx_mio_uartx_tfr_s cn31xx;
5040 struct cvmx_mio_uartx_tfr_s cn38xx;
5041 struct cvmx_mio_uartx_tfr_s cn38xxp2;
5042 struct cvmx_mio_uartx_tfr_s cn50xx;
5043 struct cvmx_mio_uartx_tfr_s cn52xx;
5044 struct cvmx_mio_uartx_tfr_s cn52xxp1;
5045 struct cvmx_mio_uartx_tfr_s cn56xx;
5046 struct cvmx_mio_uartx_tfr_s cn56xxp1;
5047 struct cvmx_mio_uartx_tfr_s cn58xx;
5048 struct cvmx_mio_uartx_tfr_s cn58xxp1;
751c9f68 5049 struct cvmx_mio_uartx_tfr_s cn61xx;
aa32a955
DD		 5050 struct cvmx_mio_uartx_tfr_s cn63xx;
5051 struct cvmx_mio_uartx_tfr_s cn63xxp1;
751c9f68
DD		 5052 struct cvmx_mio_uartx_tfr_s cn66xx;
5053 struct cvmx_mio_uartx_tfr_s cn68xx;
5054 struct cvmx_mio_uartx_tfr_s cn68xxp1;
c5aa59e8 5055 struct cvmx_mio_uartx_tfr_s cnf71xx;
54293ec3
DD		 5056};
5057
5058union cvmx_mio_uartx_thr {
5059 uint64_t u64;
5060 struct cvmx_mio_uartx_thr_s {
c5aa59e8 5061#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5062 uint64_t reserved_8_63:56;
5063 uint64_t thr:8;
c5aa59e8
DD		 5064#else
5065 uint64_t thr:8;
5066 uint64_t reserved_8_63:56;
5067#endif
54293ec3
DD		 5068 } s;
5069 struct cvmx_mio_uartx_thr_s cn30xx;
5070 struct cvmx_mio_uartx_thr_s cn31xx;
5071 struct cvmx_mio_uartx_thr_s cn38xx;
5072 struct cvmx_mio_uartx_thr_s cn38xxp2;
5073 struct cvmx_mio_uartx_thr_s cn50xx;
5074 struct cvmx_mio_uartx_thr_s cn52xx;
5075 struct cvmx_mio_uartx_thr_s cn52xxp1;
5076 struct cvmx_mio_uartx_thr_s cn56xx;
5077 struct cvmx_mio_uartx_thr_s cn56xxp1;
5078 struct cvmx_mio_uartx_thr_s cn58xx;
5079 struct cvmx_mio_uartx_thr_s cn58xxp1;
751c9f68 5080 struct cvmx_mio_uartx_thr_s cn61xx;
aa32a955
DD		 5081 struct cvmx_mio_uartx_thr_s cn63xx;
5082 struct cvmx_mio_uartx_thr_s cn63xxp1;
751c9f68
DD		 5083 struct cvmx_mio_uartx_thr_s cn66xx;
5084 struct cvmx_mio_uartx_thr_s cn68xx;
5085 struct cvmx_mio_uartx_thr_s cn68xxp1;
c5aa59e8 5086 struct cvmx_mio_uartx_thr_s cnf71xx;
54293ec3
DD		 5087};
5088
5089union cvmx_mio_uartx_usr {
5090 uint64_t u64;
5091 struct cvmx_mio_uartx_usr_s {
c5aa59e8 5092#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5093 uint64_t reserved_5_63:59;
5094 uint64_t rff:1;
5095 uint64_t rfne:1;
5096 uint64_t tfe:1;
5097 uint64_t tfnf:1;
5098 uint64_t busy:1;
c5aa59e8
DD		 5099#else
5100 uint64_t busy:1;
5101 uint64_t tfnf:1;
5102 uint64_t tfe:1;
5103 uint64_t rfne:1;
5104 uint64_t rff:1;
5105 uint64_t reserved_5_63:59;
5106#endif
54293ec3
DD		 5107 } s;
5108 struct cvmx_mio_uartx_usr_s cn30xx;
5109 struct cvmx_mio_uartx_usr_s cn31xx;
5110 struct cvmx_mio_uartx_usr_s cn38xx;
5111 struct cvmx_mio_uartx_usr_s cn38xxp2;
5112 struct cvmx_mio_uartx_usr_s cn50xx;
5113 struct cvmx_mio_uartx_usr_s cn52xx;
5114 struct cvmx_mio_uartx_usr_s cn52xxp1;
5115 struct cvmx_mio_uartx_usr_s cn56xx;
5116 struct cvmx_mio_uartx_usr_s cn56xxp1;
5117 struct cvmx_mio_uartx_usr_s cn58xx;
5118 struct cvmx_mio_uartx_usr_s cn58xxp1;
751c9f68 5119 struct cvmx_mio_uartx_usr_s cn61xx;
aa32a955
DD		 5120 struct cvmx_mio_uartx_usr_s cn63xx;
5121 struct cvmx_mio_uartx_usr_s cn63xxp1;
751c9f68
DD		 5122 struct cvmx_mio_uartx_usr_s cn66xx;
5123 struct cvmx_mio_uartx_usr_s cn68xx;
5124 struct cvmx_mio_uartx_usr_s cn68xxp1;
c5aa59e8 5125 struct cvmx_mio_uartx_usr_s cnf71xx;
54293ec3
DD		 5126};
5127
5128union cvmx_mio_uart2_dlh {
5129 uint64_t u64;
5130 struct cvmx_mio_uart2_dlh_s {
c5aa59e8 5131#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5132 uint64_t reserved_8_63:56;
5133 uint64_t dlh:8;
c5aa59e8
DD		 5134#else
5135 uint64_t dlh:8;
5136 uint64_t reserved_8_63:56;
5137#endif
54293ec3
DD		 5138 } s;
5139 struct cvmx_mio_uart2_dlh_s cn52xx;
5140 struct cvmx_mio_uart2_dlh_s cn52xxp1;
5141};
5142
5143union cvmx_mio_uart2_dll {
5144 uint64_t u64;
5145 struct cvmx_mio_uart2_dll_s {
c5aa59e8 5146#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5147 uint64_t reserved_8_63:56;
5148 uint64_t dll:8;
c5aa59e8
DD		 5149#else
5150 uint64_t dll:8;
5151 uint64_t reserved_8_63:56;
5152#endif
54293ec3
DD		 5153 } s;
5154 struct cvmx_mio_uart2_dll_s cn52xx;
5155 struct cvmx_mio_uart2_dll_s cn52xxp1;
5156};
5157
5158union cvmx_mio_uart2_far {
5159 uint64_t u64;
5160 struct cvmx_mio_uart2_far_s {
c5aa59e8 5161#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5162 uint64_t reserved_1_63:63;
5163 uint64_t far:1;
c5aa59e8
DD		 5164#else
5165 uint64_t far:1;
5166 uint64_t reserved_1_63:63;
5167#endif
54293ec3
DD		 5168 } s;
5169 struct cvmx_mio_uart2_far_s cn52xx;
5170 struct cvmx_mio_uart2_far_s cn52xxp1;
5171};
5172
5173union cvmx_mio_uart2_fcr {
5174 uint64_t u64;
5175 struct cvmx_mio_uart2_fcr_s {
c5aa59e8 5176#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5177 uint64_t reserved_8_63:56;
5178 uint64_t rxtrig:2;
5179 uint64_t txtrig:2;
5180 uint64_t reserved_3_3:1;
5181 uint64_t txfr:1;
5182 uint64_t rxfr:1;
5183 uint64_t en:1;
c5aa59e8
DD		 5184#else
5185 uint64_t en:1;
5186 uint64_t rxfr:1;
5187 uint64_t txfr:1;
5188 uint64_t reserved_3_3:1;
5189 uint64_t txtrig:2;
5190 uint64_t rxtrig:2;
5191 uint64_t reserved_8_63:56;
5192#endif
54293ec3
DD		 5193 } s;
5194 struct cvmx_mio_uart2_fcr_s cn52xx;
5195 struct cvmx_mio_uart2_fcr_s cn52xxp1;
5196};
5197
5198union cvmx_mio_uart2_htx {
5199 uint64_t u64;
5200 struct cvmx_mio_uart2_htx_s {
c5aa59e8 5201#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5202 uint64_t reserved_1_63:63;
5203 uint64_t htx:1;
c5aa59e8
DD		 5204#else
5205 uint64_t htx:1;
5206 uint64_t reserved_1_63:63;
5207#endif
54293ec3
DD		 5208 } s;
5209 struct cvmx_mio_uart2_htx_s cn52xx;
5210 struct cvmx_mio_uart2_htx_s cn52xxp1;
5211};
5212
5213union cvmx_mio_uart2_ier {
5214 uint64_t u64;
5215 struct cvmx_mio_uart2_ier_s {
c5aa59e8 5216#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5217 uint64_t reserved_8_63:56;
5218 uint64_t ptime:1;
5219 uint64_t reserved_4_6:3;
5220 uint64_t edssi:1;
5221 uint64_t elsi:1;
5222 uint64_t etbei:1;
5223 uint64_t erbfi:1;
c5aa59e8
DD		 5224#else
5225 uint64_t erbfi:1;
5226 uint64_t etbei:1;
5227 uint64_t elsi:1;
5228 uint64_t edssi:1;
5229 uint64_t reserved_4_6:3;
5230 uint64_t ptime:1;
5231 uint64_t reserved_8_63:56;
5232#endif
54293ec3
DD		 5233 } s;
5234 struct cvmx_mio_uart2_ier_s cn52xx;
5235 struct cvmx_mio_uart2_ier_s cn52xxp1;
5236};
5237
5238union cvmx_mio_uart2_iir {
5239 uint64_t u64;
5240 struct cvmx_mio_uart2_iir_s {
c5aa59e8 5241#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5242 uint64_t reserved_8_63:56;
5243 uint64_t fen:2;
5244 uint64_t reserved_4_5:2;
5245 uint64_t iid:4;
c5aa59e8
DD		 5246#else
5247 uint64_t iid:4;
5248 uint64_t reserved_4_5:2;
5249 uint64_t fen:2;
5250 uint64_t reserved_8_63:56;
5251#endif
54293ec3
DD		 5252 } s;
5253 struct cvmx_mio_uart2_iir_s cn52xx;
5254 struct cvmx_mio_uart2_iir_s cn52xxp1;
5255};
5256
5257union cvmx_mio_uart2_lcr {
5258 uint64_t u64;
5259 struct cvmx_mio_uart2_lcr_s {
c5aa59e8 5260#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5261 uint64_t reserved_8_63:56;
5262 uint64_t dlab:1;
5263 uint64_t brk:1;
5264 uint64_t reserved_5_5:1;
5265 uint64_t eps:1;
5266 uint64_t pen:1;
5267 uint64_t stop:1;
5268 uint64_t cls:2;
c5aa59e8
DD		 5269#else
5270 uint64_t cls:2;
5271 uint64_t stop:1;
5272 uint64_t pen:1;
5273 uint64_t eps:1;
5274 uint64_t reserved_5_5:1;
5275 uint64_t brk:1;
5276 uint64_t dlab:1;
5277 uint64_t reserved_8_63:56;
5278#endif
54293ec3
DD		 5279 } s;
5280 struct cvmx_mio_uart2_lcr_s cn52xx;
5281 struct cvmx_mio_uart2_lcr_s cn52xxp1;
5282};
5283
5284union cvmx_mio_uart2_lsr {
5285 uint64_t u64;
5286 struct cvmx_mio_uart2_lsr_s {
c5aa59e8 5287#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5288 uint64_t reserved_8_63:56;
5289 uint64_t ferr:1;
5290 uint64_t temt:1;
5291 uint64_t thre:1;
5292 uint64_t bi:1;
5293 uint64_t fe:1;
5294 uint64_t pe:1;
5295 uint64_t oe:1;
5296 uint64_t dr:1;
c5aa59e8
DD		 5297#else
5298 uint64_t dr:1;
5299 uint64_t oe:1;
5300 uint64_t pe:1;
5301 uint64_t fe:1;
5302 uint64_t bi:1;
5303 uint64_t thre:1;
5304 uint64_t temt:1;
5305 uint64_t ferr:1;
5306 uint64_t reserved_8_63:56;
5307#endif
54293ec3
DD		 5308 } s;
5309 struct cvmx_mio_uart2_lsr_s cn52xx;
5310 struct cvmx_mio_uart2_lsr_s cn52xxp1;
5311};
5312
5313union cvmx_mio_uart2_mcr {
5314 uint64_t u64;
5315 struct cvmx_mio_uart2_mcr_s {
c5aa59e8 5316#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5317 uint64_t reserved_6_63:58;
5318 uint64_t afce:1;
5319 uint64_t loop:1;
5320 uint64_t out2:1;
5321 uint64_t out1:1;
5322 uint64_t rts:1;
5323 uint64_t dtr:1;
c5aa59e8
DD		 5324#else
5325 uint64_t dtr:1;
5326 uint64_t rts:1;
5327 uint64_t out1:1;
5328 uint64_t out2:1;
5329 uint64_t loop:1;
5330 uint64_t afce:1;
5331 uint64_t reserved_6_63:58;
5332#endif
54293ec3
DD		 5333 } s;
5334 struct cvmx_mio_uart2_mcr_s cn52xx;
5335 struct cvmx_mio_uart2_mcr_s cn52xxp1;
5336};
5337
5338union cvmx_mio_uart2_msr {
5339 uint64_t u64;
5340 struct cvmx_mio_uart2_msr_s {
c5aa59e8 5341#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5342 uint64_t reserved_8_63:56;
5343 uint64_t dcd:1;
5344 uint64_t ri:1;
5345 uint64_t dsr:1;
5346 uint64_t cts:1;
5347 uint64_t ddcd:1;
5348 uint64_t teri:1;
5349 uint64_t ddsr:1;
5350 uint64_t dcts:1;
c5aa59e8
DD		 5351#else
5352 uint64_t dcts:1;
5353 uint64_t ddsr:1;
5354 uint64_t teri:1;
5355 uint64_t ddcd:1;
5356 uint64_t cts:1;
5357 uint64_t dsr:1;
5358 uint64_t ri:1;
5359 uint64_t dcd:1;
5360 uint64_t reserved_8_63:56;
5361#endif
54293ec3
DD		 5362 } s;
5363 struct cvmx_mio_uart2_msr_s cn52xx;
5364 struct cvmx_mio_uart2_msr_s cn52xxp1;
5365};
5366
5367union cvmx_mio_uart2_rbr {
5368 uint64_t u64;
5369 struct cvmx_mio_uart2_rbr_s {
c5aa59e8 5370#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5371 uint64_t reserved_8_63:56;
5372 uint64_t rbr:8;
c5aa59e8
DD		 5373#else
5374 uint64_t rbr:8;
5375 uint64_t reserved_8_63:56;
5376#endif
54293ec3
DD		 5377 } s;
5378 struct cvmx_mio_uart2_rbr_s cn52xx;
5379 struct cvmx_mio_uart2_rbr_s cn52xxp1;
5380};
5381
5382union cvmx_mio_uart2_rfl {
5383 uint64_t u64;
5384 struct cvmx_mio_uart2_rfl_s {
c5aa59e8 5385#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5386 uint64_t reserved_7_63:57;
5387 uint64_t rfl:7;
c5aa59e8
DD		 5388#else
5389 uint64_t rfl:7;
5390 uint64_t reserved_7_63:57;
5391#endif
54293ec3
DD		 5392 } s;
5393 struct cvmx_mio_uart2_rfl_s cn52xx;
5394 struct cvmx_mio_uart2_rfl_s cn52xxp1;
5395};
5396
5397union cvmx_mio_uart2_rfw {
5398 uint64_t u64;
5399 struct cvmx_mio_uart2_rfw_s {
c5aa59e8 5400#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5401 uint64_t reserved_10_63:54;
5402 uint64_t rffe:1;
5403 uint64_t rfpe:1;
5404 uint64_t rfwd:8;
c5aa59e8
DD		 5405#else
5406 uint64_t rfwd:8;
5407 uint64_t rfpe:1;
5408 uint64_t rffe:1;
5409 uint64_t reserved_10_63:54;
5410#endif
54293ec3
DD		 5411 } s;
5412 struct cvmx_mio_uart2_rfw_s cn52xx;
5413 struct cvmx_mio_uart2_rfw_s cn52xxp1;
5414};
5415
5416union cvmx_mio_uart2_sbcr {
5417 uint64_t u64;
5418 struct cvmx_mio_uart2_sbcr_s {
c5aa59e8 5419#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5420 uint64_t reserved_1_63:63;
5421 uint64_t sbcr:1;
c5aa59e8
DD		 5422#else
5423 uint64_t sbcr:1;
5424 uint64_t reserved_1_63:63;
5425#endif
54293ec3
DD		 5426 } s;
5427 struct cvmx_mio_uart2_sbcr_s cn52xx;
5428 struct cvmx_mio_uart2_sbcr_s cn52xxp1;
5429};
5430
5431union cvmx_mio_uart2_scr {
5432 uint64_t u64;
5433 struct cvmx_mio_uart2_scr_s {
c5aa59e8 5434#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5435 uint64_t reserved_8_63:56;
5436 uint64_t scr:8;
c5aa59e8
DD		 5437#else
5438 uint64_t scr:8;
5439 uint64_t reserved_8_63:56;
5440#endif
54293ec3
DD		 5441 } s;
5442 struct cvmx_mio_uart2_scr_s cn52xx;
5443 struct cvmx_mio_uart2_scr_s cn52xxp1;
5444};
5445
5446union cvmx_mio_uart2_sfe {
5447 uint64_t u64;
5448 struct cvmx_mio_uart2_sfe_s {
c5aa59e8 5449#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5450 uint64_t reserved_1_63:63;
5451 uint64_t sfe:1;
c5aa59e8
DD		 5452#else
5453 uint64_t sfe:1;
5454 uint64_t reserved_1_63:63;
5455#endif
54293ec3
DD		 5456 } s;
5457 struct cvmx_mio_uart2_sfe_s cn52xx;
5458 struct cvmx_mio_uart2_sfe_s cn52xxp1;
5459};
5460
5461union cvmx_mio_uart2_srr {
5462 uint64_t u64;
5463 struct cvmx_mio_uart2_srr_s {
c5aa59e8 5464#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5465 uint64_t reserved_3_63:61;
5466 uint64_t stfr:1;
5467 uint64_t srfr:1;
5468 uint64_t usr:1;
c5aa59e8
DD		 5469#else
5470 uint64_t usr:1;
5471 uint64_t srfr:1;
5472 uint64_t stfr:1;
5473 uint64_t reserved_3_63:61;
5474#endif
54293ec3
DD		 5475 } s;
5476 struct cvmx_mio_uart2_srr_s cn52xx;
5477 struct cvmx_mio_uart2_srr_s cn52xxp1;
5478};
5479
5480union cvmx_mio_uart2_srt {
5481 uint64_t u64;
5482 struct cvmx_mio_uart2_srt_s {
c5aa59e8 5483#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5484 uint64_t reserved_2_63:62;
5485 uint64_t srt:2;
c5aa59e8
DD		 5486#else
5487 uint64_t srt:2;
5488 uint64_t reserved_2_63:62;
5489#endif
54293ec3
DD		 5490 } s;
5491 struct cvmx_mio_uart2_srt_s cn52xx;
5492 struct cvmx_mio_uart2_srt_s cn52xxp1;
5493};
5494
5495union cvmx_mio_uart2_srts {
5496 uint64_t u64;
5497 struct cvmx_mio_uart2_srts_s {
c5aa59e8 5498#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5499 uint64_t reserved_1_63:63;
5500 uint64_t srts:1;
c5aa59e8
DD		 5501#else
5502 uint64_t srts:1;
5503 uint64_t reserved_1_63:63;
5504#endif
54293ec3
DD		 5505 } s;
5506 struct cvmx_mio_uart2_srts_s cn52xx;
5507 struct cvmx_mio_uart2_srts_s cn52xxp1;
5508};
5509
5510union cvmx_mio_uart2_stt {
5511 uint64_t u64;
5512 struct cvmx_mio_uart2_stt_s {
c5aa59e8 5513#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5514 uint64_t reserved_2_63:62;
5515 uint64_t stt:2;
c5aa59e8
DD		 5516#else
5517 uint64_t stt:2;
5518 uint64_t reserved_2_63:62;
5519#endif
54293ec3
DD		 5520 } s;
5521 struct cvmx_mio_uart2_stt_s cn52xx;
5522 struct cvmx_mio_uart2_stt_s cn52xxp1;
5523};
5524
5525union cvmx_mio_uart2_tfl {
5526 uint64_t u64;
5527 struct cvmx_mio_uart2_tfl_s {
c5aa59e8 5528#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5529 uint64_t reserved_7_63:57;
5530 uint64_t tfl:7;
c5aa59e8
DD		 5531#else
5532 uint64_t tfl:7;
5533 uint64_t reserved_7_63:57;
5534#endif
54293ec3
DD		 5535 } s;
5536 struct cvmx_mio_uart2_tfl_s cn52xx;
5537 struct cvmx_mio_uart2_tfl_s cn52xxp1;
5538};
5539
5540union cvmx_mio_uart2_tfr {
5541 uint64_t u64;
5542 struct cvmx_mio_uart2_tfr_s {
c5aa59e8 5543#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5544 uint64_t reserved_8_63:56;
5545 uint64_t tfr:8;
c5aa59e8
DD		 5546#else
5547 uint64_t tfr:8;
5548 uint64_t reserved_8_63:56;
5549#endif
54293ec3
DD		 5550 } s;
5551 struct cvmx_mio_uart2_tfr_s cn52xx;
5552 struct cvmx_mio_uart2_tfr_s cn52xxp1;
5553};
5554
5555union cvmx_mio_uart2_thr {
5556 uint64_t u64;
5557 struct cvmx_mio_uart2_thr_s {
c5aa59e8 5558#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5559 uint64_t reserved_8_63:56;
5560 uint64_t thr:8;
c5aa59e8
DD		 5561#else
5562 uint64_t thr:8;
5563 uint64_t reserved_8_63:56;
5564#endif
54293ec3
DD		 5565 } s;
5566 struct cvmx_mio_uart2_thr_s cn52xx;
5567 struct cvmx_mio_uart2_thr_s cn52xxp1;
5568};
5569
5570union cvmx_mio_uart2_usr {
5571 uint64_t u64;
5572 struct cvmx_mio_uart2_usr_s {
c5aa59e8 5573#ifdef __BIG_ENDIAN_BITFIELD
54293ec3
DD		 5574 uint64_t reserved_5_63:59;
5575 uint64_t rff:1;
5576 uint64_t rfne:1;
5577 uint64_t tfe:1;
5578 uint64_t tfnf:1;
5579 uint64_t busy:1;
c5aa59e8
DD		 5580#else
5581 uint64_t busy:1;
5582 uint64_t tfnf:1;
5583 uint64_t tfe:1;
5584 uint64_t rfne:1;
5585 uint64_t rff:1;
5586 uint64_t reserved_5_63:59;
5587#endif
54293ec3
DD		 5588 } s;
5589 struct cvmx_mio_uart2_usr_s cn52xx;
5590 struct cvmx_mio_uart2_usr_s cn52xxp1;
5591};
5592
5593#endif
Linux kernel - Deliverables
This page took 0.644141 seconds and 5 git commands to generate.