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80ff0fd3 DD |
1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
c5aa59e8 | 7 | * Copyright (c) 2003-2012 Cavium Networks |
80ff0fd3 DD |
8 | * |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_PKO_DEFS_H__ | |
29 | #define __CVMX_PKO_DEFS_H__ | |
30 | ||
c5aa59e8 DD |
31 | #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) |
32 | #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) | |
33 | #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) | |
34 | #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) | |
35 | #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) | |
36 | #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) | |
37 | #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) | |
38 | #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) | |
39 | #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) | |
40 | #define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) | |
41 | #define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) | |
42 | #define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) | |
43 | #define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) | |
44 | #define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) | |
45 | #define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) | |
46 | #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) | |
47 | #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) | |
48 | #define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) | |
49 | #define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) | |
50 | #define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) | |
51 | #define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) | |
52 | #define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) | |
53 | #define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) | |
54 | #define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) | |
55 | #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) | |
56 | #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) | |
57 | #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) | |
58 | #define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) | |
59 | #define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) | |
60 | #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) | |
61 | #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) | |
62 | #define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) | |
63 | #define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) | |
64 | #define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) | |
65 | #define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) | |
66 | #define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) | |
67 | #define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) | |
68 | #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) | |
69 | #define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) | |
70 | #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) | |
71 | #define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) | |
72 | #define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) | |
73 | #define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) | |
74 | #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) | |
75 | #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) | |
76 | #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) | |
77 | #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) | |
78 | #define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) | |
79 | #define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) | |
80 | #define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) | |
81 | #define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) | |
82 | #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) | |
83 | #define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) | |
84 | #define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) | |
85 | #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) | |
86 | #define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) | |
87 | #define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) | |
80ff0fd3 DD |
88 | |
89 | union cvmx_pko_mem_count0 { | |
90 | uint64_t u64; | |
91 | struct cvmx_pko_mem_count0_s { | |
c5aa59e8 | 92 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
93 | uint64_t reserved_32_63:32; |
94 | uint64_t count:32; | |
c5aa59e8 DD |
95 | #else |
96 | uint64_t count:32; | |
97 | uint64_t reserved_32_63:32; | |
98 | #endif | |
80ff0fd3 DD |
99 | } s; |
100 | struct cvmx_pko_mem_count0_s cn30xx; | |
101 | struct cvmx_pko_mem_count0_s cn31xx; | |
102 | struct cvmx_pko_mem_count0_s cn38xx; | |
103 | struct cvmx_pko_mem_count0_s cn38xxp2; | |
104 | struct cvmx_pko_mem_count0_s cn50xx; | |
105 | struct cvmx_pko_mem_count0_s cn52xx; | |
106 | struct cvmx_pko_mem_count0_s cn52xxp1; | |
107 | struct cvmx_pko_mem_count0_s cn56xx; | |
108 | struct cvmx_pko_mem_count0_s cn56xxp1; | |
109 | struct cvmx_pko_mem_count0_s cn58xx; | |
110 | struct cvmx_pko_mem_count0_s cn58xxp1; | |
c5aa59e8 DD |
111 | struct cvmx_pko_mem_count0_s cn61xx; |
112 | struct cvmx_pko_mem_count0_s cn63xx; | |
113 | struct cvmx_pko_mem_count0_s cn63xxp1; | |
114 | struct cvmx_pko_mem_count0_s cn66xx; | |
115 | struct cvmx_pko_mem_count0_s cn68xx; | |
116 | struct cvmx_pko_mem_count0_s cn68xxp1; | |
117 | struct cvmx_pko_mem_count0_s cnf71xx; | |
80ff0fd3 DD |
118 | }; |
119 | ||
120 | union cvmx_pko_mem_count1 { | |
121 | uint64_t u64; | |
122 | struct cvmx_pko_mem_count1_s { | |
c5aa59e8 | 123 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
124 | uint64_t reserved_48_63:16; |
125 | uint64_t count:48; | |
c5aa59e8 DD |
126 | #else |
127 | uint64_t count:48; | |
128 | uint64_t reserved_48_63:16; | |
129 | #endif | |
80ff0fd3 DD |
130 | } s; |
131 | struct cvmx_pko_mem_count1_s cn30xx; | |
132 | struct cvmx_pko_mem_count1_s cn31xx; | |
133 | struct cvmx_pko_mem_count1_s cn38xx; | |
134 | struct cvmx_pko_mem_count1_s cn38xxp2; | |
135 | struct cvmx_pko_mem_count1_s cn50xx; | |
136 | struct cvmx_pko_mem_count1_s cn52xx; | |
137 | struct cvmx_pko_mem_count1_s cn52xxp1; | |
138 | struct cvmx_pko_mem_count1_s cn56xx; | |
139 | struct cvmx_pko_mem_count1_s cn56xxp1; | |
140 | struct cvmx_pko_mem_count1_s cn58xx; | |
141 | struct cvmx_pko_mem_count1_s cn58xxp1; | |
c5aa59e8 DD |
142 | struct cvmx_pko_mem_count1_s cn61xx; |
143 | struct cvmx_pko_mem_count1_s cn63xx; | |
144 | struct cvmx_pko_mem_count1_s cn63xxp1; | |
145 | struct cvmx_pko_mem_count1_s cn66xx; | |
146 | struct cvmx_pko_mem_count1_s cn68xx; | |
147 | struct cvmx_pko_mem_count1_s cn68xxp1; | |
148 | struct cvmx_pko_mem_count1_s cnf71xx; | |
80ff0fd3 DD |
149 | }; |
150 | ||
151 | union cvmx_pko_mem_debug0 { | |
152 | uint64_t u64; | |
153 | struct cvmx_pko_mem_debug0_s { | |
c5aa59e8 | 154 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
155 | uint64_t fau:28; |
156 | uint64_t cmd:14; | |
157 | uint64_t segs:6; | |
158 | uint64_t size:16; | |
c5aa59e8 DD |
159 | #else |
160 | uint64_t size:16; | |
161 | uint64_t segs:6; | |
162 | uint64_t cmd:14; | |
163 | uint64_t fau:28; | |
164 | #endif | |
80ff0fd3 DD |
165 | } s; |
166 | struct cvmx_pko_mem_debug0_s cn30xx; | |
167 | struct cvmx_pko_mem_debug0_s cn31xx; | |
168 | struct cvmx_pko_mem_debug0_s cn38xx; | |
169 | struct cvmx_pko_mem_debug0_s cn38xxp2; | |
170 | struct cvmx_pko_mem_debug0_s cn50xx; | |
171 | struct cvmx_pko_mem_debug0_s cn52xx; | |
172 | struct cvmx_pko_mem_debug0_s cn52xxp1; | |
173 | struct cvmx_pko_mem_debug0_s cn56xx; | |
174 | struct cvmx_pko_mem_debug0_s cn56xxp1; | |
175 | struct cvmx_pko_mem_debug0_s cn58xx; | |
176 | struct cvmx_pko_mem_debug0_s cn58xxp1; | |
c5aa59e8 DD |
177 | struct cvmx_pko_mem_debug0_s cn61xx; |
178 | struct cvmx_pko_mem_debug0_s cn63xx; | |
179 | struct cvmx_pko_mem_debug0_s cn63xxp1; | |
180 | struct cvmx_pko_mem_debug0_s cn66xx; | |
181 | struct cvmx_pko_mem_debug0_s cn68xx; | |
182 | struct cvmx_pko_mem_debug0_s cn68xxp1; | |
183 | struct cvmx_pko_mem_debug0_s cnf71xx; | |
80ff0fd3 DD |
184 | }; |
185 | ||
186 | union cvmx_pko_mem_debug1 { | |
187 | uint64_t u64; | |
188 | struct cvmx_pko_mem_debug1_s { | |
c5aa59e8 | 189 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
190 | uint64_t i:1; |
191 | uint64_t back:4; | |
192 | uint64_t pool:3; | |
193 | uint64_t size:16; | |
194 | uint64_t ptr:40; | |
c5aa59e8 DD |
195 | #else |
196 | uint64_t ptr:40; | |
197 | uint64_t size:16; | |
198 | uint64_t pool:3; | |
199 | uint64_t back:4; | |
200 | uint64_t i:1; | |
201 | #endif | |
80ff0fd3 DD |
202 | } s; |
203 | struct cvmx_pko_mem_debug1_s cn30xx; | |
204 | struct cvmx_pko_mem_debug1_s cn31xx; | |
205 | struct cvmx_pko_mem_debug1_s cn38xx; | |
206 | struct cvmx_pko_mem_debug1_s cn38xxp2; | |
207 | struct cvmx_pko_mem_debug1_s cn50xx; | |
208 | struct cvmx_pko_mem_debug1_s cn52xx; | |
209 | struct cvmx_pko_mem_debug1_s cn52xxp1; | |
210 | struct cvmx_pko_mem_debug1_s cn56xx; | |
211 | struct cvmx_pko_mem_debug1_s cn56xxp1; | |
212 | struct cvmx_pko_mem_debug1_s cn58xx; | |
213 | struct cvmx_pko_mem_debug1_s cn58xxp1; | |
c5aa59e8 DD |
214 | struct cvmx_pko_mem_debug1_s cn61xx; |
215 | struct cvmx_pko_mem_debug1_s cn63xx; | |
216 | struct cvmx_pko_mem_debug1_s cn63xxp1; | |
217 | struct cvmx_pko_mem_debug1_s cn66xx; | |
218 | struct cvmx_pko_mem_debug1_s cn68xx; | |
219 | struct cvmx_pko_mem_debug1_s cn68xxp1; | |
220 | struct cvmx_pko_mem_debug1_s cnf71xx; | |
80ff0fd3 DD |
221 | }; |
222 | ||
223 | union cvmx_pko_mem_debug10 { | |
224 | uint64_t u64; | |
225 | struct cvmx_pko_mem_debug10_s { | |
c5aa59e8 DD |
226 | #ifdef __BIG_ENDIAN_BITFIELD |
227 | uint64_t reserved_0_63:64; | |
228 | #else | |
80ff0fd3 | 229 | uint64_t reserved_0_63:64; |
c5aa59e8 | 230 | #endif |
80ff0fd3 DD |
231 | } s; |
232 | struct cvmx_pko_mem_debug10_cn30xx { | |
c5aa59e8 | 233 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
234 | uint64_t fau:28; |
235 | uint64_t cmd:14; | |
236 | uint64_t segs:6; | |
237 | uint64_t size:16; | |
c5aa59e8 DD |
238 | #else |
239 | uint64_t size:16; | |
240 | uint64_t segs:6; | |
241 | uint64_t cmd:14; | |
242 | uint64_t fau:28; | |
243 | #endif | |
80ff0fd3 DD |
244 | } cn30xx; |
245 | struct cvmx_pko_mem_debug10_cn30xx cn31xx; | |
246 | struct cvmx_pko_mem_debug10_cn30xx cn38xx; | |
247 | struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; | |
248 | struct cvmx_pko_mem_debug10_cn50xx { | |
c5aa59e8 | 249 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
250 | uint64_t reserved_49_63:15; |
251 | uint64_t ptrs1:17; | |
252 | uint64_t reserved_17_31:15; | |
253 | uint64_t ptrs2:17; | |
c5aa59e8 DD |
254 | #else |
255 | uint64_t ptrs2:17; | |
256 | uint64_t reserved_17_31:15; | |
257 | uint64_t ptrs1:17; | |
258 | uint64_t reserved_49_63:15; | |
259 | #endif | |
80ff0fd3 DD |
260 | } cn50xx; |
261 | struct cvmx_pko_mem_debug10_cn50xx cn52xx; | |
262 | struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; | |
263 | struct cvmx_pko_mem_debug10_cn50xx cn56xx; | |
264 | struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; | |
265 | struct cvmx_pko_mem_debug10_cn50xx cn58xx; | |
266 | struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; | |
c5aa59e8 DD |
267 | struct cvmx_pko_mem_debug10_cn50xx cn61xx; |
268 | struct cvmx_pko_mem_debug10_cn50xx cn63xx; | |
269 | struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; | |
270 | struct cvmx_pko_mem_debug10_cn50xx cn66xx; | |
271 | struct cvmx_pko_mem_debug10_cn50xx cn68xx; | |
272 | struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; | |
273 | struct cvmx_pko_mem_debug10_cn50xx cnf71xx; | |
80ff0fd3 DD |
274 | }; |
275 | ||
276 | union cvmx_pko_mem_debug11 { | |
277 | uint64_t u64; | |
278 | struct cvmx_pko_mem_debug11_s { | |
c5aa59e8 | 279 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
280 | uint64_t i:1; |
281 | uint64_t back:4; | |
282 | uint64_t pool:3; | |
283 | uint64_t size:16; | |
284 | uint64_t reserved_0_39:40; | |
c5aa59e8 DD |
285 | #else |
286 | uint64_t reserved_0_39:40; | |
287 | uint64_t size:16; | |
288 | uint64_t pool:3; | |
289 | uint64_t back:4; | |
290 | uint64_t i:1; | |
291 | #endif | |
80ff0fd3 DD |
292 | } s; |
293 | struct cvmx_pko_mem_debug11_cn30xx { | |
c5aa59e8 | 294 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
295 | uint64_t i:1; |
296 | uint64_t back:4; | |
297 | uint64_t pool:3; | |
298 | uint64_t size:16; | |
299 | uint64_t ptr:40; | |
c5aa59e8 DD |
300 | #else |
301 | uint64_t ptr:40; | |
302 | uint64_t size:16; | |
303 | uint64_t pool:3; | |
304 | uint64_t back:4; | |
305 | uint64_t i:1; | |
306 | #endif | |
80ff0fd3 DD |
307 | } cn30xx; |
308 | struct cvmx_pko_mem_debug11_cn30xx cn31xx; | |
309 | struct cvmx_pko_mem_debug11_cn30xx cn38xx; | |
310 | struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; | |
311 | struct cvmx_pko_mem_debug11_cn50xx { | |
c5aa59e8 | 312 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
313 | uint64_t reserved_23_63:41; |
314 | uint64_t maj:1; | |
315 | uint64_t uid:3; | |
316 | uint64_t sop:1; | |
317 | uint64_t len:1; | |
318 | uint64_t chk:1; | |
319 | uint64_t cnt:13; | |
320 | uint64_t mod:3; | |
c5aa59e8 DD |
321 | #else |
322 | uint64_t mod:3; | |
323 | uint64_t cnt:13; | |
324 | uint64_t chk:1; | |
325 | uint64_t len:1; | |
326 | uint64_t sop:1; | |
327 | uint64_t uid:3; | |
328 | uint64_t maj:1; | |
329 | uint64_t reserved_23_63:41; | |
330 | #endif | |
80ff0fd3 DD |
331 | } cn50xx; |
332 | struct cvmx_pko_mem_debug11_cn50xx cn52xx; | |
333 | struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; | |
334 | struct cvmx_pko_mem_debug11_cn50xx cn56xx; | |
335 | struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; | |
336 | struct cvmx_pko_mem_debug11_cn50xx cn58xx; | |
337 | struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; | |
c5aa59e8 DD |
338 | struct cvmx_pko_mem_debug11_cn50xx cn61xx; |
339 | struct cvmx_pko_mem_debug11_cn50xx cn63xx; | |
340 | struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; | |
341 | struct cvmx_pko_mem_debug11_cn50xx cn66xx; | |
342 | struct cvmx_pko_mem_debug11_cn50xx cn68xx; | |
343 | struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; | |
344 | struct cvmx_pko_mem_debug11_cn50xx cnf71xx; | |
80ff0fd3 DD |
345 | }; |
346 | ||
347 | union cvmx_pko_mem_debug12 { | |
348 | uint64_t u64; | |
349 | struct cvmx_pko_mem_debug12_s { | |
c5aa59e8 | 350 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 | 351 | uint64_t reserved_0_63:64; |
c5aa59e8 DD |
352 | #else |
353 | uint64_t reserved_0_63:64; | |
354 | #endif | |
80ff0fd3 DD |
355 | } s; |
356 | struct cvmx_pko_mem_debug12_cn30xx { | |
c5aa59e8 | 357 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 | 358 | uint64_t data:64; |
c5aa59e8 DD |
359 | #else |
360 | uint64_t data:64; | |
361 | #endif | |
80ff0fd3 DD |
362 | } cn30xx; |
363 | struct cvmx_pko_mem_debug12_cn30xx cn31xx; | |
364 | struct cvmx_pko_mem_debug12_cn30xx cn38xx; | |
365 | struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; | |
366 | struct cvmx_pko_mem_debug12_cn50xx { | |
c5aa59e8 | 367 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
368 | uint64_t fau:28; |
369 | uint64_t cmd:14; | |
370 | uint64_t segs:6; | |
371 | uint64_t size:16; | |
c5aa59e8 DD |
372 | #else |
373 | uint64_t size:16; | |
374 | uint64_t segs:6; | |
375 | uint64_t cmd:14; | |
376 | uint64_t fau:28; | |
377 | #endif | |
80ff0fd3 DD |
378 | } cn50xx; |
379 | struct cvmx_pko_mem_debug12_cn50xx cn52xx; | |
380 | struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; | |
381 | struct cvmx_pko_mem_debug12_cn50xx cn56xx; | |
382 | struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; | |
383 | struct cvmx_pko_mem_debug12_cn50xx cn58xx; | |
384 | struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; | |
c5aa59e8 DD |
385 | struct cvmx_pko_mem_debug12_cn50xx cn61xx; |
386 | struct cvmx_pko_mem_debug12_cn50xx cn63xx; | |
387 | struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; | |
388 | struct cvmx_pko_mem_debug12_cn50xx cn66xx; | |
389 | struct cvmx_pko_mem_debug12_cn68xx { | |
390 | #ifdef __BIG_ENDIAN_BITFIELD | |
391 | uint64_t state:64; | |
392 | #else | |
393 | uint64_t state:64; | |
394 | #endif | |
395 | } cn68xx; | |
396 | struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; | |
397 | struct cvmx_pko_mem_debug12_cn50xx cnf71xx; | |
80ff0fd3 DD |
398 | }; |
399 | ||
400 | union cvmx_pko_mem_debug13 { | |
401 | uint64_t u64; | |
402 | struct cvmx_pko_mem_debug13_s { | |
c5aa59e8 DD |
403 | #ifdef __BIG_ENDIAN_BITFIELD |
404 | uint64_t reserved_0_63:64; | |
405 | #else | |
406 | uint64_t reserved_0_63:64; | |
407 | #endif | |
80ff0fd3 DD |
408 | } s; |
409 | struct cvmx_pko_mem_debug13_cn30xx { | |
c5aa59e8 | 410 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
411 | uint64_t reserved_51_63:13; |
412 | uint64_t widx:17; | |
413 | uint64_t ridx2:17; | |
414 | uint64_t widx2:17; | |
c5aa59e8 DD |
415 | #else |
416 | uint64_t widx2:17; | |
417 | uint64_t ridx2:17; | |
418 | uint64_t widx:17; | |
419 | uint64_t reserved_51_63:13; | |
420 | #endif | |
80ff0fd3 DD |
421 | } cn30xx; |
422 | struct cvmx_pko_mem_debug13_cn30xx cn31xx; | |
423 | struct cvmx_pko_mem_debug13_cn30xx cn38xx; | |
424 | struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; | |
425 | struct cvmx_pko_mem_debug13_cn50xx { | |
c5aa59e8 | 426 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
427 | uint64_t i:1; |
428 | uint64_t back:4; | |
429 | uint64_t pool:3; | |
430 | uint64_t size:16; | |
431 | uint64_t ptr:40; | |
c5aa59e8 DD |
432 | #else |
433 | uint64_t ptr:40; | |
434 | uint64_t size:16; | |
435 | uint64_t pool:3; | |
436 | uint64_t back:4; | |
437 | uint64_t i:1; | |
438 | #endif | |
80ff0fd3 DD |
439 | } cn50xx; |
440 | struct cvmx_pko_mem_debug13_cn50xx cn52xx; | |
441 | struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; | |
442 | struct cvmx_pko_mem_debug13_cn50xx cn56xx; | |
443 | struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; | |
444 | struct cvmx_pko_mem_debug13_cn50xx cn58xx; | |
445 | struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; | |
c5aa59e8 DD |
446 | struct cvmx_pko_mem_debug13_cn50xx cn61xx; |
447 | struct cvmx_pko_mem_debug13_cn50xx cn63xx; | |
448 | struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; | |
449 | struct cvmx_pko_mem_debug13_cn50xx cn66xx; | |
450 | struct cvmx_pko_mem_debug13_cn68xx { | |
451 | #ifdef __BIG_ENDIAN_BITFIELD | |
452 | uint64_t state:64; | |
453 | #else | |
454 | uint64_t state:64; | |
455 | #endif | |
456 | } cn68xx; | |
457 | struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; | |
458 | struct cvmx_pko_mem_debug13_cn50xx cnf71xx; | |
80ff0fd3 DD |
459 | }; |
460 | ||
461 | union cvmx_pko_mem_debug14 { | |
462 | uint64_t u64; | |
463 | struct cvmx_pko_mem_debug14_s { | |
c5aa59e8 | 464 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 | 465 | uint64_t reserved_0_63:64; |
c5aa59e8 DD |
466 | #else |
467 | uint64_t reserved_0_63:64; | |
468 | #endif | |
80ff0fd3 DD |
469 | } s; |
470 | struct cvmx_pko_mem_debug14_cn30xx { | |
c5aa59e8 | 471 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
472 | uint64_t reserved_17_63:47; |
473 | uint64_t ridx:17; | |
c5aa59e8 DD |
474 | #else |
475 | uint64_t ridx:17; | |
476 | uint64_t reserved_17_63:47; | |
477 | #endif | |
80ff0fd3 DD |
478 | } cn30xx; |
479 | struct cvmx_pko_mem_debug14_cn30xx cn31xx; | |
480 | struct cvmx_pko_mem_debug14_cn30xx cn38xx; | |
481 | struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; | |
482 | struct cvmx_pko_mem_debug14_cn52xx { | |
c5aa59e8 DD |
483 | #ifdef __BIG_ENDIAN_BITFIELD |
484 | uint64_t data:64; | |
485 | #else | |
80ff0fd3 | 486 | uint64_t data:64; |
c5aa59e8 | 487 | #endif |
80ff0fd3 DD |
488 | } cn52xx; |
489 | struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; | |
490 | struct cvmx_pko_mem_debug14_cn52xx cn56xx; | |
491 | struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; | |
c5aa59e8 DD |
492 | struct cvmx_pko_mem_debug14_cn52xx cn61xx; |
493 | struct cvmx_pko_mem_debug14_cn52xx cn63xx; | |
494 | struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; | |
495 | struct cvmx_pko_mem_debug14_cn52xx cn66xx; | |
496 | struct cvmx_pko_mem_debug14_cn52xx cnf71xx; | |
80ff0fd3 DD |
497 | }; |
498 | ||
499 | union cvmx_pko_mem_debug2 { | |
500 | uint64_t u64; | |
501 | struct cvmx_pko_mem_debug2_s { | |
c5aa59e8 | 502 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
503 | uint64_t i:1; |
504 | uint64_t back:4; | |
505 | uint64_t pool:3; | |
506 | uint64_t size:16; | |
507 | uint64_t ptr:40; | |
c5aa59e8 DD |
508 | #else |
509 | uint64_t ptr:40; | |
510 | uint64_t size:16; | |
511 | uint64_t pool:3; | |
512 | uint64_t back:4; | |
513 | uint64_t i:1; | |
514 | #endif | |
80ff0fd3 DD |
515 | } s; |
516 | struct cvmx_pko_mem_debug2_s cn30xx; | |
517 | struct cvmx_pko_mem_debug2_s cn31xx; | |
518 | struct cvmx_pko_mem_debug2_s cn38xx; | |
519 | struct cvmx_pko_mem_debug2_s cn38xxp2; | |
520 | struct cvmx_pko_mem_debug2_s cn50xx; | |
521 | struct cvmx_pko_mem_debug2_s cn52xx; | |
522 | struct cvmx_pko_mem_debug2_s cn52xxp1; | |
523 | struct cvmx_pko_mem_debug2_s cn56xx; | |
524 | struct cvmx_pko_mem_debug2_s cn56xxp1; | |
525 | struct cvmx_pko_mem_debug2_s cn58xx; | |
526 | struct cvmx_pko_mem_debug2_s cn58xxp1; | |
c5aa59e8 DD |
527 | struct cvmx_pko_mem_debug2_s cn61xx; |
528 | struct cvmx_pko_mem_debug2_s cn63xx; | |
529 | struct cvmx_pko_mem_debug2_s cn63xxp1; | |
530 | struct cvmx_pko_mem_debug2_s cn66xx; | |
531 | struct cvmx_pko_mem_debug2_s cn68xx; | |
532 | struct cvmx_pko_mem_debug2_s cn68xxp1; | |
533 | struct cvmx_pko_mem_debug2_s cnf71xx; | |
80ff0fd3 DD |
534 | }; |
535 | ||
536 | union cvmx_pko_mem_debug3 { | |
537 | uint64_t u64; | |
538 | struct cvmx_pko_mem_debug3_s { | |
c5aa59e8 DD |
539 | #ifdef __BIG_ENDIAN_BITFIELD |
540 | uint64_t reserved_0_63:64; | |
541 | #else | |
80ff0fd3 | 542 | uint64_t reserved_0_63:64; |
c5aa59e8 | 543 | #endif |
80ff0fd3 DD |
544 | } s; |
545 | struct cvmx_pko_mem_debug3_cn30xx { | |
c5aa59e8 | 546 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
547 | uint64_t i:1; |
548 | uint64_t back:4; | |
549 | uint64_t pool:3; | |
550 | uint64_t size:16; | |
551 | uint64_t ptr:40; | |
c5aa59e8 DD |
552 | #else |
553 | uint64_t ptr:40; | |
554 | uint64_t size:16; | |
555 | uint64_t pool:3; | |
556 | uint64_t back:4; | |
557 | uint64_t i:1; | |
558 | #endif | |
80ff0fd3 DD |
559 | } cn30xx; |
560 | struct cvmx_pko_mem_debug3_cn30xx cn31xx; | |
561 | struct cvmx_pko_mem_debug3_cn30xx cn38xx; | |
562 | struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; | |
563 | struct cvmx_pko_mem_debug3_cn50xx { | |
c5aa59e8 DD |
564 | #ifdef __BIG_ENDIAN_BITFIELD |
565 | uint64_t data:64; | |
566 | #else | |
80ff0fd3 | 567 | uint64_t data:64; |
c5aa59e8 | 568 | #endif |
80ff0fd3 DD |
569 | } cn50xx; |
570 | struct cvmx_pko_mem_debug3_cn50xx cn52xx; | |
571 | struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; | |
572 | struct cvmx_pko_mem_debug3_cn50xx cn56xx; | |
573 | struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; | |
574 | struct cvmx_pko_mem_debug3_cn50xx cn58xx; | |
575 | struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; | |
c5aa59e8 DD |
576 | struct cvmx_pko_mem_debug3_cn50xx cn61xx; |
577 | struct cvmx_pko_mem_debug3_cn50xx cn63xx; | |
578 | struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; | |
579 | struct cvmx_pko_mem_debug3_cn50xx cn66xx; | |
580 | struct cvmx_pko_mem_debug3_cn50xx cn68xx; | |
581 | struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; | |
582 | struct cvmx_pko_mem_debug3_cn50xx cnf71xx; | |
80ff0fd3 DD |
583 | }; |
584 | ||
585 | union cvmx_pko_mem_debug4 { | |
586 | uint64_t u64; | |
587 | struct cvmx_pko_mem_debug4_s { | |
c5aa59e8 DD |
588 | #ifdef __BIG_ENDIAN_BITFIELD |
589 | uint64_t reserved_0_63:64; | |
590 | #else | |
80ff0fd3 | 591 | uint64_t reserved_0_63:64; |
c5aa59e8 | 592 | #endif |
80ff0fd3 DD |
593 | } s; |
594 | struct cvmx_pko_mem_debug4_cn30xx { | |
c5aa59e8 DD |
595 | #ifdef __BIG_ENDIAN_BITFIELD |
596 | uint64_t data:64; | |
597 | #else | |
80ff0fd3 | 598 | uint64_t data:64; |
c5aa59e8 | 599 | #endif |
80ff0fd3 DD |
600 | } cn30xx; |
601 | struct cvmx_pko_mem_debug4_cn30xx cn31xx; | |
602 | struct cvmx_pko_mem_debug4_cn30xx cn38xx; | |
603 | struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; | |
604 | struct cvmx_pko_mem_debug4_cn50xx { | |
c5aa59e8 | 605 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
606 | uint64_t cmnd_segs:3; |
607 | uint64_t cmnd_siz:16; | |
608 | uint64_t cmnd_off:6; | |
609 | uint64_t uid:3; | |
610 | uint64_t dread_sop:1; | |
611 | uint64_t init_dwrite:1; | |
612 | uint64_t chk_once:1; | |
613 | uint64_t chk_mode:1; | |
614 | uint64_t active:1; | |
615 | uint64_t static_p:1; | |
616 | uint64_t qos:3; | |
617 | uint64_t qcb_ridx:5; | |
618 | uint64_t qid_off_max:4; | |
619 | uint64_t qid_off:4; | |
620 | uint64_t qid_base:8; | |
621 | uint64_t wait:1; | |
622 | uint64_t minor:2; | |
623 | uint64_t major:3; | |
c5aa59e8 DD |
624 | #else |
625 | uint64_t major:3; | |
626 | uint64_t minor:2; | |
627 | uint64_t wait:1; | |
628 | uint64_t qid_base:8; | |
629 | uint64_t qid_off:4; | |
630 | uint64_t qid_off_max:4; | |
631 | uint64_t qcb_ridx:5; | |
632 | uint64_t qos:3; | |
633 | uint64_t static_p:1; | |
634 | uint64_t active:1; | |
635 | uint64_t chk_mode:1; | |
636 | uint64_t chk_once:1; | |
637 | uint64_t init_dwrite:1; | |
638 | uint64_t dread_sop:1; | |
639 | uint64_t uid:3; | |
640 | uint64_t cmnd_off:6; | |
641 | uint64_t cmnd_siz:16; | |
642 | uint64_t cmnd_segs:3; | |
643 | #endif | |
80ff0fd3 DD |
644 | } cn50xx; |
645 | struct cvmx_pko_mem_debug4_cn52xx { | |
c5aa59e8 | 646 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
647 | uint64_t curr_siz:8; |
648 | uint64_t curr_off:16; | |
649 | uint64_t cmnd_segs:6; | |
650 | uint64_t cmnd_siz:16; | |
651 | uint64_t cmnd_off:6; | |
652 | uint64_t uid:2; | |
653 | uint64_t dread_sop:1; | |
654 | uint64_t init_dwrite:1; | |
655 | uint64_t chk_once:1; | |
656 | uint64_t chk_mode:1; | |
657 | uint64_t wait:1; | |
658 | uint64_t minor:2; | |
659 | uint64_t major:3; | |
c5aa59e8 DD |
660 | #else |
661 | uint64_t major:3; | |
662 | uint64_t minor:2; | |
663 | uint64_t wait:1; | |
664 | uint64_t chk_mode:1; | |
665 | uint64_t chk_once:1; | |
666 | uint64_t init_dwrite:1; | |
667 | uint64_t dread_sop:1; | |
668 | uint64_t uid:2; | |
669 | uint64_t cmnd_off:6; | |
670 | uint64_t cmnd_siz:16; | |
671 | uint64_t cmnd_segs:6; | |
672 | uint64_t curr_off:16; | |
673 | uint64_t curr_siz:8; | |
674 | #endif | |
80ff0fd3 DD |
675 | } cn52xx; |
676 | struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; | |
677 | struct cvmx_pko_mem_debug4_cn52xx cn56xx; | |
678 | struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; | |
679 | struct cvmx_pko_mem_debug4_cn50xx cn58xx; | |
680 | struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; | |
c5aa59e8 DD |
681 | struct cvmx_pko_mem_debug4_cn52xx cn61xx; |
682 | struct cvmx_pko_mem_debug4_cn52xx cn63xx; | |
683 | struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; | |
684 | struct cvmx_pko_mem_debug4_cn52xx cn66xx; | |
685 | struct cvmx_pko_mem_debug4_cn52xx cn68xx; | |
686 | struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; | |
687 | struct cvmx_pko_mem_debug4_cn52xx cnf71xx; | |
80ff0fd3 DD |
688 | }; |
689 | ||
690 | union cvmx_pko_mem_debug5 { | |
691 | uint64_t u64; | |
692 | struct cvmx_pko_mem_debug5_s { | |
c5aa59e8 | 693 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 | 694 | uint64_t reserved_0_63:64; |
c5aa59e8 DD |
695 | #else |
696 | uint64_t reserved_0_63:64; | |
697 | #endif | |
80ff0fd3 DD |
698 | } s; |
699 | struct cvmx_pko_mem_debug5_cn30xx { | |
c5aa59e8 | 700 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
701 | uint64_t dwri_mod:1; |
702 | uint64_t dwri_sop:1; | |
703 | uint64_t dwri_len:1; | |
704 | uint64_t dwri_cnt:13; | |
705 | uint64_t cmnd_siz:16; | |
706 | uint64_t uid:1; | |
707 | uint64_t xfer_wor:1; | |
708 | uint64_t xfer_dwr:1; | |
709 | uint64_t cbuf_fre:1; | |
710 | uint64_t reserved_27_27:1; | |
711 | uint64_t chk_mode:1; | |
712 | uint64_t active:1; | |
713 | uint64_t qos:3; | |
714 | uint64_t qcb_ridx:5; | |
715 | uint64_t qid_off:3; | |
716 | uint64_t qid_base:7; | |
717 | uint64_t wait:1; | |
718 | uint64_t minor:2; | |
719 | uint64_t major:4; | |
c5aa59e8 DD |
720 | #else |
721 | uint64_t major:4; | |
722 | uint64_t minor:2; | |
723 | uint64_t wait:1; | |
724 | uint64_t qid_base:7; | |
725 | uint64_t qid_off:3; | |
726 | uint64_t qcb_ridx:5; | |
727 | uint64_t qos:3; | |
728 | uint64_t active:1; | |
729 | uint64_t chk_mode:1; | |
730 | uint64_t reserved_27_27:1; | |
731 | uint64_t cbuf_fre:1; | |
732 | uint64_t xfer_dwr:1; | |
733 | uint64_t xfer_wor:1; | |
734 | uint64_t uid:1; | |
735 | uint64_t cmnd_siz:16; | |
736 | uint64_t dwri_cnt:13; | |
737 | uint64_t dwri_len:1; | |
738 | uint64_t dwri_sop:1; | |
739 | uint64_t dwri_mod:1; | |
740 | #endif | |
80ff0fd3 DD |
741 | } cn30xx; |
742 | struct cvmx_pko_mem_debug5_cn30xx cn31xx; | |
743 | struct cvmx_pko_mem_debug5_cn30xx cn38xx; | |
744 | struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; | |
745 | struct cvmx_pko_mem_debug5_cn50xx { | |
c5aa59e8 | 746 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
747 | uint64_t curr_ptr:29; |
748 | uint64_t curr_siz:16; | |
749 | uint64_t curr_off:16; | |
750 | uint64_t cmnd_segs:3; | |
c5aa59e8 DD |
751 | #else |
752 | uint64_t cmnd_segs:3; | |
753 | uint64_t curr_off:16; | |
754 | uint64_t curr_siz:16; | |
755 | uint64_t curr_ptr:29; | |
756 | #endif | |
80ff0fd3 DD |
757 | } cn50xx; |
758 | struct cvmx_pko_mem_debug5_cn52xx { | |
c5aa59e8 | 759 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
760 | uint64_t reserved_54_63:10; |
761 | uint64_t nxt_inflt:6; | |
762 | uint64_t curr_ptr:40; | |
763 | uint64_t curr_siz:8; | |
c5aa59e8 DD |
764 | #else |
765 | uint64_t curr_siz:8; | |
766 | uint64_t curr_ptr:40; | |
767 | uint64_t nxt_inflt:6; | |
768 | uint64_t reserved_54_63:10; | |
769 | #endif | |
80ff0fd3 DD |
770 | } cn52xx; |
771 | struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; | |
772 | struct cvmx_pko_mem_debug5_cn52xx cn56xx; | |
773 | struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; | |
774 | struct cvmx_pko_mem_debug5_cn50xx cn58xx; | |
775 | struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; | |
c5aa59e8 DD |
776 | struct cvmx_pko_mem_debug5_cn61xx { |
777 | #ifdef __BIG_ENDIAN_BITFIELD | |
778 | uint64_t reserved_56_63:8; | |
779 | uint64_t ptp:1; | |
780 | uint64_t major_3:1; | |
781 | uint64_t nxt_inflt:6; | |
782 | uint64_t curr_ptr:40; | |
783 | uint64_t curr_siz:8; | |
784 | #else | |
785 | uint64_t curr_siz:8; | |
786 | uint64_t curr_ptr:40; | |
787 | uint64_t nxt_inflt:6; | |
788 | uint64_t major_3:1; | |
789 | uint64_t ptp:1; | |
790 | uint64_t reserved_56_63:8; | |
791 | #endif | |
792 | } cn61xx; | |
793 | struct cvmx_pko_mem_debug5_cn61xx cn63xx; | |
794 | struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; | |
795 | struct cvmx_pko_mem_debug5_cn61xx cn66xx; | |
796 | struct cvmx_pko_mem_debug5_cn68xx { | |
797 | #ifdef __BIG_ENDIAN_BITFIELD | |
798 | uint64_t reserved_57_63:7; | |
799 | uint64_t uid_2:1; | |
800 | uint64_t ptp:1; | |
801 | uint64_t major_3:1; | |
802 | uint64_t nxt_inflt:6; | |
803 | uint64_t curr_ptr:40; | |
804 | uint64_t curr_siz:8; | |
805 | #else | |
806 | uint64_t curr_siz:8; | |
807 | uint64_t curr_ptr:40; | |
808 | uint64_t nxt_inflt:6; | |
809 | uint64_t major_3:1; | |
810 | uint64_t ptp:1; | |
811 | uint64_t uid_2:1; | |
812 | uint64_t reserved_57_63:7; | |
813 | #endif | |
814 | } cn68xx; | |
815 | struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; | |
816 | struct cvmx_pko_mem_debug5_cn61xx cnf71xx; | |
80ff0fd3 DD |
817 | }; |
818 | ||
819 | union cvmx_pko_mem_debug6 { | |
820 | uint64_t u64; | |
821 | struct cvmx_pko_mem_debug6_s { | |
c5aa59e8 | 822 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
823 | uint64_t reserved_37_63:27; |
824 | uint64_t qid_offres:4; | |
825 | uint64_t qid_offths:4; | |
826 | uint64_t preempter:1; | |
827 | uint64_t preemptee:1; | |
828 | uint64_t preempted:1; | |
829 | uint64_t active:1; | |
830 | uint64_t statc:1; | |
831 | uint64_t qos:3; | |
832 | uint64_t qcb_ridx:5; | |
833 | uint64_t qid_offmax:4; | |
834 | uint64_t reserved_0_11:12; | |
c5aa59e8 DD |
835 | #else |
836 | uint64_t reserved_0_11:12; | |
837 | uint64_t qid_offmax:4; | |
838 | uint64_t qcb_ridx:5; | |
839 | uint64_t qos:3; | |
840 | uint64_t statc:1; | |
841 | uint64_t active:1; | |
842 | uint64_t preempted:1; | |
843 | uint64_t preemptee:1; | |
844 | uint64_t preempter:1; | |
845 | uint64_t qid_offths:4; | |
846 | uint64_t qid_offres:4; | |
847 | uint64_t reserved_37_63:27; | |
848 | #endif | |
80ff0fd3 DD |
849 | } s; |
850 | struct cvmx_pko_mem_debug6_cn30xx { | |
c5aa59e8 | 851 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
852 | uint64_t reserved_11_63:53; |
853 | uint64_t qid_offm:3; | |
854 | uint64_t static_p:1; | |
855 | uint64_t work_min:3; | |
856 | uint64_t dwri_chk:1; | |
857 | uint64_t dwri_uid:1; | |
858 | uint64_t dwri_mod:2; | |
c5aa59e8 DD |
859 | #else |
860 | uint64_t dwri_mod:2; | |
861 | uint64_t dwri_uid:1; | |
862 | uint64_t dwri_chk:1; | |
863 | uint64_t work_min:3; | |
864 | uint64_t static_p:1; | |
865 | uint64_t qid_offm:3; | |
866 | uint64_t reserved_11_63:53; | |
867 | #endif | |
80ff0fd3 DD |
868 | } cn30xx; |
869 | struct cvmx_pko_mem_debug6_cn30xx cn31xx; | |
870 | struct cvmx_pko_mem_debug6_cn30xx cn38xx; | |
871 | struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; | |
872 | struct cvmx_pko_mem_debug6_cn50xx { | |
c5aa59e8 | 873 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
874 | uint64_t reserved_11_63:53; |
875 | uint64_t curr_ptr:11; | |
c5aa59e8 DD |
876 | #else |
877 | uint64_t curr_ptr:11; | |
878 | uint64_t reserved_11_63:53; | |
879 | #endif | |
80ff0fd3 DD |
880 | } cn50xx; |
881 | struct cvmx_pko_mem_debug6_cn52xx { | |
c5aa59e8 | 882 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
883 | uint64_t reserved_37_63:27; |
884 | uint64_t qid_offres:4; | |
885 | uint64_t qid_offths:4; | |
886 | uint64_t preempter:1; | |
887 | uint64_t preemptee:1; | |
888 | uint64_t preempted:1; | |
889 | uint64_t active:1; | |
890 | uint64_t statc:1; | |
891 | uint64_t qos:3; | |
892 | uint64_t qcb_ridx:5; | |
893 | uint64_t qid_offmax:4; | |
894 | uint64_t qid_off:4; | |
895 | uint64_t qid_base:8; | |
c5aa59e8 DD |
896 | #else |
897 | uint64_t qid_base:8; | |
898 | uint64_t qid_off:4; | |
899 | uint64_t qid_offmax:4; | |
900 | uint64_t qcb_ridx:5; | |
901 | uint64_t qos:3; | |
902 | uint64_t statc:1; | |
903 | uint64_t active:1; | |
904 | uint64_t preempted:1; | |
905 | uint64_t preemptee:1; | |
906 | uint64_t preempter:1; | |
907 | uint64_t qid_offths:4; | |
908 | uint64_t qid_offres:4; | |
909 | uint64_t reserved_37_63:27; | |
910 | #endif | |
80ff0fd3 DD |
911 | } cn52xx; |
912 | struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; | |
913 | struct cvmx_pko_mem_debug6_cn52xx cn56xx; | |
914 | struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; | |
915 | struct cvmx_pko_mem_debug6_cn50xx cn58xx; | |
916 | struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; | |
c5aa59e8 DD |
917 | struct cvmx_pko_mem_debug6_cn52xx cn61xx; |
918 | struct cvmx_pko_mem_debug6_cn52xx cn63xx; | |
919 | struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; | |
920 | struct cvmx_pko_mem_debug6_cn52xx cn66xx; | |
921 | struct cvmx_pko_mem_debug6_cn52xx cn68xx; | |
922 | struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; | |
923 | struct cvmx_pko_mem_debug6_cn52xx cnf71xx; | |
80ff0fd3 DD |
924 | }; |
925 | ||
926 | union cvmx_pko_mem_debug7 { | |
927 | uint64_t u64; | |
928 | struct cvmx_pko_mem_debug7_s { | |
c5aa59e8 DD |
929 | #ifdef __BIG_ENDIAN_BITFIELD |
930 | uint64_t reserved_0_63:64; | |
931 | #else | |
932 | uint64_t reserved_0_63:64; | |
933 | #endif | |
80ff0fd3 DD |
934 | } s; |
935 | struct cvmx_pko_mem_debug7_cn30xx { | |
c5aa59e8 | 936 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
937 | uint64_t reserved_58_63:6; |
938 | uint64_t dwb:9; | |
939 | uint64_t start:33; | |
940 | uint64_t size:16; | |
c5aa59e8 DD |
941 | #else |
942 | uint64_t size:16; | |
943 | uint64_t start:33; | |
944 | uint64_t dwb:9; | |
945 | uint64_t reserved_58_63:6; | |
946 | #endif | |
80ff0fd3 DD |
947 | } cn30xx; |
948 | struct cvmx_pko_mem_debug7_cn30xx cn31xx; | |
949 | struct cvmx_pko_mem_debug7_cn30xx cn38xx; | |
950 | struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; | |
951 | struct cvmx_pko_mem_debug7_cn50xx { | |
c5aa59e8 | 952 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
953 | uint64_t qos:5; |
954 | uint64_t tail:1; | |
955 | uint64_t buf_siz:13; | |
956 | uint64_t buf_ptr:33; | |
957 | uint64_t qcb_widx:6; | |
958 | uint64_t qcb_ridx:6; | |
c5aa59e8 DD |
959 | #else |
960 | uint64_t qcb_ridx:6; | |
961 | uint64_t qcb_widx:6; | |
962 | uint64_t buf_ptr:33; | |
963 | uint64_t buf_siz:13; | |
964 | uint64_t tail:1; | |
965 | uint64_t qos:5; | |
966 | #endif | |
80ff0fd3 DD |
967 | } cn50xx; |
968 | struct cvmx_pko_mem_debug7_cn50xx cn52xx; | |
969 | struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; | |
970 | struct cvmx_pko_mem_debug7_cn50xx cn56xx; | |
971 | struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; | |
972 | struct cvmx_pko_mem_debug7_cn50xx cn58xx; | |
973 | struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; | |
c5aa59e8 DD |
974 | struct cvmx_pko_mem_debug7_cn50xx cn61xx; |
975 | struct cvmx_pko_mem_debug7_cn50xx cn63xx; | |
976 | struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; | |
977 | struct cvmx_pko_mem_debug7_cn50xx cn66xx; | |
978 | struct cvmx_pko_mem_debug7_cn68xx { | |
979 | #ifdef __BIG_ENDIAN_BITFIELD | |
980 | uint64_t qos:3; | |
981 | uint64_t tail:1; | |
982 | uint64_t buf_siz:13; | |
983 | uint64_t buf_ptr:33; | |
984 | uint64_t qcb_widx:7; | |
985 | uint64_t qcb_ridx:7; | |
986 | #else | |
987 | uint64_t qcb_ridx:7; | |
988 | uint64_t qcb_widx:7; | |
989 | uint64_t buf_ptr:33; | |
990 | uint64_t buf_siz:13; | |
991 | uint64_t tail:1; | |
992 | uint64_t qos:3; | |
993 | #endif | |
994 | } cn68xx; | |
995 | struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; | |
996 | struct cvmx_pko_mem_debug7_cn50xx cnf71xx; | |
80ff0fd3 DD |
997 | }; |
998 | ||
999 | union cvmx_pko_mem_debug8 { | |
1000 | uint64_t u64; | |
1001 | struct cvmx_pko_mem_debug8_s { | |
c5aa59e8 | 1002 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1003 | uint64_t reserved_59_63:5; |
1004 | uint64_t tail:1; | |
1005 | uint64_t buf_siz:13; | |
1006 | uint64_t reserved_0_44:45; | |
c5aa59e8 DD |
1007 | #else |
1008 | uint64_t reserved_0_44:45; | |
1009 | uint64_t buf_siz:13; | |
1010 | uint64_t tail:1; | |
1011 | uint64_t reserved_59_63:5; | |
1012 | #endif | |
80ff0fd3 DD |
1013 | } s; |
1014 | struct cvmx_pko_mem_debug8_cn30xx { | |
c5aa59e8 | 1015 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1016 | uint64_t qos:5; |
1017 | uint64_t tail:1; | |
1018 | uint64_t buf_siz:13; | |
1019 | uint64_t buf_ptr:33; | |
1020 | uint64_t qcb_widx:6; | |
1021 | uint64_t qcb_ridx:6; | |
c5aa59e8 DD |
1022 | #else |
1023 | uint64_t qcb_ridx:6; | |
1024 | uint64_t qcb_widx:6; | |
1025 | uint64_t buf_ptr:33; | |
1026 | uint64_t buf_siz:13; | |
1027 | uint64_t tail:1; | |
1028 | uint64_t qos:5; | |
1029 | #endif | |
1030 | } cn30xx; | |
1031 | struct cvmx_pko_mem_debug8_cn30xx cn31xx; | |
1032 | struct cvmx_pko_mem_debug8_cn30xx cn38xx; | |
80ff0fd3 DD |
1033 | struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; |
1034 | struct cvmx_pko_mem_debug8_cn50xx { | |
c5aa59e8 | 1035 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1036 | uint64_t reserved_28_63:36; |
1037 | uint64_t doorbell:20; | |
1038 | uint64_t reserved_6_7:2; | |
1039 | uint64_t static_p:1; | |
1040 | uint64_t s_tail:1; | |
1041 | uint64_t static_q:1; | |
1042 | uint64_t qos:3; | |
c5aa59e8 DD |
1043 | #else |
1044 | uint64_t qos:3; | |
1045 | uint64_t static_q:1; | |
1046 | uint64_t s_tail:1; | |
1047 | uint64_t static_p:1; | |
1048 | uint64_t reserved_6_7:2; | |
1049 | uint64_t doorbell:20; | |
1050 | uint64_t reserved_28_63:36; | |
1051 | #endif | |
80ff0fd3 DD |
1052 | } cn50xx; |
1053 | struct cvmx_pko_mem_debug8_cn52xx { | |
c5aa59e8 | 1054 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1055 | uint64_t reserved_29_63:35; |
1056 | uint64_t preempter:1; | |
1057 | uint64_t doorbell:20; | |
1058 | uint64_t reserved_7_7:1; | |
1059 | uint64_t preemptee:1; | |
1060 | uint64_t static_p:1; | |
1061 | uint64_t s_tail:1; | |
1062 | uint64_t static_q:1; | |
1063 | uint64_t qos:3; | |
c5aa59e8 DD |
1064 | #else |
1065 | uint64_t qos:3; | |
1066 | uint64_t static_q:1; | |
1067 | uint64_t s_tail:1; | |
1068 | uint64_t static_p:1; | |
1069 | uint64_t preemptee:1; | |
1070 | uint64_t reserved_7_7:1; | |
1071 | uint64_t doorbell:20; | |
1072 | uint64_t preempter:1; | |
1073 | uint64_t reserved_29_63:35; | |
1074 | #endif | |
80ff0fd3 DD |
1075 | } cn52xx; |
1076 | struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; | |
1077 | struct cvmx_pko_mem_debug8_cn52xx cn56xx; | |
1078 | struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; | |
1079 | struct cvmx_pko_mem_debug8_cn50xx cn58xx; | |
1080 | struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; | |
c5aa59e8 DD |
1081 | struct cvmx_pko_mem_debug8_cn61xx { |
1082 | #ifdef __BIG_ENDIAN_BITFIELD | |
1083 | uint64_t reserved_42_63:22; | |
1084 | uint64_t qid_qqos:8; | |
1085 | uint64_t reserved_33_33:1; | |
1086 | uint64_t qid_idx:4; | |
1087 | uint64_t preempter:1; | |
1088 | uint64_t doorbell:20; | |
1089 | uint64_t reserved_7_7:1; | |
1090 | uint64_t preemptee:1; | |
1091 | uint64_t static_p:1; | |
1092 | uint64_t s_tail:1; | |
1093 | uint64_t static_q:1; | |
1094 | uint64_t qos:3; | |
1095 | #else | |
1096 | uint64_t qos:3; | |
1097 | uint64_t static_q:1; | |
1098 | uint64_t s_tail:1; | |
1099 | uint64_t static_p:1; | |
1100 | uint64_t preemptee:1; | |
1101 | uint64_t reserved_7_7:1; | |
1102 | uint64_t doorbell:20; | |
1103 | uint64_t preempter:1; | |
1104 | uint64_t qid_idx:4; | |
1105 | uint64_t reserved_33_33:1; | |
1106 | uint64_t qid_qqos:8; | |
1107 | uint64_t reserved_42_63:22; | |
1108 | #endif | |
1109 | } cn61xx; | |
1110 | struct cvmx_pko_mem_debug8_cn52xx cn63xx; | |
1111 | struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; | |
1112 | struct cvmx_pko_mem_debug8_cn61xx cn66xx; | |
1113 | struct cvmx_pko_mem_debug8_cn68xx { | |
1114 | #ifdef __BIG_ENDIAN_BITFIELD | |
1115 | uint64_t reserved_37_63:27; | |
1116 | uint64_t preempter:1; | |
1117 | uint64_t doorbell:20; | |
1118 | uint64_t reserved_9_15:7; | |
1119 | uint64_t preemptee:1; | |
1120 | uint64_t static_p:1; | |
1121 | uint64_t s_tail:1; | |
1122 | uint64_t static_q:1; | |
1123 | uint64_t qos:5; | |
1124 | #else | |
1125 | uint64_t qos:5; | |
1126 | uint64_t static_q:1; | |
1127 | uint64_t s_tail:1; | |
1128 | uint64_t static_p:1; | |
1129 | uint64_t preemptee:1; | |
1130 | uint64_t reserved_9_15:7; | |
1131 | uint64_t doorbell:20; | |
1132 | uint64_t preempter:1; | |
1133 | uint64_t reserved_37_63:27; | |
1134 | #endif | |
1135 | } cn68xx; | |
1136 | struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; | |
1137 | struct cvmx_pko_mem_debug8_cn61xx cnf71xx; | |
80ff0fd3 DD |
1138 | }; |
1139 | ||
1140 | union cvmx_pko_mem_debug9 { | |
1141 | uint64_t u64; | |
1142 | struct cvmx_pko_mem_debug9_s { | |
c5aa59e8 | 1143 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1144 | uint64_t reserved_49_63:15; |
1145 | uint64_t ptrs0:17; | |
1146 | uint64_t reserved_0_31:32; | |
c5aa59e8 DD |
1147 | #else |
1148 | uint64_t reserved_0_31:32; | |
1149 | uint64_t ptrs0:17; | |
1150 | uint64_t reserved_49_63:15; | |
1151 | #endif | |
80ff0fd3 DD |
1152 | } s; |
1153 | struct cvmx_pko_mem_debug9_cn30xx { | |
c5aa59e8 | 1154 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1155 | uint64_t reserved_28_63:36; |
1156 | uint64_t doorbell:20; | |
1157 | uint64_t reserved_5_7:3; | |
1158 | uint64_t s_tail:1; | |
1159 | uint64_t static_q:1; | |
1160 | uint64_t qos:3; | |
c5aa59e8 DD |
1161 | #else |
1162 | uint64_t qos:3; | |
1163 | uint64_t static_q:1; | |
1164 | uint64_t s_tail:1; | |
1165 | uint64_t reserved_5_7:3; | |
1166 | uint64_t doorbell:20; | |
1167 | uint64_t reserved_28_63:36; | |
1168 | #endif | |
80ff0fd3 DD |
1169 | } cn30xx; |
1170 | struct cvmx_pko_mem_debug9_cn30xx cn31xx; | |
1171 | struct cvmx_pko_mem_debug9_cn38xx { | |
c5aa59e8 | 1172 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1173 | uint64_t reserved_28_63:36; |
1174 | uint64_t doorbell:20; | |
1175 | uint64_t reserved_6_7:2; | |
1176 | uint64_t static_p:1; | |
1177 | uint64_t s_tail:1; | |
1178 | uint64_t static_q:1; | |
1179 | uint64_t qos:3; | |
c5aa59e8 DD |
1180 | #else |
1181 | uint64_t qos:3; | |
1182 | uint64_t static_q:1; | |
1183 | uint64_t s_tail:1; | |
1184 | uint64_t static_p:1; | |
1185 | uint64_t reserved_6_7:2; | |
1186 | uint64_t doorbell:20; | |
1187 | uint64_t reserved_28_63:36; | |
1188 | #endif | |
80ff0fd3 DD |
1189 | } cn38xx; |
1190 | struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; | |
1191 | struct cvmx_pko_mem_debug9_cn50xx { | |
c5aa59e8 | 1192 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1193 | uint64_t reserved_49_63:15; |
1194 | uint64_t ptrs0:17; | |
1195 | uint64_t reserved_17_31:15; | |
1196 | uint64_t ptrs3:17; | |
c5aa59e8 DD |
1197 | #else |
1198 | uint64_t ptrs3:17; | |
1199 | uint64_t reserved_17_31:15; | |
1200 | uint64_t ptrs0:17; | |
1201 | uint64_t reserved_49_63:15; | |
1202 | #endif | |
80ff0fd3 DD |
1203 | } cn50xx; |
1204 | struct cvmx_pko_mem_debug9_cn50xx cn52xx; | |
1205 | struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; | |
1206 | struct cvmx_pko_mem_debug9_cn50xx cn56xx; | |
1207 | struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; | |
1208 | struct cvmx_pko_mem_debug9_cn50xx cn58xx; | |
1209 | struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; | |
c5aa59e8 DD |
1210 | struct cvmx_pko_mem_debug9_cn50xx cn61xx; |
1211 | struct cvmx_pko_mem_debug9_cn50xx cn63xx; | |
1212 | struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; | |
1213 | struct cvmx_pko_mem_debug9_cn50xx cn66xx; | |
1214 | struct cvmx_pko_mem_debug9_cn50xx cn68xx; | |
1215 | struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; | |
1216 | struct cvmx_pko_mem_debug9_cn50xx cnf71xx; | |
1217 | }; | |
1218 | ||
1219 | union cvmx_pko_mem_iport_ptrs { | |
1220 | uint64_t u64; | |
1221 | struct cvmx_pko_mem_iport_ptrs_s { | |
1222 | #ifdef __BIG_ENDIAN_BITFIELD | |
1223 | uint64_t reserved_63_63:1; | |
1224 | uint64_t crc:1; | |
1225 | uint64_t static_p:1; | |
1226 | uint64_t qos_mask:8; | |
1227 | uint64_t min_pkt:3; | |
1228 | uint64_t reserved_31_49:19; | |
1229 | uint64_t pipe:7; | |
1230 | uint64_t reserved_21_23:3; | |
1231 | uint64_t intr:5; | |
1232 | uint64_t reserved_13_15:3; | |
1233 | uint64_t eid:5; | |
1234 | uint64_t reserved_7_7:1; | |
1235 | uint64_t ipid:7; | |
1236 | #else | |
1237 | uint64_t ipid:7; | |
1238 | uint64_t reserved_7_7:1; | |
1239 | uint64_t eid:5; | |
1240 | uint64_t reserved_13_15:3; | |
1241 | uint64_t intr:5; | |
1242 | uint64_t reserved_21_23:3; | |
1243 | uint64_t pipe:7; | |
1244 | uint64_t reserved_31_49:19; | |
1245 | uint64_t min_pkt:3; | |
1246 | uint64_t qos_mask:8; | |
1247 | uint64_t static_p:1; | |
1248 | uint64_t crc:1; | |
1249 | uint64_t reserved_63_63:1; | |
1250 | #endif | |
1251 | } s; | |
1252 | struct cvmx_pko_mem_iport_ptrs_s cn68xx; | |
1253 | struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; | |
1254 | }; | |
1255 | ||
1256 | union cvmx_pko_mem_iport_qos { | |
1257 | uint64_t u64; | |
1258 | struct cvmx_pko_mem_iport_qos_s { | |
1259 | #ifdef __BIG_ENDIAN_BITFIELD | |
1260 | uint64_t reserved_61_63:3; | |
1261 | uint64_t qos_mask:8; | |
1262 | uint64_t reserved_13_52:40; | |
1263 | uint64_t eid:5; | |
1264 | uint64_t reserved_7_7:1; | |
1265 | uint64_t ipid:7; | |
1266 | #else | |
1267 | uint64_t ipid:7; | |
1268 | uint64_t reserved_7_7:1; | |
1269 | uint64_t eid:5; | |
1270 | uint64_t reserved_13_52:40; | |
1271 | uint64_t qos_mask:8; | |
1272 | uint64_t reserved_61_63:3; | |
1273 | #endif | |
1274 | } s; | |
1275 | struct cvmx_pko_mem_iport_qos_s cn68xx; | |
1276 | struct cvmx_pko_mem_iport_qos_s cn68xxp1; | |
1277 | }; | |
1278 | ||
1279 | union cvmx_pko_mem_iqueue_ptrs { | |
1280 | uint64_t u64; | |
1281 | struct cvmx_pko_mem_iqueue_ptrs_s { | |
1282 | #ifdef __BIG_ENDIAN_BITFIELD | |
1283 | uint64_t s_tail:1; | |
1284 | uint64_t static_p:1; | |
1285 | uint64_t static_q:1; | |
1286 | uint64_t qos_mask:8; | |
1287 | uint64_t buf_ptr:31; | |
1288 | uint64_t tail:1; | |
1289 | uint64_t index:5; | |
1290 | uint64_t reserved_15_15:1; | |
1291 | uint64_t ipid:7; | |
1292 | uint64_t qid:8; | |
1293 | #else | |
1294 | uint64_t qid:8; | |
1295 | uint64_t ipid:7; | |
1296 | uint64_t reserved_15_15:1; | |
1297 | uint64_t index:5; | |
1298 | uint64_t tail:1; | |
1299 | uint64_t buf_ptr:31; | |
1300 | uint64_t qos_mask:8; | |
1301 | uint64_t static_q:1; | |
1302 | uint64_t static_p:1; | |
1303 | uint64_t s_tail:1; | |
1304 | #endif | |
1305 | } s; | |
1306 | struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; | |
1307 | struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; | |
1308 | }; | |
1309 | ||
1310 | union cvmx_pko_mem_iqueue_qos { | |
1311 | uint64_t u64; | |
1312 | struct cvmx_pko_mem_iqueue_qos_s { | |
1313 | #ifdef __BIG_ENDIAN_BITFIELD | |
1314 | uint64_t reserved_61_63:3; | |
1315 | uint64_t qos_mask:8; | |
1316 | uint64_t reserved_15_52:38; | |
1317 | uint64_t ipid:7; | |
1318 | uint64_t qid:8; | |
1319 | #else | |
1320 | uint64_t qid:8; | |
1321 | uint64_t ipid:7; | |
1322 | uint64_t reserved_15_52:38; | |
1323 | uint64_t qos_mask:8; | |
1324 | uint64_t reserved_61_63:3; | |
1325 | #endif | |
1326 | } s; | |
1327 | struct cvmx_pko_mem_iqueue_qos_s cn68xx; | |
1328 | struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; | |
80ff0fd3 DD |
1329 | }; |
1330 | ||
1331 | union cvmx_pko_mem_port_ptrs { | |
1332 | uint64_t u64; | |
1333 | struct cvmx_pko_mem_port_ptrs_s { | |
c5aa59e8 | 1334 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1335 | uint64_t reserved_62_63:2; |
1336 | uint64_t static_p:1; | |
1337 | uint64_t qos_mask:8; | |
1338 | uint64_t reserved_16_52:37; | |
1339 | uint64_t bp_port:6; | |
1340 | uint64_t eid:4; | |
1341 | uint64_t pid:6; | |
c5aa59e8 DD |
1342 | #else |
1343 | uint64_t pid:6; | |
1344 | uint64_t eid:4; | |
1345 | uint64_t bp_port:6; | |
1346 | uint64_t reserved_16_52:37; | |
1347 | uint64_t qos_mask:8; | |
1348 | uint64_t static_p:1; | |
1349 | uint64_t reserved_62_63:2; | |
1350 | #endif | |
80ff0fd3 DD |
1351 | } s; |
1352 | struct cvmx_pko_mem_port_ptrs_s cn52xx; | |
1353 | struct cvmx_pko_mem_port_ptrs_s cn52xxp1; | |
1354 | struct cvmx_pko_mem_port_ptrs_s cn56xx; | |
1355 | struct cvmx_pko_mem_port_ptrs_s cn56xxp1; | |
c5aa59e8 DD |
1356 | struct cvmx_pko_mem_port_ptrs_s cn61xx; |
1357 | struct cvmx_pko_mem_port_ptrs_s cn63xx; | |
1358 | struct cvmx_pko_mem_port_ptrs_s cn63xxp1; | |
1359 | struct cvmx_pko_mem_port_ptrs_s cn66xx; | |
1360 | struct cvmx_pko_mem_port_ptrs_s cnf71xx; | |
80ff0fd3 DD |
1361 | }; |
1362 | ||
1363 | union cvmx_pko_mem_port_qos { | |
1364 | uint64_t u64; | |
1365 | struct cvmx_pko_mem_port_qos_s { | |
c5aa59e8 | 1366 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1367 | uint64_t reserved_61_63:3; |
1368 | uint64_t qos_mask:8; | |
1369 | uint64_t reserved_10_52:43; | |
1370 | uint64_t eid:4; | |
1371 | uint64_t pid:6; | |
c5aa59e8 DD |
1372 | #else |
1373 | uint64_t pid:6; | |
1374 | uint64_t eid:4; | |
1375 | uint64_t reserved_10_52:43; | |
1376 | uint64_t qos_mask:8; | |
1377 | uint64_t reserved_61_63:3; | |
1378 | #endif | |
80ff0fd3 DD |
1379 | } s; |
1380 | struct cvmx_pko_mem_port_qos_s cn52xx; | |
1381 | struct cvmx_pko_mem_port_qos_s cn52xxp1; | |
1382 | struct cvmx_pko_mem_port_qos_s cn56xx; | |
1383 | struct cvmx_pko_mem_port_qos_s cn56xxp1; | |
c5aa59e8 DD |
1384 | struct cvmx_pko_mem_port_qos_s cn61xx; |
1385 | struct cvmx_pko_mem_port_qos_s cn63xx; | |
1386 | struct cvmx_pko_mem_port_qos_s cn63xxp1; | |
1387 | struct cvmx_pko_mem_port_qos_s cn66xx; | |
1388 | struct cvmx_pko_mem_port_qos_s cnf71xx; | |
80ff0fd3 DD |
1389 | }; |
1390 | ||
1391 | union cvmx_pko_mem_port_rate0 { | |
1392 | uint64_t u64; | |
1393 | struct cvmx_pko_mem_port_rate0_s { | |
c5aa59e8 DD |
1394 | #ifdef __BIG_ENDIAN_BITFIELD |
1395 | uint64_t reserved_51_63:13; | |
1396 | uint64_t rate_word:19; | |
1397 | uint64_t rate_pkt:24; | |
1398 | uint64_t reserved_7_7:1; | |
1399 | uint64_t pid:7; | |
1400 | #else | |
1401 | uint64_t pid:7; | |
1402 | uint64_t reserved_7_7:1; | |
1403 | uint64_t rate_pkt:24; | |
1404 | uint64_t rate_word:19; | |
1405 | uint64_t reserved_51_63:13; | |
1406 | #endif | |
1407 | } s; | |
1408 | struct cvmx_pko_mem_port_rate0_cn52xx { | |
1409 | #ifdef __BIG_ENDIAN_BITFIELD | |
80ff0fd3 DD |
1410 | uint64_t reserved_51_63:13; |
1411 | uint64_t rate_word:19; | |
1412 | uint64_t rate_pkt:24; | |
1413 | uint64_t reserved_6_7:2; | |
1414 | uint64_t pid:6; | |
c5aa59e8 DD |
1415 | #else |
1416 | uint64_t pid:6; | |
1417 | uint64_t reserved_6_7:2; | |
1418 | uint64_t rate_pkt:24; | |
1419 | uint64_t rate_word:19; | |
1420 | uint64_t reserved_51_63:13; | |
1421 | #endif | |
1422 | } cn52xx; | |
1423 | struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; | |
1424 | struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; | |
1425 | struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; | |
1426 | struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; | |
1427 | struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; | |
1428 | struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; | |
1429 | struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; | |
1430 | struct cvmx_pko_mem_port_rate0_s cn68xx; | |
1431 | struct cvmx_pko_mem_port_rate0_s cn68xxp1; | |
1432 | struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; | |
80ff0fd3 DD |
1433 | }; |
1434 | ||
1435 | union cvmx_pko_mem_port_rate1 { | |
1436 | uint64_t u64; | |
1437 | struct cvmx_pko_mem_port_rate1_s { | |
c5aa59e8 DD |
1438 | #ifdef __BIG_ENDIAN_BITFIELD |
1439 | uint64_t reserved_32_63:32; | |
1440 | uint64_t rate_lim:24; | |
1441 | uint64_t reserved_7_7:1; | |
1442 | uint64_t pid:7; | |
1443 | #else | |
1444 | uint64_t pid:7; | |
1445 | uint64_t reserved_7_7:1; | |
1446 | uint64_t rate_lim:24; | |
1447 | uint64_t reserved_32_63:32; | |
1448 | #endif | |
1449 | } s; | |
1450 | struct cvmx_pko_mem_port_rate1_cn52xx { | |
1451 | #ifdef __BIG_ENDIAN_BITFIELD | |
80ff0fd3 DD |
1452 | uint64_t reserved_32_63:32; |
1453 | uint64_t rate_lim:24; | |
1454 | uint64_t reserved_6_7:2; | |
1455 | uint64_t pid:6; | |
c5aa59e8 DD |
1456 | #else |
1457 | uint64_t pid:6; | |
1458 | uint64_t reserved_6_7:2; | |
1459 | uint64_t rate_lim:24; | |
1460 | uint64_t reserved_32_63:32; | |
1461 | #endif | |
1462 | } cn52xx; | |
1463 | struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; | |
1464 | struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; | |
1465 | struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; | |
1466 | struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; | |
1467 | struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; | |
1468 | struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; | |
1469 | struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; | |
1470 | struct cvmx_pko_mem_port_rate1_s cn68xx; | |
1471 | struct cvmx_pko_mem_port_rate1_s cn68xxp1; | |
1472 | struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; | |
80ff0fd3 DD |
1473 | }; |
1474 | ||
1475 | union cvmx_pko_mem_queue_ptrs { | |
1476 | uint64_t u64; | |
1477 | struct cvmx_pko_mem_queue_ptrs_s { | |
c5aa59e8 | 1478 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1479 | uint64_t s_tail:1; |
1480 | uint64_t static_p:1; | |
1481 | uint64_t static_q:1; | |
1482 | uint64_t qos_mask:8; | |
1483 | uint64_t buf_ptr:36; | |
1484 | uint64_t tail:1; | |
1485 | uint64_t index:3; | |
1486 | uint64_t port:6; | |
1487 | uint64_t queue:7; | |
c5aa59e8 DD |
1488 | #else |
1489 | uint64_t queue:7; | |
1490 | uint64_t port:6; | |
1491 | uint64_t index:3; | |
1492 | uint64_t tail:1; | |
1493 | uint64_t buf_ptr:36; | |
1494 | uint64_t qos_mask:8; | |
1495 | uint64_t static_q:1; | |
1496 | uint64_t static_p:1; | |
1497 | uint64_t s_tail:1; | |
1498 | #endif | |
80ff0fd3 DD |
1499 | } s; |
1500 | struct cvmx_pko_mem_queue_ptrs_s cn30xx; | |
1501 | struct cvmx_pko_mem_queue_ptrs_s cn31xx; | |
1502 | struct cvmx_pko_mem_queue_ptrs_s cn38xx; | |
1503 | struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; | |
1504 | struct cvmx_pko_mem_queue_ptrs_s cn50xx; | |
1505 | struct cvmx_pko_mem_queue_ptrs_s cn52xx; | |
1506 | struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; | |
1507 | struct cvmx_pko_mem_queue_ptrs_s cn56xx; | |
1508 | struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; | |
1509 | struct cvmx_pko_mem_queue_ptrs_s cn58xx; | |
1510 | struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; | |
c5aa59e8 DD |
1511 | struct cvmx_pko_mem_queue_ptrs_s cn61xx; |
1512 | struct cvmx_pko_mem_queue_ptrs_s cn63xx; | |
1513 | struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; | |
1514 | struct cvmx_pko_mem_queue_ptrs_s cn66xx; | |
1515 | struct cvmx_pko_mem_queue_ptrs_s cnf71xx; | |
80ff0fd3 DD |
1516 | }; |
1517 | ||
1518 | union cvmx_pko_mem_queue_qos { | |
1519 | uint64_t u64; | |
1520 | struct cvmx_pko_mem_queue_qos_s { | |
c5aa59e8 | 1521 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1522 | uint64_t reserved_61_63:3; |
1523 | uint64_t qos_mask:8; | |
1524 | uint64_t reserved_13_52:40; | |
1525 | uint64_t pid:6; | |
1526 | uint64_t qid:7; | |
c5aa59e8 DD |
1527 | #else |
1528 | uint64_t qid:7; | |
1529 | uint64_t pid:6; | |
1530 | uint64_t reserved_13_52:40; | |
1531 | uint64_t qos_mask:8; | |
1532 | uint64_t reserved_61_63:3; | |
1533 | #endif | |
80ff0fd3 DD |
1534 | } s; |
1535 | struct cvmx_pko_mem_queue_qos_s cn30xx; | |
1536 | struct cvmx_pko_mem_queue_qos_s cn31xx; | |
1537 | struct cvmx_pko_mem_queue_qos_s cn38xx; | |
1538 | struct cvmx_pko_mem_queue_qos_s cn38xxp2; | |
1539 | struct cvmx_pko_mem_queue_qos_s cn50xx; | |
1540 | struct cvmx_pko_mem_queue_qos_s cn52xx; | |
1541 | struct cvmx_pko_mem_queue_qos_s cn52xxp1; | |
1542 | struct cvmx_pko_mem_queue_qos_s cn56xx; | |
1543 | struct cvmx_pko_mem_queue_qos_s cn56xxp1; | |
1544 | struct cvmx_pko_mem_queue_qos_s cn58xx; | |
1545 | struct cvmx_pko_mem_queue_qos_s cn58xxp1; | |
c5aa59e8 DD |
1546 | struct cvmx_pko_mem_queue_qos_s cn61xx; |
1547 | struct cvmx_pko_mem_queue_qos_s cn63xx; | |
1548 | struct cvmx_pko_mem_queue_qos_s cn63xxp1; | |
1549 | struct cvmx_pko_mem_queue_qos_s cn66xx; | |
1550 | struct cvmx_pko_mem_queue_qos_s cnf71xx; | |
1551 | }; | |
1552 | ||
1553 | union cvmx_pko_mem_throttle_int { | |
1554 | uint64_t u64; | |
1555 | struct cvmx_pko_mem_throttle_int_s { | |
1556 | #ifdef __BIG_ENDIAN_BITFIELD | |
1557 | uint64_t reserved_47_63:17; | |
1558 | uint64_t word:15; | |
1559 | uint64_t reserved_14_31:18; | |
1560 | uint64_t packet:6; | |
1561 | uint64_t reserved_5_7:3; | |
1562 | uint64_t intr:5; | |
1563 | #else | |
1564 | uint64_t intr:5; | |
1565 | uint64_t reserved_5_7:3; | |
1566 | uint64_t packet:6; | |
1567 | uint64_t reserved_14_31:18; | |
1568 | uint64_t word:15; | |
1569 | uint64_t reserved_47_63:17; | |
1570 | #endif | |
1571 | } s; | |
1572 | struct cvmx_pko_mem_throttle_int_s cn68xx; | |
1573 | struct cvmx_pko_mem_throttle_int_s cn68xxp1; | |
1574 | }; | |
1575 | ||
1576 | union cvmx_pko_mem_throttle_pipe { | |
1577 | uint64_t u64; | |
1578 | struct cvmx_pko_mem_throttle_pipe_s { | |
1579 | #ifdef __BIG_ENDIAN_BITFIELD | |
1580 | uint64_t reserved_47_63:17; | |
1581 | uint64_t word:15; | |
1582 | uint64_t reserved_14_31:18; | |
1583 | uint64_t packet:6; | |
1584 | uint64_t reserved_7_7:1; | |
1585 | uint64_t pipe:7; | |
1586 | #else | |
1587 | uint64_t pipe:7; | |
1588 | uint64_t reserved_7_7:1; | |
1589 | uint64_t packet:6; | |
1590 | uint64_t reserved_14_31:18; | |
1591 | uint64_t word:15; | |
1592 | uint64_t reserved_47_63:17; | |
1593 | #endif | |
1594 | } s; | |
1595 | struct cvmx_pko_mem_throttle_pipe_s cn68xx; | |
1596 | struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; | |
80ff0fd3 DD |
1597 | }; |
1598 | ||
1599 | union cvmx_pko_reg_bist_result { | |
1600 | uint64_t u64; | |
1601 | struct cvmx_pko_reg_bist_result_s { | |
c5aa59e8 DD |
1602 | #ifdef __BIG_ENDIAN_BITFIELD |
1603 | uint64_t reserved_0_63:64; | |
1604 | #else | |
80ff0fd3 | 1605 | uint64_t reserved_0_63:64; |
c5aa59e8 | 1606 | #endif |
80ff0fd3 DD |
1607 | } s; |
1608 | struct cvmx_pko_reg_bist_result_cn30xx { | |
c5aa59e8 | 1609 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1610 | uint64_t reserved_27_63:37; |
1611 | uint64_t psb2:5; | |
1612 | uint64_t count:1; | |
1613 | uint64_t rif:1; | |
1614 | uint64_t wif:1; | |
1615 | uint64_t ncb:1; | |
1616 | uint64_t out:1; | |
1617 | uint64_t crc:1; | |
1618 | uint64_t chk:1; | |
1619 | uint64_t qsb:2; | |
1620 | uint64_t qcb:2; | |
1621 | uint64_t pdb:4; | |
1622 | uint64_t psb:7; | |
c5aa59e8 DD |
1623 | #else |
1624 | uint64_t psb:7; | |
1625 | uint64_t pdb:4; | |
1626 | uint64_t qcb:2; | |
1627 | uint64_t qsb:2; | |
1628 | uint64_t chk:1; | |
1629 | uint64_t crc:1; | |
1630 | uint64_t out:1; | |
1631 | uint64_t ncb:1; | |
1632 | uint64_t wif:1; | |
1633 | uint64_t rif:1; | |
1634 | uint64_t count:1; | |
1635 | uint64_t psb2:5; | |
1636 | uint64_t reserved_27_63:37; | |
1637 | #endif | |
80ff0fd3 DD |
1638 | } cn30xx; |
1639 | struct cvmx_pko_reg_bist_result_cn30xx cn31xx; | |
1640 | struct cvmx_pko_reg_bist_result_cn30xx cn38xx; | |
1641 | struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; | |
1642 | struct cvmx_pko_reg_bist_result_cn50xx { | |
c5aa59e8 | 1643 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1644 | uint64_t reserved_33_63:31; |
1645 | uint64_t csr:1; | |
1646 | uint64_t iob:1; | |
1647 | uint64_t out_crc:1; | |
1648 | uint64_t out_ctl:3; | |
1649 | uint64_t out_sta:1; | |
1650 | uint64_t out_wif:1; | |
1651 | uint64_t prt_chk:3; | |
1652 | uint64_t prt_nxt:1; | |
1653 | uint64_t prt_psb:6; | |
1654 | uint64_t ncb_inb:2; | |
1655 | uint64_t prt_qcb:2; | |
1656 | uint64_t prt_qsb:3; | |
1657 | uint64_t dat_dat:4; | |
1658 | uint64_t dat_ptr:4; | |
c5aa59e8 DD |
1659 | #else |
1660 | uint64_t dat_ptr:4; | |
1661 | uint64_t dat_dat:4; | |
1662 | uint64_t prt_qsb:3; | |
1663 | uint64_t prt_qcb:2; | |
1664 | uint64_t ncb_inb:2; | |
1665 | uint64_t prt_psb:6; | |
1666 | uint64_t prt_nxt:1; | |
1667 | uint64_t prt_chk:3; | |
1668 | uint64_t out_wif:1; | |
1669 | uint64_t out_sta:1; | |
1670 | uint64_t out_ctl:3; | |
1671 | uint64_t out_crc:1; | |
1672 | uint64_t iob:1; | |
1673 | uint64_t csr:1; | |
1674 | uint64_t reserved_33_63:31; | |
1675 | #endif | |
80ff0fd3 DD |
1676 | } cn50xx; |
1677 | struct cvmx_pko_reg_bist_result_cn52xx { | |
c5aa59e8 | 1678 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1679 | uint64_t reserved_35_63:29; |
1680 | uint64_t csr:1; | |
1681 | uint64_t iob:1; | |
1682 | uint64_t out_dat:1; | |
1683 | uint64_t out_ctl:3; | |
1684 | uint64_t out_sta:1; | |
1685 | uint64_t out_wif:1; | |
1686 | uint64_t prt_chk:3; | |
1687 | uint64_t prt_nxt:1; | |
1688 | uint64_t prt_psb:8; | |
1689 | uint64_t ncb_inb:2; | |
1690 | uint64_t prt_qcb:2; | |
1691 | uint64_t prt_qsb:3; | |
1692 | uint64_t prt_ctl:2; | |
1693 | uint64_t dat_dat:2; | |
1694 | uint64_t dat_ptr:4; | |
c5aa59e8 DD |
1695 | #else |
1696 | uint64_t dat_ptr:4; | |
1697 | uint64_t dat_dat:2; | |
1698 | uint64_t prt_ctl:2; | |
1699 | uint64_t prt_qsb:3; | |
1700 | uint64_t prt_qcb:2; | |
1701 | uint64_t ncb_inb:2; | |
1702 | uint64_t prt_psb:8; | |
1703 | uint64_t prt_nxt:1; | |
1704 | uint64_t prt_chk:3; | |
1705 | uint64_t out_wif:1; | |
1706 | uint64_t out_sta:1; | |
1707 | uint64_t out_ctl:3; | |
1708 | uint64_t out_dat:1; | |
1709 | uint64_t iob:1; | |
1710 | uint64_t csr:1; | |
1711 | uint64_t reserved_35_63:29; | |
1712 | #endif | |
1713 | } cn52xx; | |
1714 | struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; | |
1715 | struct cvmx_pko_reg_bist_result_cn52xx cn56xx; | |
1716 | struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; | |
1717 | struct cvmx_pko_reg_bist_result_cn50xx cn58xx; | |
1718 | struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; | |
1719 | struct cvmx_pko_reg_bist_result_cn52xx cn61xx; | |
1720 | struct cvmx_pko_reg_bist_result_cn52xx cn63xx; | |
1721 | struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; | |
1722 | struct cvmx_pko_reg_bist_result_cn52xx cn66xx; | |
1723 | struct cvmx_pko_reg_bist_result_cn68xx { | |
1724 | #ifdef __BIG_ENDIAN_BITFIELD | |
1725 | uint64_t reserved_36_63:28; | |
1726 | uint64_t crc:1; | |
1727 | uint64_t csr:1; | |
1728 | uint64_t iob:1; | |
1729 | uint64_t out_dat:1; | |
1730 | uint64_t reserved_31_31:1; | |
1731 | uint64_t out_ctl:2; | |
1732 | uint64_t out_sta:1; | |
1733 | uint64_t out_wif:1; | |
1734 | uint64_t prt_chk:3; | |
1735 | uint64_t prt_nxt:1; | |
1736 | uint64_t prt_psb7:1; | |
1737 | uint64_t reserved_21_21:1; | |
1738 | uint64_t prt_psb:6; | |
1739 | uint64_t ncb_inb:2; | |
1740 | uint64_t prt_qcb:2; | |
1741 | uint64_t prt_qsb:3; | |
1742 | uint64_t prt_ctl:2; | |
1743 | uint64_t dat_dat:2; | |
1744 | uint64_t dat_ptr:4; | |
1745 | #else | |
1746 | uint64_t dat_ptr:4; | |
1747 | uint64_t dat_dat:2; | |
1748 | uint64_t prt_ctl:2; | |
1749 | uint64_t prt_qsb:3; | |
1750 | uint64_t prt_qcb:2; | |
1751 | uint64_t ncb_inb:2; | |
1752 | uint64_t prt_psb:6; | |
1753 | uint64_t reserved_21_21:1; | |
1754 | uint64_t prt_psb7:1; | |
1755 | uint64_t prt_nxt:1; | |
1756 | uint64_t prt_chk:3; | |
1757 | uint64_t out_wif:1; | |
1758 | uint64_t out_sta:1; | |
1759 | uint64_t out_ctl:2; | |
1760 | uint64_t reserved_31_31:1; | |
1761 | uint64_t out_dat:1; | |
1762 | uint64_t iob:1; | |
1763 | uint64_t csr:1; | |
1764 | uint64_t crc:1; | |
1765 | uint64_t reserved_36_63:28; | |
1766 | #endif | |
1767 | } cn68xx; | |
1768 | struct cvmx_pko_reg_bist_result_cn68xxp1 { | |
1769 | #ifdef __BIG_ENDIAN_BITFIELD | |
1770 | uint64_t reserved_35_63:29; | |
1771 | uint64_t csr:1; | |
1772 | uint64_t iob:1; | |
1773 | uint64_t out_dat:1; | |
1774 | uint64_t reserved_31_31:1; | |
1775 | uint64_t out_ctl:2; | |
1776 | uint64_t out_sta:1; | |
1777 | uint64_t out_wif:1; | |
1778 | uint64_t prt_chk:3; | |
1779 | uint64_t prt_nxt:1; | |
1780 | uint64_t prt_psb7:1; | |
1781 | uint64_t reserved_21_21:1; | |
1782 | uint64_t prt_psb:6; | |
1783 | uint64_t ncb_inb:2; | |
1784 | uint64_t prt_qcb:2; | |
1785 | uint64_t prt_qsb:3; | |
1786 | uint64_t prt_ctl:2; | |
1787 | uint64_t dat_dat:2; | |
1788 | uint64_t dat_ptr:4; | |
1789 | #else | |
1790 | uint64_t dat_ptr:4; | |
1791 | uint64_t dat_dat:2; | |
1792 | uint64_t prt_ctl:2; | |
1793 | uint64_t prt_qsb:3; | |
1794 | uint64_t prt_qcb:2; | |
1795 | uint64_t ncb_inb:2; | |
1796 | uint64_t prt_psb:6; | |
1797 | uint64_t reserved_21_21:1; | |
1798 | uint64_t prt_psb7:1; | |
1799 | uint64_t prt_nxt:1; | |
1800 | uint64_t prt_chk:3; | |
1801 | uint64_t out_wif:1; | |
1802 | uint64_t out_sta:1; | |
1803 | uint64_t out_ctl:2; | |
1804 | uint64_t reserved_31_31:1; | |
1805 | uint64_t out_dat:1; | |
1806 | uint64_t iob:1; | |
1807 | uint64_t csr:1; | |
1808 | uint64_t reserved_35_63:29; | |
1809 | #endif | |
1810 | } cn68xxp1; | |
1811 | struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; | |
1812 | }; | |
1813 | ||
1814 | union cvmx_pko_reg_cmd_buf { | |
1815 | uint64_t u64; | |
1816 | struct cvmx_pko_reg_cmd_buf_s { | |
1817 | #ifdef __BIG_ENDIAN_BITFIELD | |
80ff0fd3 DD |
1818 | uint64_t reserved_23_63:41; |
1819 | uint64_t pool:3; | |
1820 | uint64_t reserved_13_19:7; | |
1821 | uint64_t size:13; | |
c5aa59e8 DD |
1822 | #else |
1823 | uint64_t size:13; | |
1824 | uint64_t reserved_13_19:7; | |
1825 | uint64_t pool:3; | |
1826 | uint64_t reserved_23_63:41; | |
1827 | #endif | |
80ff0fd3 DD |
1828 | } s; |
1829 | struct cvmx_pko_reg_cmd_buf_s cn30xx; | |
1830 | struct cvmx_pko_reg_cmd_buf_s cn31xx; | |
1831 | struct cvmx_pko_reg_cmd_buf_s cn38xx; | |
1832 | struct cvmx_pko_reg_cmd_buf_s cn38xxp2; | |
1833 | struct cvmx_pko_reg_cmd_buf_s cn50xx; | |
1834 | struct cvmx_pko_reg_cmd_buf_s cn52xx; | |
1835 | struct cvmx_pko_reg_cmd_buf_s cn52xxp1; | |
1836 | struct cvmx_pko_reg_cmd_buf_s cn56xx; | |
1837 | struct cvmx_pko_reg_cmd_buf_s cn56xxp1; | |
1838 | struct cvmx_pko_reg_cmd_buf_s cn58xx; | |
1839 | struct cvmx_pko_reg_cmd_buf_s cn58xxp1; | |
c5aa59e8 DD |
1840 | struct cvmx_pko_reg_cmd_buf_s cn61xx; |
1841 | struct cvmx_pko_reg_cmd_buf_s cn63xx; | |
1842 | struct cvmx_pko_reg_cmd_buf_s cn63xxp1; | |
1843 | struct cvmx_pko_reg_cmd_buf_s cn66xx; | |
1844 | struct cvmx_pko_reg_cmd_buf_s cn68xx; | |
1845 | struct cvmx_pko_reg_cmd_buf_s cn68xxp1; | |
1846 | struct cvmx_pko_reg_cmd_buf_s cnf71xx; | |
80ff0fd3 DD |
1847 | }; |
1848 | ||
1849 | union cvmx_pko_reg_crc_ctlx { | |
1850 | uint64_t u64; | |
1851 | struct cvmx_pko_reg_crc_ctlx_s { | |
c5aa59e8 | 1852 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1853 | uint64_t reserved_2_63:62; |
1854 | uint64_t invres:1; | |
1855 | uint64_t refin:1; | |
c5aa59e8 DD |
1856 | #else |
1857 | uint64_t refin:1; | |
1858 | uint64_t invres:1; | |
1859 | uint64_t reserved_2_63:62; | |
1860 | #endif | |
80ff0fd3 DD |
1861 | } s; |
1862 | struct cvmx_pko_reg_crc_ctlx_s cn38xx; | |
1863 | struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; | |
1864 | struct cvmx_pko_reg_crc_ctlx_s cn58xx; | |
1865 | struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; | |
1866 | }; | |
1867 | ||
1868 | union cvmx_pko_reg_crc_enable { | |
1869 | uint64_t u64; | |
1870 | struct cvmx_pko_reg_crc_enable_s { | |
c5aa59e8 | 1871 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1872 | uint64_t reserved_32_63:32; |
1873 | uint64_t enable:32; | |
c5aa59e8 DD |
1874 | #else |
1875 | uint64_t enable:32; | |
1876 | uint64_t reserved_32_63:32; | |
1877 | #endif | |
80ff0fd3 DD |
1878 | } s; |
1879 | struct cvmx_pko_reg_crc_enable_s cn38xx; | |
1880 | struct cvmx_pko_reg_crc_enable_s cn38xxp2; | |
1881 | struct cvmx_pko_reg_crc_enable_s cn58xx; | |
1882 | struct cvmx_pko_reg_crc_enable_s cn58xxp1; | |
1883 | }; | |
1884 | ||
1885 | union cvmx_pko_reg_crc_ivx { | |
1886 | uint64_t u64; | |
1887 | struct cvmx_pko_reg_crc_ivx_s { | |
c5aa59e8 | 1888 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1889 | uint64_t reserved_32_63:32; |
1890 | uint64_t iv:32; | |
c5aa59e8 DD |
1891 | #else |
1892 | uint64_t iv:32; | |
1893 | uint64_t reserved_32_63:32; | |
1894 | #endif | |
80ff0fd3 DD |
1895 | } s; |
1896 | struct cvmx_pko_reg_crc_ivx_s cn38xx; | |
1897 | struct cvmx_pko_reg_crc_ivx_s cn38xxp2; | |
1898 | struct cvmx_pko_reg_crc_ivx_s cn58xx; | |
1899 | struct cvmx_pko_reg_crc_ivx_s cn58xxp1; | |
1900 | }; | |
1901 | ||
1902 | union cvmx_pko_reg_debug0 { | |
1903 | uint64_t u64; | |
1904 | struct cvmx_pko_reg_debug0_s { | |
c5aa59e8 DD |
1905 | #ifdef __BIG_ENDIAN_BITFIELD |
1906 | uint64_t asserts:64; | |
1907 | #else | |
80ff0fd3 | 1908 | uint64_t asserts:64; |
c5aa59e8 | 1909 | #endif |
80ff0fd3 DD |
1910 | } s; |
1911 | struct cvmx_pko_reg_debug0_cn30xx { | |
c5aa59e8 | 1912 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
1913 | uint64_t reserved_17_63:47; |
1914 | uint64_t asserts:17; | |
c5aa59e8 DD |
1915 | #else |
1916 | uint64_t asserts:17; | |
1917 | uint64_t reserved_17_63:47; | |
1918 | #endif | |
80ff0fd3 DD |
1919 | } cn30xx; |
1920 | struct cvmx_pko_reg_debug0_cn30xx cn31xx; | |
1921 | struct cvmx_pko_reg_debug0_cn30xx cn38xx; | |
1922 | struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; | |
1923 | struct cvmx_pko_reg_debug0_s cn50xx; | |
1924 | struct cvmx_pko_reg_debug0_s cn52xx; | |
1925 | struct cvmx_pko_reg_debug0_s cn52xxp1; | |
1926 | struct cvmx_pko_reg_debug0_s cn56xx; | |
1927 | struct cvmx_pko_reg_debug0_s cn56xxp1; | |
1928 | struct cvmx_pko_reg_debug0_s cn58xx; | |
1929 | struct cvmx_pko_reg_debug0_s cn58xxp1; | |
c5aa59e8 DD |
1930 | struct cvmx_pko_reg_debug0_s cn61xx; |
1931 | struct cvmx_pko_reg_debug0_s cn63xx; | |
1932 | struct cvmx_pko_reg_debug0_s cn63xxp1; | |
1933 | struct cvmx_pko_reg_debug0_s cn66xx; | |
1934 | struct cvmx_pko_reg_debug0_s cn68xx; | |
1935 | struct cvmx_pko_reg_debug0_s cn68xxp1; | |
1936 | struct cvmx_pko_reg_debug0_s cnf71xx; | |
80ff0fd3 DD |
1937 | }; |
1938 | ||
1939 | union cvmx_pko_reg_debug1 { | |
1940 | uint64_t u64; | |
1941 | struct cvmx_pko_reg_debug1_s { | |
c5aa59e8 DD |
1942 | #ifdef __BIG_ENDIAN_BITFIELD |
1943 | uint64_t asserts:64; | |
1944 | #else | |
80ff0fd3 | 1945 | uint64_t asserts:64; |
c5aa59e8 | 1946 | #endif |
80ff0fd3 DD |
1947 | } s; |
1948 | struct cvmx_pko_reg_debug1_s cn50xx; | |
1949 | struct cvmx_pko_reg_debug1_s cn52xx; | |
1950 | struct cvmx_pko_reg_debug1_s cn52xxp1; | |
1951 | struct cvmx_pko_reg_debug1_s cn56xx; | |
1952 | struct cvmx_pko_reg_debug1_s cn56xxp1; | |
1953 | struct cvmx_pko_reg_debug1_s cn58xx; | |
1954 | struct cvmx_pko_reg_debug1_s cn58xxp1; | |
c5aa59e8 DD |
1955 | struct cvmx_pko_reg_debug1_s cn61xx; |
1956 | struct cvmx_pko_reg_debug1_s cn63xx; | |
1957 | struct cvmx_pko_reg_debug1_s cn63xxp1; | |
1958 | struct cvmx_pko_reg_debug1_s cn66xx; | |
1959 | struct cvmx_pko_reg_debug1_s cn68xx; | |
1960 | struct cvmx_pko_reg_debug1_s cn68xxp1; | |
1961 | struct cvmx_pko_reg_debug1_s cnf71xx; | |
80ff0fd3 DD |
1962 | }; |
1963 | ||
1964 | union cvmx_pko_reg_debug2 { | |
1965 | uint64_t u64; | |
1966 | struct cvmx_pko_reg_debug2_s { | |
c5aa59e8 | 1967 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 | 1968 | uint64_t asserts:64; |
c5aa59e8 DD |
1969 | #else |
1970 | uint64_t asserts:64; | |
1971 | #endif | |
80ff0fd3 DD |
1972 | } s; |
1973 | struct cvmx_pko_reg_debug2_s cn50xx; | |
1974 | struct cvmx_pko_reg_debug2_s cn52xx; | |
1975 | struct cvmx_pko_reg_debug2_s cn52xxp1; | |
1976 | struct cvmx_pko_reg_debug2_s cn56xx; | |
1977 | struct cvmx_pko_reg_debug2_s cn56xxp1; | |
1978 | struct cvmx_pko_reg_debug2_s cn58xx; | |
1979 | struct cvmx_pko_reg_debug2_s cn58xxp1; | |
c5aa59e8 DD |
1980 | struct cvmx_pko_reg_debug2_s cn61xx; |
1981 | struct cvmx_pko_reg_debug2_s cn63xx; | |
1982 | struct cvmx_pko_reg_debug2_s cn63xxp1; | |
1983 | struct cvmx_pko_reg_debug2_s cn66xx; | |
1984 | struct cvmx_pko_reg_debug2_s cn68xx; | |
1985 | struct cvmx_pko_reg_debug2_s cn68xxp1; | |
1986 | struct cvmx_pko_reg_debug2_s cnf71xx; | |
80ff0fd3 DD |
1987 | }; |
1988 | ||
1989 | union cvmx_pko_reg_debug3 { | |
1990 | uint64_t u64; | |
1991 | struct cvmx_pko_reg_debug3_s { | |
c5aa59e8 DD |
1992 | #ifdef __BIG_ENDIAN_BITFIELD |
1993 | uint64_t asserts:64; | |
1994 | #else | |
80ff0fd3 | 1995 | uint64_t asserts:64; |
c5aa59e8 | 1996 | #endif |
80ff0fd3 DD |
1997 | } s; |
1998 | struct cvmx_pko_reg_debug3_s cn50xx; | |
1999 | struct cvmx_pko_reg_debug3_s cn52xx; | |
2000 | struct cvmx_pko_reg_debug3_s cn52xxp1; | |
2001 | struct cvmx_pko_reg_debug3_s cn56xx; | |
2002 | struct cvmx_pko_reg_debug3_s cn56xxp1; | |
2003 | struct cvmx_pko_reg_debug3_s cn58xx; | |
2004 | struct cvmx_pko_reg_debug3_s cn58xxp1; | |
c5aa59e8 DD |
2005 | struct cvmx_pko_reg_debug3_s cn61xx; |
2006 | struct cvmx_pko_reg_debug3_s cn63xx; | |
2007 | struct cvmx_pko_reg_debug3_s cn63xxp1; | |
2008 | struct cvmx_pko_reg_debug3_s cn66xx; | |
2009 | struct cvmx_pko_reg_debug3_s cn68xx; | |
2010 | struct cvmx_pko_reg_debug3_s cn68xxp1; | |
2011 | struct cvmx_pko_reg_debug3_s cnf71xx; | |
2012 | }; | |
2013 | ||
2014 | union cvmx_pko_reg_debug4 { | |
2015 | uint64_t u64; | |
2016 | struct cvmx_pko_reg_debug4_s { | |
2017 | #ifdef __BIG_ENDIAN_BITFIELD | |
2018 | uint64_t asserts:64; | |
2019 | #else | |
2020 | uint64_t asserts:64; | |
2021 | #endif | |
2022 | } s; | |
2023 | struct cvmx_pko_reg_debug4_s cn68xx; | |
2024 | struct cvmx_pko_reg_debug4_s cn68xxp1; | |
80ff0fd3 DD |
2025 | }; |
2026 | ||
2027 | union cvmx_pko_reg_engine_inflight { | |
2028 | uint64_t u64; | |
2029 | struct cvmx_pko_reg_engine_inflight_s { | |
c5aa59e8 DD |
2030 | #ifdef __BIG_ENDIAN_BITFIELD |
2031 | uint64_t engine15:4; | |
2032 | uint64_t engine14:4; | |
2033 | uint64_t engine13:4; | |
2034 | uint64_t engine12:4; | |
2035 | uint64_t engine11:4; | |
2036 | uint64_t engine10:4; | |
2037 | uint64_t engine9:4; | |
2038 | uint64_t engine8:4; | |
2039 | uint64_t engine7:4; | |
2040 | uint64_t engine6:4; | |
2041 | uint64_t engine5:4; | |
2042 | uint64_t engine4:4; | |
2043 | uint64_t engine3:4; | |
2044 | uint64_t engine2:4; | |
2045 | uint64_t engine1:4; | |
2046 | uint64_t engine0:4; | |
2047 | #else | |
2048 | uint64_t engine0:4; | |
2049 | uint64_t engine1:4; | |
2050 | uint64_t engine2:4; | |
2051 | uint64_t engine3:4; | |
2052 | uint64_t engine4:4; | |
2053 | uint64_t engine5:4; | |
2054 | uint64_t engine6:4; | |
2055 | uint64_t engine7:4; | |
2056 | uint64_t engine8:4; | |
2057 | uint64_t engine9:4; | |
2058 | uint64_t engine10:4; | |
2059 | uint64_t engine11:4; | |
2060 | uint64_t engine12:4; | |
2061 | uint64_t engine13:4; | |
2062 | uint64_t engine14:4; | |
2063 | uint64_t engine15:4; | |
2064 | #endif | |
2065 | } s; | |
2066 | struct cvmx_pko_reg_engine_inflight_cn52xx { | |
2067 | #ifdef __BIG_ENDIAN_BITFIELD | |
80ff0fd3 DD |
2068 | uint64_t reserved_40_63:24; |
2069 | uint64_t engine9:4; | |
2070 | uint64_t engine8:4; | |
2071 | uint64_t engine7:4; | |
2072 | uint64_t engine6:4; | |
2073 | uint64_t engine5:4; | |
2074 | uint64_t engine4:4; | |
2075 | uint64_t engine3:4; | |
2076 | uint64_t engine2:4; | |
2077 | uint64_t engine1:4; | |
2078 | uint64_t engine0:4; | |
c5aa59e8 DD |
2079 | #else |
2080 | uint64_t engine0:4; | |
2081 | uint64_t engine1:4; | |
2082 | uint64_t engine2:4; | |
2083 | uint64_t engine3:4; | |
2084 | uint64_t engine4:4; | |
2085 | uint64_t engine5:4; | |
2086 | uint64_t engine6:4; | |
2087 | uint64_t engine7:4; | |
2088 | uint64_t engine8:4; | |
2089 | uint64_t engine9:4; | |
2090 | uint64_t reserved_40_63:24; | |
2091 | #endif | |
2092 | } cn52xx; | |
2093 | struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; | |
2094 | struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; | |
2095 | struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; | |
2096 | struct cvmx_pko_reg_engine_inflight_cn61xx { | |
2097 | #ifdef __BIG_ENDIAN_BITFIELD | |
2098 | uint64_t reserved_56_63:8; | |
2099 | uint64_t engine13:4; | |
2100 | uint64_t engine12:4; | |
2101 | uint64_t engine11:4; | |
2102 | uint64_t engine10:4; | |
2103 | uint64_t engine9:4; | |
2104 | uint64_t engine8:4; | |
2105 | uint64_t engine7:4; | |
2106 | uint64_t engine6:4; | |
2107 | uint64_t engine5:4; | |
2108 | uint64_t engine4:4; | |
2109 | uint64_t engine3:4; | |
2110 | uint64_t engine2:4; | |
2111 | uint64_t engine1:4; | |
2112 | uint64_t engine0:4; | |
2113 | #else | |
2114 | uint64_t engine0:4; | |
2115 | uint64_t engine1:4; | |
2116 | uint64_t engine2:4; | |
2117 | uint64_t engine3:4; | |
2118 | uint64_t engine4:4; | |
2119 | uint64_t engine5:4; | |
2120 | uint64_t engine6:4; | |
2121 | uint64_t engine7:4; | |
2122 | uint64_t engine8:4; | |
2123 | uint64_t engine9:4; | |
2124 | uint64_t engine10:4; | |
2125 | uint64_t engine11:4; | |
2126 | uint64_t engine12:4; | |
2127 | uint64_t engine13:4; | |
2128 | uint64_t reserved_56_63:8; | |
2129 | #endif | |
2130 | } cn61xx; | |
2131 | struct cvmx_pko_reg_engine_inflight_cn63xx { | |
2132 | #ifdef __BIG_ENDIAN_BITFIELD | |
2133 | uint64_t reserved_48_63:16; | |
2134 | uint64_t engine11:4; | |
2135 | uint64_t engine10:4; | |
2136 | uint64_t engine9:4; | |
2137 | uint64_t engine8:4; | |
2138 | uint64_t engine7:4; | |
2139 | uint64_t engine6:4; | |
2140 | uint64_t engine5:4; | |
2141 | uint64_t engine4:4; | |
2142 | uint64_t engine3:4; | |
2143 | uint64_t engine2:4; | |
2144 | uint64_t engine1:4; | |
2145 | uint64_t engine0:4; | |
2146 | #else | |
2147 | uint64_t engine0:4; | |
2148 | uint64_t engine1:4; | |
2149 | uint64_t engine2:4; | |
2150 | uint64_t engine3:4; | |
2151 | uint64_t engine4:4; | |
2152 | uint64_t engine5:4; | |
2153 | uint64_t engine6:4; | |
2154 | uint64_t engine7:4; | |
2155 | uint64_t engine8:4; | |
2156 | uint64_t engine9:4; | |
2157 | uint64_t engine10:4; | |
2158 | uint64_t engine11:4; | |
2159 | uint64_t reserved_48_63:16; | |
2160 | #endif | |
2161 | } cn63xx; | |
2162 | struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; | |
2163 | struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; | |
2164 | struct cvmx_pko_reg_engine_inflight_s cn68xx; | |
2165 | struct cvmx_pko_reg_engine_inflight_s cn68xxp1; | |
2166 | struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; | |
2167 | }; | |
2168 | ||
2169 | union cvmx_pko_reg_engine_inflight1 { | |
2170 | uint64_t u64; | |
2171 | struct cvmx_pko_reg_engine_inflight1_s { | |
2172 | #ifdef __BIG_ENDIAN_BITFIELD | |
2173 | uint64_t reserved_16_63:48; | |
2174 | uint64_t engine19:4; | |
2175 | uint64_t engine18:4; | |
2176 | uint64_t engine17:4; | |
2177 | uint64_t engine16:4; | |
2178 | #else | |
2179 | uint64_t engine16:4; | |
2180 | uint64_t engine17:4; | |
2181 | uint64_t engine18:4; | |
2182 | uint64_t engine19:4; | |
2183 | uint64_t reserved_16_63:48; | |
2184 | #endif | |
2185 | } s; | |
2186 | struct cvmx_pko_reg_engine_inflight1_s cn68xx; | |
2187 | struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; | |
2188 | }; | |
2189 | ||
2190 | union cvmx_pko_reg_engine_storagex { | |
2191 | uint64_t u64; | |
2192 | struct cvmx_pko_reg_engine_storagex_s { | |
2193 | #ifdef __BIG_ENDIAN_BITFIELD | |
2194 | uint64_t engine15:4; | |
2195 | uint64_t engine14:4; | |
2196 | uint64_t engine13:4; | |
2197 | uint64_t engine12:4; | |
2198 | uint64_t engine11:4; | |
2199 | uint64_t engine10:4; | |
2200 | uint64_t engine9:4; | |
2201 | uint64_t engine8:4; | |
2202 | uint64_t engine7:4; | |
2203 | uint64_t engine6:4; | |
2204 | uint64_t engine5:4; | |
2205 | uint64_t engine4:4; | |
2206 | uint64_t engine3:4; | |
2207 | uint64_t engine2:4; | |
2208 | uint64_t engine1:4; | |
2209 | uint64_t engine0:4; | |
2210 | #else | |
2211 | uint64_t engine0:4; | |
2212 | uint64_t engine1:4; | |
2213 | uint64_t engine2:4; | |
2214 | uint64_t engine3:4; | |
2215 | uint64_t engine4:4; | |
2216 | uint64_t engine5:4; | |
2217 | uint64_t engine6:4; | |
2218 | uint64_t engine7:4; | |
2219 | uint64_t engine8:4; | |
2220 | uint64_t engine9:4; | |
2221 | uint64_t engine10:4; | |
2222 | uint64_t engine11:4; | |
2223 | uint64_t engine12:4; | |
2224 | uint64_t engine13:4; | |
2225 | uint64_t engine14:4; | |
2226 | uint64_t engine15:4; | |
2227 | #endif | |
80ff0fd3 | 2228 | } s; |
c5aa59e8 DD |
2229 | struct cvmx_pko_reg_engine_storagex_s cn68xx; |
2230 | struct cvmx_pko_reg_engine_storagex_s cn68xxp1; | |
80ff0fd3 DD |
2231 | }; |
2232 | ||
2233 | union cvmx_pko_reg_engine_thresh { | |
2234 | uint64_t u64; | |
2235 | struct cvmx_pko_reg_engine_thresh_s { | |
c5aa59e8 DD |
2236 | #ifdef __BIG_ENDIAN_BITFIELD |
2237 | uint64_t reserved_20_63:44; | |
2238 | uint64_t mask:20; | |
2239 | #else | |
2240 | uint64_t mask:20; | |
2241 | uint64_t reserved_20_63:44; | |
2242 | #endif | |
2243 | } s; | |
2244 | struct cvmx_pko_reg_engine_thresh_cn52xx { | |
2245 | #ifdef __BIG_ENDIAN_BITFIELD | |
80ff0fd3 DD |
2246 | uint64_t reserved_10_63:54; |
2247 | uint64_t mask:10; | |
c5aa59e8 DD |
2248 | #else |
2249 | uint64_t mask:10; | |
2250 | uint64_t reserved_10_63:54; | |
2251 | #endif | |
2252 | } cn52xx; | |
2253 | struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; | |
2254 | struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; | |
2255 | struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; | |
2256 | struct cvmx_pko_reg_engine_thresh_cn61xx { | |
2257 | #ifdef __BIG_ENDIAN_BITFIELD | |
2258 | uint64_t reserved_14_63:50; | |
2259 | uint64_t mask:14; | |
2260 | #else | |
2261 | uint64_t mask:14; | |
2262 | uint64_t reserved_14_63:50; | |
2263 | #endif | |
2264 | } cn61xx; | |
2265 | struct cvmx_pko_reg_engine_thresh_cn63xx { | |
2266 | #ifdef __BIG_ENDIAN_BITFIELD | |
2267 | uint64_t reserved_12_63:52; | |
2268 | uint64_t mask:12; | |
2269 | #else | |
2270 | uint64_t mask:12; | |
2271 | uint64_t reserved_12_63:52; | |
2272 | #endif | |
2273 | } cn63xx; | |
2274 | struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; | |
2275 | struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; | |
2276 | struct cvmx_pko_reg_engine_thresh_s cn68xx; | |
2277 | struct cvmx_pko_reg_engine_thresh_s cn68xxp1; | |
2278 | struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; | |
80ff0fd3 DD |
2279 | }; |
2280 | ||
2281 | union cvmx_pko_reg_error { | |
2282 | uint64_t u64; | |
2283 | struct cvmx_pko_reg_error_s { | |
c5aa59e8 DD |
2284 | #ifdef __BIG_ENDIAN_BITFIELD |
2285 | uint64_t reserved_4_63:60; | |
2286 | uint64_t loopback:1; | |
80ff0fd3 DD |
2287 | uint64_t currzero:1; |
2288 | uint64_t doorbell:1; | |
2289 | uint64_t parity:1; | |
c5aa59e8 DD |
2290 | #else |
2291 | uint64_t parity:1; | |
2292 | uint64_t doorbell:1; | |
2293 | uint64_t currzero:1; | |
2294 | uint64_t loopback:1; | |
2295 | uint64_t reserved_4_63:60; | |
2296 | #endif | |
80ff0fd3 DD |
2297 | } s; |
2298 | struct cvmx_pko_reg_error_cn30xx { | |
c5aa59e8 | 2299 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2300 | uint64_t reserved_2_63:62; |
2301 | uint64_t doorbell:1; | |
2302 | uint64_t parity:1; | |
c5aa59e8 DD |
2303 | #else |
2304 | uint64_t parity:1; | |
2305 | uint64_t doorbell:1; | |
2306 | uint64_t reserved_2_63:62; | |
2307 | #endif | |
80ff0fd3 DD |
2308 | } cn30xx; |
2309 | struct cvmx_pko_reg_error_cn30xx cn31xx; | |
2310 | struct cvmx_pko_reg_error_cn30xx cn38xx; | |
2311 | struct cvmx_pko_reg_error_cn30xx cn38xxp2; | |
c5aa59e8 DD |
2312 | struct cvmx_pko_reg_error_cn50xx { |
2313 | #ifdef __BIG_ENDIAN_BITFIELD | |
2314 | uint64_t reserved_3_63:61; | |
2315 | uint64_t currzero:1; | |
2316 | uint64_t doorbell:1; | |
2317 | uint64_t parity:1; | |
2318 | #else | |
2319 | uint64_t parity:1; | |
2320 | uint64_t doorbell:1; | |
2321 | uint64_t currzero:1; | |
2322 | uint64_t reserved_3_63:61; | |
2323 | #endif | |
2324 | } cn50xx; | |
2325 | struct cvmx_pko_reg_error_cn50xx cn52xx; | |
2326 | struct cvmx_pko_reg_error_cn50xx cn52xxp1; | |
2327 | struct cvmx_pko_reg_error_cn50xx cn56xx; | |
2328 | struct cvmx_pko_reg_error_cn50xx cn56xxp1; | |
2329 | struct cvmx_pko_reg_error_cn50xx cn58xx; | |
2330 | struct cvmx_pko_reg_error_cn50xx cn58xxp1; | |
2331 | struct cvmx_pko_reg_error_cn50xx cn61xx; | |
2332 | struct cvmx_pko_reg_error_cn50xx cn63xx; | |
2333 | struct cvmx_pko_reg_error_cn50xx cn63xxp1; | |
2334 | struct cvmx_pko_reg_error_cn50xx cn66xx; | |
2335 | struct cvmx_pko_reg_error_s cn68xx; | |
2336 | struct cvmx_pko_reg_error_s cn68xxp1; | |
2337 | struct cvmx_pko_reg_error_cn50xx cnf71xx; | |
80ff0fd3 DD |
2338 | }; |
2339 | ||
2340 | union cvmx_pko_reg_flags { | |
2341 | uint64_t u64; | |
2342 | struct cvmx_pko_reg_flags_s { | |
c5aa59e8 DD |
2343 | #ifdef __BIG_ENDIAN_BITFIELD |
2344 | uint64_t reserved_9_63:55; | |
2345 | uint64_t dis_perf3:1; | |
2346 | uint64_t dis_perf2:1; | |
2347 | uint64_t dis_perf1:1; | |
2348 | uint64_t dis_perf0:1; | |
2349 | uint64_t ena_throttle:1; | |
80ff0fd3 DD |
2350 | uint64_t reset:1; |
2351 | uint64_t store_be:1; | |
2352 | uint64_t ena_dwb:1; | |
2353 | uint64_t ena_pko:1; | |
c5aa59e8 DD |
2354 | #else |
2355 | uint64_t ena_pko:1; | |
2356 | uint64_t ena_dwb:1; | |
2357 | uint64_t store_be:1; | |
2358 | uint64_t reset:1; | |
2359 | uint64_t ena_throttle:1; | |
2360 | uint64_t dis_perf0:1; | |
2361 | uint64_t dis_perf1:1; | |
2362 | uint64_t dis_perf2:1; | |
2363 | uint64_t dis_perf3:1; | |
2364 | uint64_t reserved_9_63:55; | |
2365 | #endif | |
80ff0fd3 | 2366 | } s; |
c5aa59e8 DD |
2367 | struct cvmx_pko_reg_flags_cn30xx { |
2368 | #ifdef __BIG_ENDIAN_BITFIELD | |
2369 | uint64_t reserved_4_63:60; | |
2370 | uint64_t reset:1; | |
2371 | uint64_t store_be:1; | |
2372 | uint64_t ena_dwb:1; | |
2373 | uint64_t ena_pko:1; | |
2374 | #else | |
2375 | uint64_t ena_pko:1; | |
2376 | uint64_t ena_dwb:1; | |
2377 | uint64_t store_be:1; | |
2378 | uint64_t reset:1; | |
2379 | uint64_t reserved_4_63:60; | |
2380 | #endif | |
2381 | } cn30xx; | |
2382 | struct cvmx_pko_reg_flags_cn30xx cn31xx; | |
2383 | struct cvmx_pko_reg_flags_cn30xx cn38xx; | |
2384 | struct cvmx_pko_reg_flags_cn30xx cn38xxp2; | |
2385 | struct cvmx_pko_reg_flags_cn30xx cn50xx; | |
2386 | struct cvmx_pko_reg_flags_cn30xx cn52xx; | |
2387 | struct cvmx_pko_reg_flags_cn30xx cn52xxp1; | |
2388 | struct cvmx_pko_reg_flags_cn30xx cn56xx; | |
2389 | struct cvmx_pko_reg_flags_cn30xx cn56xxp1; | |
2390 | struct cvmx_pko_reg_flags_cn30xx cn58xx; | |
2391 | struct cvmx_pko_reg_flags_cn30xx cn58xxp1; | |
2392 | struct cvmx_pko_reg_flags_cn61xx { | |
2393 | #ifdef __BIG_ENDIAN_BITFIELD | |
2394 | uint64_t reserved_9_63:55; | |
2395 | uint64_t dis_perf3:1; | |
2396 | uint64_t dis_perf2:1; | |
2397 | uint64_t reserved_4_6:3; | |
2398 | uint64_t reset:1; | |
2399 | uint64_t store_be:1; | |
2400 | uint64_t ena_dwb:1; | |
2401 | uint64_t ena_pko:1; | |
2402 | #else | |
2403 | uint64_t ena_pko:1; | |
2404 | uint64_t ena_dwb:1; | |
2405 | uint64_t store_be:1; | |
2406 | uint64_t reset:1; | |
2407 | uint64_t reserved_4_6:3; | |
2408 | uint64_t dis_perf2:1; | |
2409 | uint64_t dis_perf3:1; | |
2410 | uint64_t reserved_9_63:55; | |
2411 | #endif | |
2412 | } cn61xx; | |
2413 | struct cvmx_pko_reg_flags_cn30xx cn63xx; | |
2414 | struct cvmx_pko_reg_flags_cn30xx cn63xxp1; | |
2415 | struct cvmx_pko_reg_flags_cn61xx cn66xx; | |
2416 | struct cvmx_pko_reg_flags_s cn68xx; | |
2417 | struct cvmx_pko_reg_flags_cn68xxp1 { | |
2418 | #ifdef __BIG_ENDIAN_BITFIELD | |
2419 | uint64_t reserved_7_63:57; | |
2420 | uint64_t dis_perf1:1; | |
2421 | uint64_t dis_perf0:1; | |
2422 | uint64_t ena_throttle:1; | |
2423 | uint64_t reset:1; | |
2424 | uint64_t store_be:1; | |
2425 | uint64_t ena_dwb:1; | |
2426 | uint64_t ena_pko:1; | |
2427 | #else | |
2428 | uint64_t ena_pko:1; | |
2429 | uint64_t ena_dwb:1; | |
2430 | uint64_t store_be:1; | |
2431 | uint64_t reset:1; | |
2432 | uint64_t ena_throttle:1; | |
2433 | uint64_t dis_perf0:1; | |
2434 | uint64_t dis_perf1:1; | |
2435 | uint64_t reserved_7_63:57; | |
2436 | #endif | |
2437 | } cn68xxp1; | |
2438 | struct cvmx_pko_reg_flags_cn61xx cnf71xx; | |
80ff0fd3 DD |
2439 | }; |
2440 | ||
2441 | union cvmx_pko_reg_gmx_port_mode { | |
2442 | uint64_t u64; | |
2443 | struct cvmx_pko_reg_gmx_port_mode_s { | |
c5aa59e8 | 2444 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2445 | uint64_t reserved_6_63:58; |
2446 | uint64_t mode1:3; | |
2447 | uint64_t mode0:3; | |
c5aa59e8 DD |
2448 | #else |
2449 | uint64_t mode0:3; | |
2450 | uint64_t mode1:3; | |
2451 | uint64_t reserved_6_63:58; | |
2452 | #endif | |
80ff0fd3 DD |
2453 | } s; |
2454 | struct cvmx_pko_reg_gmx_port_mode_s cn30xx; | |
2455 | struct cvmx_pko_reg_gmx_port_mode_s cn31xx; | |
2456 | struct cvmx_pko_reg_gmx_port_mode_s cn38xx; | |
2457 | struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; | |
2458 | struct cvmx_pko_reg_gmx_port_mode_s cn50xx; | |
2459 | struct cvmx_pko_reg_gmx_port_mode_s cn52xx; | |
2460 | struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; | |
2461 | struct cvmx_pko_reg_gmx_port_mode_s cn56xx; | |
2462 | struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; | |
2463 | struct cvmx_pko_reg_gmx_port_mode_s cn58xx; | |
2464 | struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; | |
c5aa59e8 DD |
2465 | struct cvmx_pko_reg_gmx_port_mode_s cn61xx; |
2466 | struct cvmx_pko_reg_gmx_port_mode_s cn63xx; | |
2467 | struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; | |
2468 | struct cvmx_pko_reg_gmx_port_mode_s cn66xx; | |
2469 | struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; | |
80ff0fd3 DD |
2470 | }; |
2471 | ||
2472 | union cvmx_pko_reg_int_mask { | |
2473 | uint64_t u64; | |
2474 | struct cvmx_pko_reg_int_mask_s { | |
c5aa59e8 DD |
2475 | #ifdef __BIG_ENDIAN_BITFIELD |
2476 | uint64_t reserved_4_63:60; | |
2477 | uint64_t loopback:1; | |
80ff0fd3 DD |
2478 | uint64_t currzero:1; |
2479 | uint64_t doorbell:1; | |
2480 | uint64_t parity:1; | |
c5aa59e8 DD |
2481 | #else |
2482 | uint64_t parity:1; | |
2483 | uint64_t doorbell:1; | |
2484 | uint64_t currzero:1; | |
2485 | uint64_t loopback:1; | |
2486 | uint64_t reserved_4_63:60; | |
2487 | #endif | |
80ff0fd3 DD |
2488 | } s; |
2489 | struct cvmx_pko_reg_int_mask_cn30xx { | |
c5aa59e8 | 2490 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2491 | uint64_t reserved_2_63:62; |
2492 | uint64_t doorbell:1; | |
2493 | uint64_t parity:1; | |
c5aa59e8 DD |
2494 | #else |
2495 | uint64_t parity:1; | |
2496 | uint64_t doorbell:1; | |
2497 | uint64_t reserved_2_63:62; | |
2498 | #endif | |
80ff0fd3 DD |
2499 | } cn30xx; |
2500 | struct cvmx_pko_reg_int_mask_cn30xx cn31xx; | |
2501 | struct cvmx_pko_reg_int_mask_cn30xx cn38xx; | |
2502 | struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; | |
c5aa59e8 DD |
2503 | struct cvmx_pko_reg_int_mask_cn50xx { |
2504 | #ifdef __BIG_ENDIAN_BITFIELD | |
2505 | uint64_t reserved_3_63:61; | |
2506 | uint64_t currzero:1; | |
2507 | uint64_t doorbell:1; | |
2508 | uint64_t parity:1; | |
2509 | #else | |
2510 | uint64_t parity:1; | |
2511 | uint64_t doorbell:1; | |
2512 | uint64_t currzero:1; | |
2513 | uint64_t reserved_3_63:61; | |
2514 | #endif | |
2515 | } cn50xx; | |
2516 | struct cvmx_pko_reg_int_mask_cn50xx cn52xx; | |
2517 | struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; | |
2518 | struct cvmx_pko_reg_int_mask_cn50xx cn56xx; | |
2519 | struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; | |
2520 | struct cvmx_pko_reg_int_mask_cn50xx cn58xx; | |
2521 | struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; | |
2522 | struct cvmx_pko_reg_int_mask_cn50xx cn61xx; | |
2523 | struct cvmx_pko_reg_int_mask_cn50xx cn63xx; | |
2524 | struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; | |
2525 | struct cvmx_pko_reg_int_mask_cn50xx cn66xx; | |
2526 | struct cvmx_pko_reg_int_mask_s cn68xx; | |
2527 | struct cvmx_pko_reg_int_mask_s cn68xxp1; | |
2528 | struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; | |
2529 | }; | |
2530 | ||
2531 | union cvmx_pko_reg_loopback_bpid { | |
2532 | uint64_t u64; | |
2533 | struct cvmx_pko_reg_loopback_bpid_s { | |
2534 | #ifdef __BIG_ENDIAN_BITFIELD | |
2535 | uint64_t reserved_59_63:5; | |
2536 | uint64_t bpid7:6; | |
2537 | uint64_t reserved_52_52:1; | |
2538 | uint64_t bpid6:6; | |
2539 | uint64_t reserved_45_45:1; | |
2540 | uint64_t bpid5:6; | |
2541 | uint64_t reserved_38_38:1; | |
2542 | uint64_t bpid4:6; | |
2543 | uint64_t reserved_31_31:1; | |
2544 | uint64_t bpid3:6; | |
2545 | uint64_t reserved_24_24:1; | |
2546 | uint64_t bpid2:6; | |
2547 | uint64_t reserved_17_17:1; | |
2548 | uint64_t bpid1:6; | |
2549 | uint64_t reserved_10_10:1; | |
2550 | uint64_t bpid0:6; | |
2551 | uint64_t reserved_0_3:4; | |
2552 | #else | |
2553 | uint64_t reserved_0_3:4; | |
2554 | uint64_t bpid0:6; | |
2555 | uint64_t reserved_10_10:1; | |
2556 | uint64_t bpid1:6; | |
2557 | uint64_t reserved_17_17:1; | |
2558 | uint64_t bpid2:6; | |
2559 | uint64_t reserved_24_24:1; | |
2560 | uint64_t bpid3:6; | |
2561 | uint64_t reserved_31_31:1; | |
2562 | uint64_t bpid4:6; | |
2563 | uint64_t reserved_38_38:1; | |
2564 | uint64_t bpid5:6; | |
2565 | uint64_t reserved_45_45:1; | |
2566 | uint64_t bpid6:6; | |
2567 | uint64_t reserved_52_52:1; | |
2568 | uint64_t bpid7:6; | |
2569 | uint64_t reserved_59_63:5; | |
2570 | #endif | |
2571 | } s; | |
2572 | struct cvmx_pko_reg_loopback_bpid_s cn68xx; | |
2573 | struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; | |
2574 | }; | |
2575 | ||
2576 | union cvmx_pko_reg_loopback_pkind { | |
2577 | uint64_t u64; | |
2578 | struct cvmx_pko_reg_loopback_pkind_s { | |
2579 | #ifdef __BIG_ENDIAN_BITFIELD | |
2580 | uint64_t reserved_59_63:5; | |
2581 | uint64_t pkind7:6; | |
2582 | uint64_t reserved_52_52:1; | |
2583 | uint64_t pkind6:6; | |
2584 | uint64_t reserved_45_45:1; | |
2585 | uint64_t pkind5:6; | |
2586 | uint64_t reserved_38_38:1; | |
2587 | uint64_t pkind4:6; | |
2588 | uint64_t reserved_31_31:1; | |
2589 | uint64_t pkind3:6; | |
2590 | uint64_t reserved_24_24:1; | |
2591 | uint64_t pkind2:6; | |
2592 | uint64_t reserved_17_17:1; | |
2593 | uint64_t pkind1:6; | |
2594 | uint64_t reserved_10_10:1; | |
2595 | uint64_t pkind0:6; | |
2596 | uint64_t num_ports:4; | |
2597 | #else | |
2598 | uint64_t num_ports:4; | |
2599 | uint64_t pkind0:6; | |
2600 | uint64_t reserved_10_10:1; | |
2601 | uint64_t pkind1:6; | |
2602 | uint64_t reserved_17_17:1; | |
2603 | uint64_t pkind2:6; | |
2604 | uint64_t reserved_24_24:1; | |
2605 | uint64_t pkind3:6; | |
2606 | uint64_t reserved_31_31:1; | |
2607 | uint64_t pkind4:6; | |
2608 | uint64_t reserved_38_38:1; | |
2609 | uint64_t pkind5:6; | |
2610 | uint64_t reserved_45_45:1; | |
2611 | uint64_t pkind6:6; | |
2612 | uint64_t reserved_52_52:1; | |
2613 | uint64_t pkind7:6; | |
2614 | uint64_t reserved_59_63:5; | |
2615 | #endif | |
2616 | } s; | |
2617 | struct cvmx_pko_reg_loopback_pkind_s cn68xx; | |
2618 | struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; | |
2619 | }; | |
2620 | ||
2621 | union cvmx_pko_reg_min_pkt { | |
2622 | uint64_t u64; | |
2623 | struct cvmx_pko_reg_min_pkt_s { | |
2624 | #ifdef __BIG_ENDIAN_BITFIELD | |
2625 | uint64_t size7:8; | |
2626 | uint64_t size6:8; | |
2627 | uint64_t size5:8; | |
2628 | uint64_t size4:8; | |
2629 | uint64_t size3:8; | |
2630 | uint64_t size2:8; | |
2631 | uint64_t size1:8; | |
2632 | uint64_t size0:8; | |
2633 | #else | |
2634 | uint64_t size0:8; | |
2635 | uint64_t size1:8; | |
2636 | uint64_t size2:8; | |
2637 | uint64_t size3:8; | |
2638 | uint64_t size4:8; | |
2639 | uint64_t size5:8; | |
2640 | uint64_t size6:8; | |
2641 | uint64_t size7:8; | |
2642 | #endif | |
2643 | } s; | |
2644 | struct cvmx_pko_reg_min_pkt_s cn68xx; | |
2645 | struct cvmx_pko_reg_min_pkt_s cn68xxp1; | |
2646 | }; | |
2647 | ||
2648 | union cvmx_pko_reg_preempt { | |
2649 | uint64_t u64; | |
2650 | struct cvmx_pko_reg_preempt_s { | |
2651 | #ifdef __BIG_ENDIAN_BITFIELD | |
2652 | uint64_t reserved_16_63:48; | |
2653 | uint64_t min_size:16; | |
2654 | #else | |
2655 | uint64_t min_size:16; | |
2656 | uint64_t reserved_16_63:48; | |
2657 | #endif | |
2658 | } s; | |
2659 | struct cvmx_pko_reg_preempt_s cn52xx; | |
2660 | struct cvmx_pko_reg_preempt_s cn52xxp1; | |
2661 | struct cvmx_pko_reg_preempt_s cn56xx; | |
2662 | struct cvmx_pko_reg_preempt_s cn56xxp1; | |
2663 | struct cvmx_pko_reg_preempt_s cn61xx; | |
2664 | struct cvmx_pko_reg_preempt_s cn63xx; | |
2665 | struct cvmx_pko_reg_preempt_s cn63xxp1; | |
2666 | struct cvmx_pko_reg_preempt_s cn66xx; | |
2667 | struct cvmx_pko_reg_preempt_s cn68xx; | |
2668 | struct cvmx_pko_reg_preempt_s cn68xxp1; | |
2669 | struct cvmx_pko_reg_preempt_s cnf71xx; | |
80ff0fd3 DD |
2670 | }; |
2671 | ||
2672 | union cvmx_pko_reg_queue_mode { | |
2673 | uint64_t u64; | |
2674 | struct cvmx_pko_reg_queue_mode_s { | |
c5aa59e8 | 2675 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2676 | uint64_t reserved_2_63:62; |
2677 | uint64_t mode:2; | |
c5aa59e8 DD |
2678 | #else |
2679 | uint64_t mode:2; | |
2680 | uint64_t reserved_2_63:62; | |
2681 | #endif | |
80ff0fd3 DD |
2682 | } s; |
2683 | struct cvmx_pko_reg_queue_mode_s cn30xx; | |
2684 | struct cvmx_pko_reg_queue_mode_s cn31xx; | |
2685 | struct cvmx_pko_reg_queue_mode_s cn38xx; | |
2686 | struct cvmx_pko_reg_queue_mode_s cn38xxp2; | |
2687 | struct cvmx_pko_reg_queue_mode_s cn50xx; | |
2688 | struct cvmx_pko_reg_queue_mode_s cn52xx; | |
2689 | struct cvmx_pko_reg_queue_mode_s cn52xxp1; | |
2690 | struct cvmx_pko_reg_queue_mode_s cn56xx; | |
2691 | struct cvmx_pko_reg_queue_mode_s cn56xxp1; | |
2692 | struct cvmx_pko_reg_queue_mode_s cn58xx; | |
2693 | struct cvmx_pko_reg_queue_mode_s cn58xxp1; | |
c5aa59e8 DD |
2694 | struct cvmx_pko_reg_queue_mode_s cn61xx; |
2695 | struct cvmx_pko_reg_queue_mode_s cn63xx; | |
2696 | struct cvmx_pko_reg_queue_mode_s cn63xxp1; | |
2697 | struct cvmx_pko_reg_queue_mode_s cn66xx; | |
2698 | struct cvmx_pko_reg_queue_mode_s cn68xx; | |
2699 | struct cvmx_pko_reg_queue_mode_s cn68xxp1; | |
2700 | struct cvmx_pko_reg_queue_mode_s cnf71xx; | |
2701 | }; | |
2702 | ||
2703 | union cvmx_pko_reg_queue_preempt { | |
2704 | uint64_t u64; | |
2705 | struct cvmx_pko_reg_queue_preempt_s { | |
2706 | #ifdef __BIG_ENDIAN_BITFIELD | |
2707 | uint64_t reserved_2_63:62; | |
2708 | uint64_t preemptee:1; | |
2709 | uint64_t preempter:1; | |
2710 | #else | |
2711 | uint64_t preempter:1; | |
2712 | uint64_t preemptee:1; | |
2713 | uint64_t reserved_2_63:62; | |
2714 | #endif | |
2715 | } s; | |
2716 | struct cvmx_pko_reg_queue_preempt_s cn52xx; | |
2717 | struct cvmx_pko_reg_queue_preempt_s cn52xxp1; | |
2718 | struct cvmx_pko_reg_queue_preempt_s cn56xx; | |
2719 | struct cvmx_pko_reg_queue_preempt_s cn56xxp1; | |
2720 | struct cvmx_pko_reg_queue_preempt_s cn61xx; | |
2721 | struct cvmx_pko_reg_queue_preempt_s cn63xx; | |
2722 | struct cvmx_pko_reg_queue_preempt_s cn63xxp1; | |
2723 | struct cvmx_pko_reg_queue_preempt_s cn66xx; | |
2724 | struct cvmx_pko_reg_queue_preempt_s cn68xx; | |
2725 | struct cvmx_pko_reg_queue_preempt_s cn68xxp1; | |
2726 | struct cvmx_pko_reg_queue_preempt_s cnf71xx; | |
80ff0fd3 DD |
2727 | }; |
2728 | ||
2729 | union cvmx_pko_reg_queue_ptrs1 { | |
2730 | uint64_t u64; | |
2731 | struct cvmx_pko_reg_queue_ptrs1_s { | |
c5aa59e8 | 2732 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2733 | uint64_t reserved_2_63:62; |
2734 | uint64_t idx3:1; | |
2735 | uint64_t qid7:1; | |
c5aa59e8 DD |
2736 | #else |
2737 | uint64_t qid7:1; | |
2738 | uint64_t idx3:1; | |
2739 | uint64_t reserved_2_63:62; | |
2740 | #endif | |
80ff0fd3 DD |
2741 | } s; |
2742 | struct cvmx_pko_reg_queue_ptrs1_s cn50xx; | |
2743 | struct cvmx_pko_reg_queue_ptrs1_s cn52xx; | |
2744 | struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; | |
2745 | struct cvmx_pko_reg_queue_ptrs1_s cn56xx; | |
2746 | struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; | |
2747 | struct cvmx_pko_reg_queue_ptrs1_s cn58xx; | |
2748 | struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; | |
c5aa59e8 DD |
2749 | struct cvmx_pko_reg_queue_ptrs1_s cn61xx; |
2750 | struct cvmx_pko_reg_queue_ptrs1_s cn63xx; | |
2751 | struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; | |
2752 | struct cvmx_pko_reg_queue_ptrs1_s cn66xx; | |
2753 | struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; | |
80ff0fd3 DD |
2754 | }; |
2755 | ||
2756 | union cvmx_pko_reg_read_idx { | |
2757 | uint64_t u64; | |
2758 | struct cvmx_pko_reg_read_idx_s { | |
c5aa59e8 | 2759 | #ifdef __BIG_ENDIAN_BITFIELD |
80ff0fd3 DD |
2760 | uint64_t reserved_16_63:48; |
2761 | uint64_t inc:8; | |
2762 | uint64_t index:8; | |
c5aa59e8 DD |
2763 | #else |
2764 | uint64_t index:8; | |
2765 | uint64_t inc:8; | |
2766 | uint64_t reserved_16_63:48; | |
2767 | #endif | |
80ff0fd3 DD |
2768 | } s; |
2769 | struct cvmx_pko_reg_read_idx_s cn30xx; | |
2770 | struct cvmx_pko_reg_read_idx_s cn31xx; | |
2771 | struct cvmx_pko_reg_read_idx_s cn38xx; | |
2772 | struct cvmx_pko_reg_read_idx_s cn38xxp2; | |
2773 | struct cvmx_pko_reg_read_idx_s cn50xx; | |
2774 | struct cvmx_pko_reg_read_idx_s cn52xx; | |
2775 | struct cvmx_pko_reg_read_idx_s cn52xxp1; | |
2776 | struct cvmx_pko_reg_read_idx_s cn56xx; | |
2777 | struct cvmx_pko_reg_read_idx_s cn56xxp1; | |
2778 | struct cvmx_pko_reg_read_idx_s cn58xx; | |
2779 | struct cvmx_pko_reg_read_idx_s cn58xxp1; | |
c5aa59e8 DD |
2780 | struct cvmx_pko_reg_read_idx_s cn61xx; |
2781 | struct cvmx_pko_reg_read_idx_s cn63xx; | |
2782 | struct cvmx_pko_reg_read_idx_s cn63xxp1; | |
2783 | struct cvmx_pko_reg_read_idx_s cn66xx; | |
2784 | struct cvmx_pko_reg_read_idx_s cn68xx; | |
2785 | struct cvmx_pko_reg_read_idx_s cn68xxp1; | |
2786 | struct cvmx_pko_reg_read_idx_s cnf71xx; | |
2787 | }; | |
2788 | ||
2789 | union cvmx_pko_reg_throttle { | |
2790 | uint64_t u64; | |
2791 | struct cvmx_pko_reg_throttle_s { | |
2792 | #ifdef __BIG_ENDIAN_BITFIELD | |
2793 | uint64_t reserved_32_63:32; | |
2794 | uint64_t int_mask:32; | |
2795 | #else | |
2796 | uint64_t int_mask:32; | |
2797 | uint64_t reserved_32_63:32; | |
2798 | #endif | |
2799 | } s; | |
2800 | struct cvmx_pko_reg_throttle_s cn68xx; | |
2801 | struct cvmx_pko_reg_throttle_s cn68xxp1; | |
2802 | }; | |
2803 | ||
2804 | union cvmx_pko_reg_timestamp { | |
2805 | uint64_t u64; | |
2806 | struct cvmx_pko_reg_timestamp_s { | |
2807 | #ifdef __BIG_ENDIAN_BITFIELD | |
2808 | uint64_t reserved_4_63:60; | |
2809 | uint64_t wqe_word:4; | |
2810 | #else | |
2811 | uint64_t wqe_word:4; | |
2812 | uint64_t reserved_4_63:60; | |
2813 | #endif | |
2814 | } s; | |
2815 | struct cvmx_pko_reg_timestamp_s cn61xx; | |
2816 | struct cvmx_pko_reg_timestamp_s cn63xx; | |
2817 | struct cvmx_pko_reg_timestamp_s cn63xxp1; | |
2818 | struct cvmx_pko_reg_timestamp_s cn66xx; | |
2819 | struct cvmx_pko_reg_timestamp_s cn68xx; | |
2820 | struct cvmx_pko_reg_timestamp_s cn68xxp1; | |
2821 | struct cvmx_pko_reg_timestamp_s cnf71xx; | |
80ff0fd3 DD |
2822 | }; |
2823 | ||
2824 | #endif |