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Merge tag 'kvm-arm-for-4.3-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / mips / include / asm / octeon / cvmx-spxx-defs.h
CommitLineData
80ff0fd3
DD		 1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
c5aa59e8 7 * Copyright (c) 2003-2012 Cavium Networks
80ff0fd3
DD		 8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SPXX_DEFS_H__
29#define __CVMX_SPXX_DEFS_H__
30
c5aa59e8
DD		 31#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
36#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
37#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
38#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
39#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
40#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
41#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
42#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
43#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
44#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
45#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
46#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
80ff0fd3
DD		 47
48union cvmx_spxx_bckprs_cnt {
49 uint64_t u64;
50 struct cvmx_spxx_bckprs_cnt_s {
c5aa59e8 51#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 52 uint64_t reserved_32_63:32;
53 uint64_t cnt:32;
c5aa59e8
DD		 54#else
55 uint64_t cnt:32;
56 uint64_t reserved_32_63:32;
57#endif
80ff0fd3
DD		 58 } s;
59 struct cvmx_spxx_bckprs_cnt_s cn38xx;
60 struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
61 struct cvmx_spxx_bckprs_cnt_s cn58xx;
62 struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
63};
64
65union cvmx_spxx_bist_stat {
66 uint64_t u64;
67 struct cvmx_spxx_bist_stat_s {
c5aa59e8 68#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 69 uint64_t reserved_3_63:61;
70 uint64_t stat2:1;
71 uint64_t stat1:1;
72 uint64_t stat0:1;
c5aa59e8
DD		 73#else
74 uint64_t stat0:1;
75 uint64_t stat1:1;
76 uint64_t stat2:1;
77 uint64_t reserved_3_63:61;
78#endif
80ff0fd3
DD		 79 } s;
80 struct cvmx_spxx_bist_stat_s cn38xx;
81 struct cvmx_spxx_bist_stat_s cn38xxp2;
82 struct cvmx_spxx_bist_stat_s cn58xx;
83 struct cvmx_spxx_bist_stat_s cn58xxp1;
84};
85
86union cvmx_spxx_clk_ctl {
87 uint64_t u64;
88 struct cvmx_spxx_clk_ctl_s {
c5aa59e8 89#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 90 uint64_t reserved_17_63:47;
91 uint64_t seetrn:1;
92 uint64_t reserved_12_15:4;
93 uint64_t clkdly:5;
94 uint64_t runbist:1;
95 uint64_t statdrv:1;
96 uint64_t statrcv:1;
97 uint64_t sndtrn:1;
98 uint64_t drptrn:1;
99 uint64_t rcvtrn:1;
100 uint64_t srxdlck:1;
c5aa59e8
DD		 101#else
102 uint64_t srxdlck:1;
103 uint64_t rcvtrn:1;
104 uint64_t drptrn:1;
105 uint64_t sndtrn:1;
106 uint64_t statrcv:1;
107 uint64_t statdrv:1;
108 uint64_t runbist:1;
109 uint64_t clkdly:5;
110 uint64_t reserved_12_15:4;
111 uint64_t seetrn:1;
112 uint64_t reserved_17_63:47;
113#endif
80ff0fd3
DD		 114 } s;
115 struct cvmx_spxx_clk_ctl_s cn38xx;
116 struct cvmx_spxx_clk_ctl_s cn38xxp2;
117 struct cvmx_spxx_clk_ctl_s cn58xx;
118 struct cvmx_spxx_clk_ctl_s cn58xxp1;
119};
120
121union cvmx_spxx_clk_stat {
122 uint64_t u64;
123 struct cvmx_spxx_clk_stat_s {
c5aa59e8 124#ifdef __BIG_ENDIAN_BITFIELD
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DD		 125 uint64_t reserved_11_63:53;
126 uint64_t stxcal:1;
127 uint64_t reserved_9_9:1;
128 uint64_t srxtrn:1;
129 uint64_t s4clk1:1;
130 uint64_t s4clk0:1;
131 uint64_t d4clk1:1;
132 uint64_t d4clk0:1;
133 uint64_t reserved_0_3:4;
c5aa59e8
DD		 134#else
135 uint64_t reserved_0_3:4;
136 uint64_t d4clk0:1;
137 uint64_t d4clk1:1;
138 uint64_t s4clk0:1;
139 uint64_t s4clk1:1;
140 uint64_t srxtrn:1;
141 uint64_t reserved_9_9:1;
142 uint64_t stxcal:1;
143 uint64_t reserved_11_63:53;
144#endif
80ff0fd3
DD		 145 } s;
146 struct cvmx_spxx_clk_stat_s cn38xx;
147 struct cvmx_spxx_clk_stat_s cn38xxp2;
148 struct cvmx_spxx_clk_stat_s cn58xx;
149 struct cvmx_spxx_clk_stat_s cn58xxp1;
150};
151
152union cvmx_spxx_dbg_deskew_ctl {
153 uint64_t u64;
154 struct cvmx_spxx_dbg_deskew_ctl_s {
c5aa59e8 155#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 156 uint64_t reserved_30_63:34;
157 uint64_t fallnop:1;
158 uint64_t fall8:1;
159 uint64_t reserved_26_27:2;
160 uint64_t sstep_go:1;
161 uint64_t sstep:1;
162 uint64_t reserved_22_23:2;
163 uint64_t clrdly:1;
164 uint64_t dec:1;
165 uint64_t inc:1;
166 uint64_t mux:1;
167 uint64_t offset:5;
168 uint64_t bitsel:5;
169 uint64_t offdly:6;
170 uint64_t dllfrc:1;
171 uint64_t dlldis:1;
c5aa59e8
DD		 172#else
173 uint64_t dlldis:1;
174 uint64_t dllfrc:1;
175 uint64_t offdly:6;
176 uint64_t bitsel:5;
177 uint64_t offset:5;
178 uint64_t mux:1;
179 uint64_t inc:1;
180 uint64_t dec:1;
181 uint64_t clrdly:1;
182 uint64_t reserved_22_23:2;
183 uint64_t sstep:1;
184 uint64_t sstep_go:1;
185 uint64_t reserved_26_27:2;
186 uint64_t fall8:1;
187 uint64_t fallnop:1;
188 uint64_t reserved_30_63:34;
189#endif
80ff0fd3
DD		 190 } s;
191 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
192 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
193 struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
194 struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
195};
196
197union cvmx_spxx_dbg_deskew_state {
198 uint64_t u64;
199 struct cvmx_spxx_dbg_deskew_state_s {
c5aa59e8 200#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 201 uint64_t reserved_9_63:55;
202 uint64_t testres:1;
203 uint64_t unxterm:1;
204 uint64_t muxsel:2;
205 uint64_t offset:5;
c5aa59e8
DD		 206#else
207 uint64_t offset:5;
208 uint64_t muxsel:2;
209 uint64_t unxterm:1;
210 uint64_t testres:1;
211 uint64_t reserved_9_63:55;
212#endif
80ff0fd3
DD		 213 } s;
214 struct cvmx_spxx_dbg_deskew_state_s cn38xx;
215 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
216 struct cvmx_spxx_dbg_deskew_state_s cn58xx;
217 struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
218};
219
220union cvmx_spxx_drv_ctl {
221 uint64_t u64;
222 struct cvmx_spxx_drv_ctl_s {
c5aa59e8 223#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3 224 uint64_t reserved_0_63:64;
c5aa59e8
DD		 225#else
226 uint64_t reserved_0_63:64;
227#endif
80ff0fd3
DD		 228 } s;
229 struct cvmx_spxx_drv_ctl_cn38xx {
c5aa59e8 230#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 231 uint64_t reserved_16_63:48;
232 uint64_t stx4ncmp:4;
233 uint64_t stx4pcmp:4;
234 uint64_t srx4cmp:8;
c5aa59e8
DD		 235#else
236 uint64_t srx4cmp:8;
237 uint64_t stx4pcmp:4;
238 uint64_t stx4ncmp:4;
239 uint64_t reserved_16_63:48;
240#endif
80ff0fd3
DD		 241 } cn38xx;
242 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
243 struct cvmx_spxx_drv_ctl_cn58xx {
c5aa59e8 244#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 245 uint64_t reserved_24_63:40;
246 uint64_t stx4ncmp:4;
247 uint64_t stx4pcmp:4;
248 uint64_t reserved_10_15:6;
249 uint64_t srx4cmp:10;
c5aa59e8
DD		 250#else
251 uint64_t srx4cmp:10;
252 uint64_t reserved_10_15:6;
253 uint64_t stx4pcmp:4;
254 uint64_t stx4ncmp:4;
255 uint64_t reserved_24_63:40;
256#endif
80ff0fd3
DD		 257 } cn58xx;
258 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
259};
260
261union cvmx_spxx_err_ctl {
262 uint64_t u64;
263 struct cvmx_spxx_err_ctl_s {
c5aa59e8 264#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 265 uint64_t reserved_9_63:55;
266 uint64_t prtnxa:1;
267 uint64_t dipcls:1;
268 uint64_t dippay:1;
269 uint64_t reserved_4_5:2;
270 uint64_t errcnt:4;
c5aa59e8
DD		 271#else
272 uint64_t errcnt:4;
273 uint64_t reserved_4_5:2;
274 uint64_t dippay:1;
275 uint64_t dipcls:1;
276 uint64_t prtnxa:1;
277 uint64_t reserved_9_63:55;
278#endif
80ff0fd3
DD		 279 } s;
280 struct cvmx_spxx_err_ctl_s cn38xx;
281 struct cvmx_spxx_err_ctl_s cn38xxp2;
282 struct cvmx_spxx_err_ctl_s cn58xx;
283 struct cvmx_spxx_err_ctl_s cn58xxp1;
284};
285
286union cvmx_spxx_int_dat {
287 uint64_t u64;
288 struct cvmx_spxx_int_dat_s {
c5aa59e8 289#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 290 uint64_t reserved_32_63:32;
291 uint64_t mul:1;
292 uint64_t reserved_14_30:17;
293 uint64_t calbnk:2;
294 uint64_t rsvop:4;
295 uint64_t prt:8;
c5aa59e8
DD		 296#else
297 uint64_t prt:8;
298 uint64_t rsvop:4;
299 uint64_t calbnk:2;
300 uint64_t reserved_14_30:17;
301 uint64_t mul:1;
302 uint64_t reserved_32_63:32;
303#endif
80ff0fd3
DD		 304 } s;
305 struct cvmx_spxx_int_dat_s cn38xx;
306 struct cvmx_spxx_int_dat_s cn38xxp2;
307 struct cvmx_spxx_int_dat_s cn58xx;
308 struct cvmx_spxx_int_dat_s cn58xxp1;
309};
310
311union cvmx_spxx_int_msk {
312 uint64_t u64;
313 struct cvmx_spxx_int_msk_s {
c5aa59e8 314#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 315 uint64_t reserved_12_63:52;
316 uint64_t calerr:1;
317 uint64_t syncerr:1;
318 uint64_t diperr:1;
319 uint64_t tpaovr:1;
320 uint64_t rsverr:1;
321 uint64_t drwnng:1;
322 uint64_t clserr:1;
323 uint64_t spiovr:1;
324 uint64_t reserved_2_3:2;
325 uint64_t abnorm:1;
326 uint64_t prtnxa:1;
c5aa59e8
DD		 327#else
328 uint64_t prtnxa:1;
329 uint64_t abnorm:1;
330 uint64_t reserved_2_3:2;
331 uint64_t spiovr:1;
332 uint64_t clserr:1;
333 uint64_t drwnng:1;
334 uint64_t rsverr:1;
335 uint64_t tpaovr:1;
336 uint64_t diperr:1;
337 uint64_t syncerr:1;
338 uint64_t calerr:1;
339 uint64_t reserved_12_63:52;
340#endif
80ff0fd3
DD		 341 } s;
342 struct cvmx_spxx_int_msk_s cn38xx;
343 struct cvmx_spxx_int_msk_s cn38xxp2;
344 struct cvmx_spxx_int_msk_s cn58xx;
345 struct cvmx_spxx_int_msk_s cn58xxp1;
346};
347
348union cvmx_spxx_int_reg {
349 uint64_t u64;
350 struct cvmx_spxx_int_reg_s {
c5aa59e8 351#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 352 uint64_t reserved_32_63:32;
353 uint64_t spf:1;
354 uint64_t reserved_12_30:19;
355 uint64_t calerr:1;
356 uint64_t syncerr:1;
357 uint64_t diperr:1;
358 uint64_t tpaovr:1;
359 uint64_t rsverr:1;
360 uint64_t drwnng:1;
361 uint64_t clserr:1;
362 uint64_t spiovr:1;
363 uint64_t reserved_2_3:2;
364 uint64_t abnorm:1;
365 uint64_t prtnxa:1;
c5aa59e8
DD		 366#else
367 uint64_t prtnxa:1;
368 uint64_t abnorm:1;
369 uint64_t reserved_2_3:2;
370 uint64_t spiovr:1;
371 uint64_t clserr:1;
372 uint64_t drwnng:1;
373 uint64_t rsverr:1;
374 uint64_t tpaovr:1;
375 uint64_t diperr:1;
376 uint64_t syncerr:1;
377 uint64_t calerr:1;
378 uint64_t reserved_12_30:19;
379 uint64_t spf:1;
380 uint64_t reserved_32_63:32;
381#endif
80ff0fd3
DD		 382 } s;
383 struct cvmx_spxx_int_reg_s cn38xx;
384 struct cvmx_spxx_int_reg_s cn38xxp2;
385 struct cvmx_spxx_int_reg_s cn58xx;
386 struct cvmx_spxx_int_reg_s cn58xxp1;
387};
388
389union cvmx_spxx_int_sync {
390 uint64_t u64;
391 struct cvmx_spxx_int_sync_s {
c5aa59e8 392#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 393 uint64_t reserved_12_63:52;
394 uint64_t calerr:1;
395 uint64_t syncerr:1;
396 uint64_t diperr:1;
397 uint64_t tpaovr:1;
398 uint64_t rsverr:1;
399 uint64_t drwnng:1;
400 uint64_t clserr:1;
401 uint64_t spiovr:1;
402 uint64_t reserved_2_3:2;
403 uint64_t abnorm:1;
404 uint64_t prtnxa:1;
c5aa59e8
DD		 405#else
406 uint64_t prtnxa:1;
407 uint64_t abnorm:1;
408 uint64_t reserved_2_3:2;
409 uint64_t spiovr:1;
410 uint64_t clserr:1;
411 uint64_t drwnng:1;
412 uint64_t rsverr:1;
413 uint64_t tpaovr:1;
414 uint64_t diperr:1;
415 uint64_t syncerr:1;
416 uint64_t calerr:1;
417 uint64_t reserved_12_63:52;
418#endif
80ff0fd3
DD		 419 } s;
420 struct cvmx_spxx_int_sync_s cn38xx;
421 struct cvmx_spxx_int_sync_s cn38xxp2;
422 struct cvmx_spxx_int_sync_s cn58xx;
423 struct cvmx_spxx_int_sync_s cn58xxp1;
424};
425
426union cvmx_spxx_tpa_acc {
427 uint64_t u64;
428 struct cvmx_spxx_tpa_acc_s {
c5aa59e8 429#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 430 uint64_t reserved_32_63:32;
431 uint64_t cnt:32;
c5aa59e8
DD		 432#else
433 uint64_t cnt:32;
434 uint64_t reserved_32_63:32;
435#endif
80ff0fd3
DD		 436 } s;
437 struct cvmx_spxx_tpa_acc_s cn38xx;
438 struct cvmx_spxx_tpa_acc_s cn38xxp2;
439 struct cvmx_spxx_tpa_acc_s cn58xx;
440 struct cvmx_spxx_tpa_acc_s cn58xxp1;
441};
442
443union cvmx_spxx_tpa_max {
444 uint64_t u64;
445 struct cvmx_spxx_tpa_max_s {
c5aa59e8 446#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 447 uint64_t reserved_32_63:32;
448 uint64_t max:32;
c5aa59e8
DD		 449#else
450 uint64_t max:32;
451 uint64_t reserved_32_63:32;
452#endif
80ff0fd3
DD		 453 } s;
454 struct cvmx_spxx_tpa_max_s cn38xx;
455 struct cvmx_spxx_tpa_max_s cn38xxp2;
456 struct cvmx_spxx_tpa_max_s cn58xx;
457 struct cvmx_spxx_tpa_max_s cn58xxp1;
458};
459
460union cvmx_spxx_tpa_sel {
461 uint64_t u64;
462 struct cvmx_spxx_tpa_sel_s {
c5aa59e8 463#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 464 uint64_t reserved_4_63:60;
465 uint64_t prtsel:4;
c5aa59e8
DD		 466#else
467 uint64_t prtsel:4;
468 uint64_t reserved_4_63:60;
469#endif
80ff0fd3
DD		 470 } s;
471 struct cvmx_spxx_tpa_sel_s cn38xx;
472 struct cvmx_spxx_tpa_sel_s cn38xxp2;
473 struct cvmx_spxx_tpa_sel_s cn58xx;
474 struct cvmx_spxx_tpa_sel_s cn58xxp1;
475};
476
477union cvmx_spxx_trn4_ctl {
478 uint64_t u64;
479 struct cvmx_spxx_trn4_ctl_s {
c5aa59e8 480#ifdef __BIG_ENDIAN_BITFIELD
80ff0fd3
DD		 481 uint64_t reserved_13_63:51;
482 uint64_t trntest:1;
483 uint64_t jitter:3;
484 uint64_t clr_boot:1;
485 uint64_t set_boot:1;
486 uint64_t maxdist:5;
487 uint64_t macro_en:1;
488 uint64_t mux_en:1;
c5aa59e8
DD		 489#else
490 uint64_t mux_en:1;
491 uint64_t macro_en:1;
492 uint64_t maxdist:5;
493 uint64_t set_boot:1;
494 uint64_t clr_boot:1;
495 uint64_t jitter:3;
496 uint64_t trntest:1;
497 uint64_t reserved_13_63:51;
498#endif
80ff0fd3
DD		 499 } s;
500 struct cvmx_spxx_trn4_ctl_s cn38xx;
501 struct cvmx_spxx_trn4_ctl_s cn38xxp2;
502 struct cvmx_spxx_trn4_ctl_s cn58xx;
503 struct cvmx_spxx_trn4_ctl_s cn58xxp1;
504};
505
506#endif
Linux kernel - Deliverables
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