[deliverable/linux.git] / arch / mips / include / asm / pgtable-64.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 */
#ifndef _ASM_PGTABLE_64_H
#define _ASM_PGTABLE_64_H

#include <linux/compiler.h>
#include <linux/linkage.h>

#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/cachectl.h>
#include <asm/fixmap.h>

#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48)
#include <asm-generic/pgtable-nopmd.h>
#else
#include <asm-generic/pgtable-nopud.h>
#endif

/*
 * Each address space has 2 4K pages as its page directory, giving 1024
 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
 * tables. Each page table is also a single 4K page, giving 512 (==
 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
 * invalid_pmd_table, each pmd entry is initialized to point to
 * invalid_pte_table, each pte is initialized to 0. When memory is low,
 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
 * and empty_bad_page_table is returned back to higher layer code, so
 * that the failure is recognized later on. Linux does not seem to
 * handle these failures very well though. The empty_bad_page_table has
 * invalid pte entries in it, to force page faults.
 *
 * Kernel mappings: kernel mappings are held in the swapper_pg_table.
 * The layout is identical to userspace except it's indexed with the
 * fault address - VMALLOC_START.
 */


/* PGDIR_SHIFT determines what a third-level page table entry can map */
#ifdef __PAGETABLE_PMD_FOLDED
#define PGDIR_SHIFT	(PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
#else

/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))


#define PGDIR_SHIFT	(PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
#endif
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * For 4kB page size we use a 3 level page tree and an 8kB pud, which
 * permits us mapping 40 bits of virtual address space.
 *
 * We used to implement 41 bits by having an order 1 pmd level but that seemed
 * rather pointless.
 *
 * For 8kB page size we use a 3 level page tree which permits a total of
 * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
 * two levels would be easy to implement.
 *
 * For 16kB page size we use a 2 level page tree which permits a total of
 * 36 bits of virtual address space.  We could add a third level but it seems
 * like at the moment there's no need for this.
 *
 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
 * of virtual address space.
 */
#ifdef CONFIG_PAGE_SIZE_4KB
#define PGD_ORDER		1
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_8KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_16KB
#ifdef CONFIG_MIPS_VA_BITS_48
#define PGD_ORDER               1
#else
#define PGD_ORDER               0
#endif
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_32KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_64KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#ifdef CONFIG_MIPS_VA_BITS_48
#define PMD_ORDER		0
#else
#define PMD_ORDER		aieeee_attempt_to_allocate_pmd
#endif
#define PTE_ORDER		0
#endif

#define PTRS_PER_PGD	((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
#ifndef __PAGETABLE_PMD_FOLDED
#define PTRS_PER_PMD	((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
#endif
#define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))

#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
#define FIRST_USER_ADDRESS	0UL

/*
 * TLB refill handlers also map the vmalloc area into xuseg.  Avoid
 * the first couple of pages so NULL pointer dereferences will still
 * reliably trap.
 */
#define VMALLOC_START		(MAP_BASE + (2 * PAGE_SIZE))
#define VMALLOC_END	\
	(MAP_BASE + \
	 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
	     (1UL << cpu_vmbits)) - (1UL << 32))

#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
	VMALLOC_START != CKSSEG
/* Load modules into 32bit-compatible segment. */
#define MODULE_START	CKSSEG
#define MODULE_END	(FIXADDR_START-2*PAGE_SIZE)
#endif

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#ifndef __PAGETABLE_PMD_FOLDED
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
#endif
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))

extern pte_t invalid_pte_table[PTRS_PER_PTE];
extern pte_t empty_bad_page_table[PTRS_PER_PTE];


#ifndef __PAGETABLE_PMD_FOLDED
/*
 * For 3-level pagetables we defines these ourselves, for 2-level the
 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
 */
typedef struct { unsigned long pmd; } pmd_t;
#define pmd_val(x)	((x).pmd)
#define __pmd(x)	((pmd_t) { (x) } )


extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
#endif

/*
 * Empty pgd/pmd entries point to the invalid_pte_table.
 */
static inline int pmd_none(pmd_t pmd)
{
	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}

static inline int pmd_bad(pmd_t pmd)
{
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
	/* pmd_huge(pmd) but inline */
	if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
		return 0;
#endif

	if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
		return 1;

	return 0;
}

static inline int pmd_present(pmd_t pmd)
{
	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}

static inline void pmd_clear(pmd_t *pmdp)
{
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}
#ifndef __PAGETABLE_PMD_FOLDED

/*
 * Empty pud entries point to the invalid_pmd_table.
 */
static inline int pud_none(pud_t pud)
{
	return pud_val(pud) == (unsigned long) invalid_pmd_table;
}

static inline int pud_bad(pud_t pud)
{
	return pud_val(pud) & ~PAGE_MASK;
}

static inline int pud_present(pud_t pud)
{
	return pud_val(pud) != (unsigned long) invalid_pmd_table;
}

static inline void pud_clear(pud_t *pudp)
{
	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
}
#endif

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#ifdef CONFIG_CPU_VR41XX
#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
#else
#define pte_pfn(x)		((unsigned long)((x).pte >> _PFN_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
#define pfn_pmd(pfn, prot)	__pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
#endif

#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address)	pmd_index(address)

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pmd_index(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, addr)	((mm)->pgd + pgd_index(addr))

#ifndef __PAGETABLE_PMD_FOLDED
static inline unsigned long pud_page_vaddr(pud_t pud)
{
	return pud_val(pud);
}
#define pud_phys(pud)		virt_to_phys((void *)pud_val(pud))
#define pud_page(pud)		(pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))

/* Find an entry in the second-level page table.. */
static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
{
	return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
}
#endif

/* Find an entry in the third-level page table.. */
#define __pte_offset(address)						\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_map(dir, address)					\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))

/*
 * Initialize a new pgd / pmd table with invalid pointers.
 */
extern void pgd_init(unsigned long page);
extern void pmd_init(unsigned long page, unsigned long pagetable);

/*
 * Non-present pages:  high 40 bits are offset, next 8 bits type,
 * low 16 bits zero.
 */
static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 16) | (offset << 24); return pte; }

#define __swp_type(x)		(((x).val >> 16) & 0xff)
#define __swp_offset(x)		((x).val >> 24)
#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#endif /* _ASM_PGTABLE_64_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	*/
	9	#ifndef _ASM_PGTABLE_64_H
	10	#define _ASM_PGTABLE_64_H
	11
344afa65	12	#include <linux/compiler.h>
1da177e4 LT	13	#include <linux/linkage.h>
	14
	15	#include <asm/addrspace.h>
	16	#include <asm/page.h>
	17	#include <asm/cachectl.h>
656be92f	18	#include <asm/fixmap.h>
1da177e4	19
1e321fa9	20	#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48)
325f8a0a DD	21	#include <asm-generic/pgtable-nopmd.h>
325f8a0a DD	22	#else
c6e8b587	23	#include <asm-generic/pgtable-nopud.h>
325f8a0a	24	#endif
c6e8b587	25
1da177e4 LT	26	/*
	27	* Each address space has 2 4K pages as its page directory, giving 1024
	28	* (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
c6e8b587 RB	29	* single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
	30	* tables. Each page table is also a single 4K page, giving 512 (==
	31	* PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
	32	* invalid_pmd_table, each pmd entry is initialized to point to
1da177e4 LT	33	* invalid_pte_table, each pte is initialized to 0. When memory is low,
	34	* and a pmd table or a page table allocation fails, empty_bad_pmd_table
	35	* and empty_bad_page_table is returned back to higher layer code, so
	36	* that the failure is recognized later on. Linux does not seem to
	37	* handle these failures very well though. The empty_bad_page_table has
	38	* invalid pte entries in it, to force page faults.
	39	*
	40	* Kernel mappings: kernel mappings are held in the swapper_pg_table.
	41	* The layout is identical to userspace except it's indexed with the
	42	* fault address - VMALLOC_START.
	43	*/
	44
325f8a0a DD	45
	46	/* PGDIR_SHIFT determines what a third-level page table entry can map */
	47	#ifdef __PAGETABLE_PMD_FOLDED
	48	#define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
	49	#else
	50
1da177e4	51	/* PMD_SHIFT determines the size of the area a second-level page table can map */
c6e8b587	52	#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
1da177e4 LT	53	#define PMD_SIZE (1UL << PMD_SHIFT)
	54	#define PMD_MASK (~(PMD_SIZE-1))
	55
325f8a0a	56
c6e8b587	57	#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
325f8a0a	58	#endif
1da177e4 LT	59	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	60	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	61
	62	/*
c6e8b587	63	* For 4kB page size we use a 3 level page tree and an 8kB pud, which
1da177e4 LT	64	* permits us mapping 40 bits of virtual address space.
	65	*
	66	* We used to implement 41 bits by having an order 1 pmd level but that seemed
	67	* rather pointless.
	68	*
	69	* For 8kB page size we use a 3 level page tree which permits a total of
	70	* 8TB of address space. Alternatively a 33-bit / 8GB organization using
	71	* two levels would be easy to implement.
	72	*
	73	* For 16kB page size we use a 2 level page tree which permits a total of
f29244a5	74	* 36 bits of virtual address space. We could add a third level but it seems
1da177e4 LT	75	* like at the moment there's no need for this.
	76	*
	77	* For 64kB page size we use a 2 level page table tree for a total of 42 bits
	78	* of virtual address space.
	79	*/
	80	#ifdef CONFIG_PAGE_SIZE_4KB
	81	#define PGD_ORDER 1
c6e8b587	82	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	83	#define PMD_ORDER 0
	84	#define PTE_ORDER 0
	85	#endif
	86	#ifdef CONFIG_PAGE_SIZE_8KB
	87	#define PGD_ORDER 0
c6e8b587	88	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	89	#define PMD_ORDER 0
	90	#define PTE_ORDER 0
	91	#endif
	92	#ifdef CONFIG_PAGE_SIZE_16KB
1e321fa9 LY	93	#ifdef CONFIG_MIPS_VA_BITS_48
	94	#define PGD_ORDER 1
	95	#else
	96	#define PGD_ORDER 0
	97	#endif
c6e8b587	98	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	99	#define PMD_ORDER 0
	100	#define PTE_ORDER 0
	101	#endif
c52399be RB	102	#ifdef CONFIG_PAGE_SIZE_32KB
	103	#define PGD_ORDER 0
	104	#define PUD_ORDER aieeee_attempt_to_allocate_pud
	105	#define PMD_ORDER 0
	106	#define PTE_ORDER 0
	107	#endif
1da177e4 LT	108	#ifdef CONFIG_PAGE_SIZE_64KB
1da177e4 LT	109	#define PGD_ORDER 0
c6e8b587	110	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1e321fa9 LY	111	#ifdef CONFIG_MIPS_VA_BITS_48
	112	#define PMD_ORDER 0
	113	#else
325f8a0a	114	#define PMD_ORDER aieeee_attempt_to_allocate_pmd
1e321fa9	115	#endif
1da177e4 LT	116	#define PTE_ORDER 0
	117	#endif
	118
	119	#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
325f8a0a	120	#ifndef __PAGETABLE_PMD_FOLDED
1da177e4	121	#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
325f8a0a	122	#endif
1da177e4 LT	123	#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
1da177e4 LT	124
1e321fa9	125	#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
9dbd7b91	126	#define FIRST_USER_ADDRESS 0UL
1da177e4	127
c8f3cc0b DD	128	/*
	129	* TLB refill handlers also map the vmalloc area into xuseg. Avoid
	130	* the first couple of pages so NULL pointer dereferences will still
	131	* reliably trap.
	132	*/
	133	#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
1da177e4	134	#define VMALLOC_END \
c8f3cc0b	135	(MAP_BASE + \
91dfc423 GR	136	min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
	137	(1UL << cpu_vmbits)) - (1UL << 32))
	138
054c51b4	139	#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
656be92f AN	140	VMALLOC_START != CKSSEG
	141	/* Load modules into 32bit-compatible segment. */
	142	#define MODULE_START CKSSEG
	143	#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
656be92f	144	#endif
1da177e4 LT	145
	146	#define pte_ERROR(e) \
	147	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
325f8a0a	148	#ifndef __PAGETABLE_PMD_FOLDED
1da177e4 LT	149	#define pmd_ERROR(e) \
1da177e4 LT	150	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
325f8a0a	151	#endif
1da177e4 LT	152	#define pgd_ERROR(e) \
	153	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
	154
c6e8b587 RB	155	extern pte_t invalid_pte_table[PTRS_PER_PTE];
c6e8b587 RB	156	extern pte_t empty_bad_page_table[PTRS_PER_PTE];
325f8a0a DD	157
	158
	159	#ifndef __PAGETABLE_PMD_FOLDED
	160	/*
	161	* For 3-level pagetables we defines these ourselves, for 2-level the
	162	* definitions are supplied by <asm-generic/pgtable-nopmd.h>.
	163	*/
	164	typedef struct { unsigned long pmd; } pmd_t;
	165	#define pmd_val(x) ((x).pmd)
	166	#define __pmd(x) ((pmd_t) { (x) } )
	167
	168
c6e8b587	169	extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
325f8a0a	170	#endif
1da177e4 LT	171
1da177e4 LT	172	/*
1b3a6e97	173	* Empty pgd/pmd entries point to the invalid_pte_table.
1da177e4 LT	174	*/
	175	static inline int pmd_none(pmd_t pmd)
	176	{
	177	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
	178	}
	179
344afa65 RB	180	static inline int pmd_bad(pmd_t pmd)
344afa65 RB	181	{
970d032f	182	#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
344afa65 RB	183	/* pmd_huge(pmd) but inline */
	184	if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
	185	return 0;
	186	#endif
	187
	188	if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
	189	return 1;
	190
	191	return 0;
	192	}
1da177e4 LT	193
	194	static inline int pmd_present(pmd_t pmd)
	195	{
	196	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
	197	}
	198
	199	static inline void pmd_clear(pmd_t *pmdp)
	200	{
	201	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	202	}
325f8a0a	203	#ifndef __PAGETABLE_PMD_FOLDED
1da177e4 LT	204
1da177e4 LT	205	/*
f29244a5	206	* Empty pud entries point to the invalid_pmd_table.
1da177e4	207	*/
c6e8b587	208	static inline int pud_none(pud_t pud)
1da177e4	209	{
c6e8b587	210	return pud_val(pud) == (unsigned long) invalid_pmd_table;
1da177e4 LT	211	}
1da177e4 LT	212
c6e8b587 RB	213	static inline int pud_bad(pud_t pud)
	214	{
	215	return pud_val(pud) & ~PAGE_MASK;
	216	}
1da177e4	217
c6e8b587	218	static inline int pud_present(pud_t pud)
1da177e4	219	{
c6e8b587	220	return pud_val(pud) != (unsigned long) invalid_pmd_table;
1da177e4 LT	221	}
1da177e4 LT	222
c6e8b587	223	static inline void pud_clear(pud_t *pudp)
1da177e4	224	{
c6e8b587	225	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
1da177e4	226	}
325f8a0a	227	#endif
1da177e4	228
1b3a6e97 TS	229	#define pte_page(x) pfn_to_page(pte_pfn(x))
1b3a6e97 TS	230
1da177e4 LT	231	#ifdef CONFIG_CPU_VR41XX
	232	#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
	233	#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) \| pgprot_val(prot))
	234	#else
6dd9344c DD	235	#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
6dd9344c DD	236	#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) \| pgprot_val(prot))
86ea9c51	237	#define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) \| pgprot_val(prot))
1da177e4 LT	238	#endif
	239
	240	#define __pgd_offset(address) pgd_index(address)
f29244a5	241	#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1b3a6e97	242	#define __pmd_offset(address) pmd_index(address)
1da177e4 LT	243
1da177e4 LT	244	/* to find an entry in a kernel page-table-directory */
e0cc87f5	245	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4	246
f29244a5	247	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1b3a6e97	248	#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1da177e4 LT	249
1da177e4 LT	250	/* to find an entry in a page-table-directory */
21a151d8	251	#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
1da177e4	252
325f8a0a	253	#ifndef __PAGETABLE_PMD_FOLDED
46a82b2d	254	static inline unsigned long pud_page_vaddr(pud_t pud)
1da177e4	255	{
c6e8b587	256	return pud_val(pud);
1da177e4	257	}
c9d06962	258	#define pud_phys(pud) virt_to_phys((void *)pud_val(pud))
46a82b2d	259	#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
1da177e4 LT	260
1da177e4 LT	261	/* Find an entry in the second-level page table.. */
c6e8b587	262	static inline pmd_t pmd_offset(pud_t pud, unsigned long address)
1da177e4	263	{
46a82b2d	264	return (pmd_t ) pud_page_vaddr(pud) + pmd_index(address);
1da177e4	265	}
325f8a0a	266	#endif
1da177e4 LT	267
	268	/* Find an entry in the third-level page table.. */
	269	#define __pte_offset(address) \
	270	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	271	#define pte_offset(dir, address) \
5b70a317	272	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4	273	#define pte_offset_kernel(dir, address) \
5b70a317	274	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4 LT	275	#define pte_offset_map(dir, address) \
1da177e4 LT	276	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
1da177e4	277	#define pte_unmap(pte) ((void)(pte))
1da177e4 LT	278
	279	/*
	280	* Initialize a new pgd / pmd table with invalid pointers.
	281	*/
	282	extern void pgd_init(unsigned long page);
	283	extern void pmd_init(unsigned long page, unsigned long pagetable);
	284
	285	/*
5ae03b12 DD	286	* Non-present pages: high 40 bits are offset, next 8 bits type,
5ae03b12 DD	287	* low 16 bits zero.
1da177e4 LT	288	*/
1da177e4 LT	289	static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
5ae03b12	290	{ pte_t pte; pte_val(pte) = (type << 16) \| (offset << 24); return pte; }
1da177e4	291
5ae03b12 DD	292	#define __swp_type(x) (((x).val >> 16) & 0xff)
5ae03b12 DD	293	#define __swp_offset(x) ((x).val >> 24)
21a151d8	294	#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
70342287	295	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1da177e4 LT	296	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1da177e4 LT	297
1da177e4	298	#endif /* _ASM_PGTABLE_64_H */