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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 2002 by Ralf Baechle | |
7 | * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. | |
8 | * Copyright (C) 2002 Maciej W. Rozycki | |
9 | */ | |
10 | #ifndef _ASM_PGTABLE_BITS_H | |
11 | #define _ASM_PGTABLE_BITS_H | |
12 | ||
1da177e4 LT |
13 | |
14 | /* | |
15 | * Note that we shift the lower 32bits of each EntryLo[01] entry | |
16 | * 6 bits to the left. That way we can convert the PFN into the | |
17 | * physical address by a single 'and' operation and gain 6 additional | |
18 | * bits for storing information which isn't present in a normal | |
19 | * MIPS page table. | |
20 | * | |
21 | * Similar to the Alpha port, we need to keep track of the ref | |
22 | * and mod bits in software. We have a software "yeah you can read | |
23 | * from this page" bit, and a hardware one which actually lets the | |
70342287 | 24 | * process read from the page. On the same token we have a software |
1da177e4 LT |
25 | * writable bit and the real hardware one which actually lets the |
26 | * process write to the page, this keeps a mod bit via the hardware | |
27 | * dirty bit. | |
28 | * | |
29 | * Certain revisions of the R4000 and R5000 have a bug where if a | |
30 | * certain sequence occurs in the last 3 instructions of an executable | |
31 | * page, and the following page is not mapped, the cpu can do | |
32 | * unpredictable things. The code (when it is written) to deal with | |
33 | * this problem will be in the update_mmu_cache() code for the r4k. | |
34 | */ | |
34adb28d | 35 | #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) |
1da177e4 | 36 | |
a2c763e0 | 37 | /* |
05f9883a | 38 | * The following bits are implemented by the TLB hardware |
a2c763e0 | 39 | */ |
c5b36783 SH |
40 | #define _PAGE_NO_EXEC_SHIFT 0 |
41 | #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) | |
42 | #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) | |
43 | #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) | |
44 | #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) | |
77a5c593 SH |
45 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) |
46 | #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) | |
a2c763e0 | 47 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) |
77a5c593 SH |
48 | #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) |
49 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) | |
50 | #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) | |
51 | #define _CACHE_MASK (7 << _CACHE_SHIFT) | |
a2c763e0 RB |
52 | |
53 | /* | |
54 | * The following bits are implemented in software | |
82de378c | 55 | */ |
c5b36783 | 56 | #define _PAGE_PRESENT_SHIFT (24) |
a2c763e0 | 57 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) |
77a5c593 | 58 | #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) |
a2c763e0 | 59 | #define _PAGE_READ (1 << _PAGE_READ_SHIFT) |
77a5c593 | 60 | #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) |
a2c763e0 | 61 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) |
77a5c593 | 62 | #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) |
a2c763e0 | 63 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) |
77a5c593 | 64 | #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) |
a2c763e0 | 65 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) |
1da177e4 | 66 | |
77a5c593 | 67 | #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) |
1da177e4 | 68 | |
c5b36783 SH |
69 | /* |
70 | * Bits for extended EntryLo0/EntryLo1 registers | |
71 | */ | |
72 | #define _PFNX_MASK 0xffffff | |
73 | ||
6dd9344c | 74 | #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
1da177e4 | 75 | |
a2c763e0 | 76 | /* |
05f9883a | 77 | * The following bits are implemented in software |
a2c763e0 | 78 | */ |
05f9883a SH |
79 | #define _PAGE_PRESENT_SHIFT (0) |
80 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) | |
81 | #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) | |
82 | #define _PAGE_READ (1 << _PAGE_READ_SHIFT) | |
83 | #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) | |
84 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) | |
85 | #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) | |
86 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) | |
87 | #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) | |
88 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) | |
1da177e4 | 89 | |
a2c763e0 | 90 | /* |
05f9883a | 91 | * The following bits are implemented by the TLB hardware |
a2c763e0 | 92 | */ |
05f9883a SH |
93 | #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) |
94 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) | |
95 | #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) | |
96 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) | |
97 | #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) | |
a2c763e0 | 98 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) |
05f9883a | 99 | #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) |
a2c763e0 | 100 | #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) |
05f9883a | 101 | #define _CACHE_MASK _CACHE_UNCACHED |
1da177e4 | 102 | |
05f9883a | 103 | #define _PFN_SHIFT PAGE_SHIFT |
1da177e4 | 104 | |
05f9883a | 105 | #else |
6dd9344c | 106 | /* |
be0c37c9 | 107 | * Below are the "Normal" R4K cases |
6dd9344c DD |
108 | */ |
109 | ||
a2c763e0 RB |
110 | /* |
111 | * The following bits are implemented in software | |
a2c763e0 | 112 | */ |
05f9883a | 113 | #define _PAGE_PRESENT_SHIFT 0 |
6dd9344c | 114 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) |
be0c37c9 | 115 | /* R2 or later cores check for RI/XI support to determine _PAGE_READ */ |
d7b63141 | 116 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
be0c37c9 SH |
117 | #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) |
118 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) | |
119 | #else | |
120 | #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) | |
121 | #define _PAGE_READ (1 << _PAGE_READ_SHIFT) | |
6dd9344c DD |
122 | #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) |
123 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) | |
be0c37c9 | 124 | #endif |
6dd9344c DD |
125 | #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) |
126 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) | |
6dd9344c DD |
127 | #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) |
128 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) | |
6dd9344c | 129 | |
be0c37c9 SH |
130 | #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) |
131 | /* Huge TLB page */ | |
6dd9344c DD |
132 | #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
133 | #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) | |
be0c37c9 | 134 | #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
970d032f | 135 | |
d7b63141 | 136 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
be0c37c9 | 137 | /* XI - page cannot be executed */ |
b2787370 KS |
138 | #ifdef _PAGE_HUGE_SHIFT |
139 | #define _PAGE_NO_EXEC_SHIFT (_PAGE_HUGE_SHIFT + 1) | |
1cfa8de2 | 140 | #else |
be0c37c9 SH |
141 | #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
142 | #endif | |
143 | #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) | |
6dd9344c | 144 | |
be0c37c9 SH |
145 | /* RI - page cannot be read */ |
146 | #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) | |
147 | #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) | |
148 | #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT | |
149 | #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) | |
1cfa8de2 | 150 | #endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ |
6dd9344c | 151 | |
1cfa8de2 | 152 | #if defined(_PAGE_NO_READ_SHIFT) |
6dd9344c | 153 | #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) |
b2787370 KS |
154 | #elif defined(_PAGE_HUGE_SHIFT) |
155 | #define _PAGE_GLOBAL_SHIFT (_PAGE_HUGE_SHIFT + 1) | |
1cfa8de2 | 156 | #else |
be0c37c9 | 157 | #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
1cfa8de2 | 158 | #endif |
be0c37c9 | 159 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) |
be0c37c9 | 160 | |
6dd9344c DD |
161 | #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) |
162 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) | |
6dd9344c DD |
163 | #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) |
164 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) | |
6dd9344c DD |
165 | #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) |
166 | #define _CACHE_MASK (7 << _CACHE_SHIFT) | |
167 | ||
168 | #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) | |
1da177e4 | 169 | |
34adb28d | 170 | #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ |
bec50527 | 171 | |
be0c37c9 SH |
172 | #ifndef _PAGE_NO_EXEC |
173 | #define _PAGE_NO_EXEC 0 | |
174 | #endif | |
175 | #ifndef _PAGE_NO_READ | |
176 | #define _PAGE_NO_READ 0 | |
177 | #endif | |
178 | ||
05f9883a SH |
179 | #define _PAGE_SILENT_READ _PAGE_VALID |
180 | #define _PAGE_SILENT_WRITE _PAGE_DIRTY | |
181 | ||
6dd9344c DD |
182 | #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) |
183 | ||
be0c37c9 SH |
184 | /* |
185 | * The final layouts of the PTE bits are: | |
186 | * | |
187 | * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P | |
188 | * 32-bit, R1 or earler: CCC D V G M A W R P | |
189 | * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P | |
190 | * 32-bit, R2 or later: CCC D V G RI/R XI M A W P | |
191 | */ | |
6dd9344c DD |
192 | |
193 | ||
194 | #ifndef __ASSEMBLY__ | |
195 | /* | |
196 | * pte_to_entrylo converts a page table entry (PTE) into a Mips | |
197 | * entrylo0/1 value. | |
198 | */ | |
199 | static inline uint64_t pte_to_entrylo(unsigned long pte_val) | |
200 | { | |
d7b63141 | 201 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
05857c64 | 202 | if (cpu_has_rixi) { |
6dd9344c DD |
203 | int sa; |
204 | #ifdef CONFIG_32BIT | |
205 | sa = 31 - _PAGE_NO_READ_SHIFT; | |
206 | #else | |
207 | sa = 63 - _PAGE_NO_READ_SHIFT; | |
208 | #endif | |
209 | /* | |
210 | * C has no way to express that this is a DSRL | |
211 | * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily | |
212 | * in the fast path this is done in assembly | |
213 | */ | |
214 | return (pte_val >> _PAGE_GLOBAL_SHIFT) | | |
215 | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); | |
216 | } | |
be0c37c9 | 217 | #endif |
6dd9344c DD |
218 | |
219 | return pte_val >> _PAGE_GLOBAL_SHIFT; | |
220 | } | |
221 | #endif | |
bec50527 CD |
222 | |
223 | /* | |
224 | * Cache attributes | |
225 | */ | |
226 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | |
227 | ||
228 | #define _CACHE_CACHABLE_NONCOHERENT 0 | |
fb020350 | 229 | #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED |
bec50527 CD |
230 | |
231 | #elif defined(CONFIG_CPU_SB1) | |
1da177e4 LT |
232 | |
233 | /* No penalty for being coherent on the SB1, so just | |
234 | use it for "noncoherent" spaces, too. Shouldn't hurt. */ | |
235 | ||
bec50527 | 236 | #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) |
1da177e4 | 237 | |
152ebb44 HC |
238 | #elif defined(CONFIG_CPU_LOONGSON3) |
239 | ||
240 | /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ | |
241 | ||
152ebb44 HC |
242 | #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ |
243 | #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ | |
152ebb44 | 244 | |
f1f5e414 | 245 | #elif defined(CONFIG_MACH_INGENIC) |
80bc94d1 MC |
246 | |
247 | /* Ingenic uses the WA bit to achieve write-combine memory writes */ | |
248 | #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) | |
249 | ||
fb020350 | 250 | #endif |
1da177e4 | 251 | |
fb020350 MC |
252 | #ifndef _CACHE_CACHABLE_NO_WA |
253 | #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) | |
254 | #endif | |
255 | #ifndef _CACHE_CACHABLE_WA | |
256 | #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) | |
257 | #endif | |
258 | #ifndef _CACHE_UNCACHED | |
259 | #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) | |
260 | #endif | |
261 | #ifndef _CACHE_CACHABLE_NONCOHERENT | |
262 | #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) | |
263 | #endif | |
264 | #ifndef _CACHE_CACHABLE_CE | |
265 | #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) | |
266 | #endif | |
267 | #ifndef _CACHE_CACHABLE_COW | |
268 | #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) | |
269 | #endif | |
270 | #ifndef _CACHE_CACHABLE_CUW | |
271 | #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) | |
272 | #endif | |
273 | #ifndef _CACHE_UNCACHED_ACCELERATED | |
274 | #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) | |
1da177e4 | 275 | #endif |
1da177e4 | 276 | |
be0c37c9 | 277 | #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) |
05f9883a | 278 | #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) |
1da177e4 | 279 | |
05f9883a SH |
280 | #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ |
281 | _PFN_MASK | _CACHE_MASK) | |
1da177e4 | 282 | |
1da177e4 | 283 | #endif /* _ASM_PGTABLE_BITS_H */ |