projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Copyright (C) 2001, 2002, MontaVista Software Inc. | |
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
| 4 | * Copyright (c) 2003 Maciej W. Rozycki | |
| 5 | * | |
| 6 | * include/asm-mips/time.h | |
| 7 | * header file for the new style time.c file and time services. | |
| 8 | * | |
| 70342287 RB |
9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the | |
| 1da177e4 LT |
11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. | |
| 1da177e4 LT |
13 | */ |
| 14 | #ifndef _ASM_TIME_H | |
| 15 | #define _ASM_TIME_H | |
| 16 | ||
| 1da177e4 | 17 | #include <linux/rtc.h> |
| 53c2df2f | 18 | #include <linux/spinlock.h> |
| 93c846f9 | 19 | #include <linux/clockchips.h> |
| 00598560 | 20 | #include <linux/clocksource.h> |
| 53c2df2f AN |
21 | |
| 22 | extern spinlock_t rtc_lock; | |
| 1da177e4 LT |
23 | |
| 24 | /* | |
| 4b550488 | 25 | * RTC ops. By default, they point to weak no-op RTC functions. |
| d23ee8fe YY |
26 | * rtc_mips_set_time - reverse the above translation and set time to RTC. |
| 27 | * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need | |
| 1da177e4 LT |
28 | * to be set. Used by RTC sync-up. |
| 29 | */ | |
| 4b550488 RB |
30 | extern int rtc_mips_set_time(unsigned long); |
| 31 | extern int rtc_mips_set_mmss(unsigned long); | |
| 1da177e4 | 32 | |
| 1da177e4 LT |
33 | /* |
| 34 | * board specific routines required by time_init(). | |
| 1da177e4 | 35 | */ |
| 4b550488 | 36 | extern void plat_time_init(void); |
| 1da177e4 LT |
37 | |
| 38 | /* | |
| 39 | * mips_hpt_frequency - must be set if you intend to use an R4k-compatible | |
| c9662341 | 40 | * counter as a timer interrupt source. |
| 1da177e4 LT |
41 | */ |
| 42 | extern unsigned int mips_hpt_frequency; | |
| 43 | ||
| 91a2fcc8 RB |
44 | /* |
| 45 | * The performance counter IRQ on MIPS is a close relative to the timer IRQ | |
| 46 | * so it lives here. | |
| 47 | */ | |
| 48 | extern int (*perf_irq)(void); | |
| 49 | ||
| 7bcf7717 RB |
50 | /* |
| 51 | * Initialize the calling CPU's compare interrupt as clockevent device | |
| 52 | */ | |
| 38760d40 | 53 | extern unsigned int __weak get_c0_compare_int(void); |
| 779e7d41 | 54 | extern int r4k_clockevent_init(void); |
| 0ab2b7d0 | 55 | extern int gic_clockevent_init(void); |
| 779e7d41 | 56 | |
| 5aa85c9f | 57 | static inline int mips_clockevent_init(void) |
| 42f77542 | 58 | { |
| b633648c | 59 | #if defined(CONFIG_CEVT_GIC) |
| 0ab2b7d0 | 60 | return (gic_clockevent_init() | r4k_clockevent_init()); |
| 592e527f | 61 | #elif defined(CONFIG_CEVT_R4K) |
| 779e7d41 ML |
62 | return r4k_clockevent_init(); |
| 63 | #else | |
| 5aa85c9f | 64 | return -ENXIO; |
| 42f77542 | 65 | #endif |
| 779e7d41 | 66 | } |
| 7bcf7717 | 67 | |
| 940f6b48 RB |
68 | /* |
| 69 | * Initialize the count register as a clocksource | |
| 70 | */ | |
| 779e7d41 | 71 | extern int init_r4k_clocksource(void); |
| 779e7d41 | 72 | |
| 69e634f1 | 73 | static inline int init_mips_clocksource(void) |
| 940f6b48 | 74 | { |
| f7886e87 | 75 | #ifdef CONFIG_CSRC_R4K |
| 779e7d41 ML |
76 | return init_r4k_clocksource(); |
| 77 | #else | |
| 69e634f1 | 78 | return 0; |
| 940f6b48 | 79 | #endif |
| 779e7d41 | 80 | } |
| 940f6b48 | 81 | |
| e3a4fab0 TG |
82 | static inline void clockevent_set_clock(struct clock_event_device *cd, |
| 83 | unsigned int clock) | |
| 84 | { | |
| 85 | clockevents_calc_mult_shift(cd, clock, 4); | |
| 86 | } | |
| 93c846f9 | 87 | |
| 1da177e4 | 88 | #endif /* _ASM_TIME_H */ |