[deliverable/linux.git] / arch / mips / include / asm / timex.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
 * Copyright (C) 2014 by Maciej W. Rozycki
 */
#ifndef _ASM_TIMEX_H
#define _ASM_TIMEX_H

#ifdef __KERNEL__

#include <linux/compiler.h>

#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/mipsregs.h>
#include <asm/cpu-type.h>

/*
 * This is the clock rate of the i8253 PIT.  A MIPS system may not have
 * a PIT by the symbol is used all over the kernel including some APIs.
 * So keeping it defined to the number for the PIT is the only sane thing
 * for now.
 */
#define CLOCK_TICK_RATE 1193182

/*
 * Standard way to access the cycle counter.
 * Currently only used on SMP for scheduling.
 *
 * Only the low 32 bits are available as a continuously counting entity.
 * But this only means we'll force a reschedule every 8 seconds or so,
 * which isn't an evil thing.
 *
 * We know that all SMP capable CPUs have cycle counters.
 */

typedef unsigned int cycles_t;

/*
 * On R4000/R4400 before version 5.0 an erratum exists such that if the
 * cycle counter is read in the exact moment that it is matching the
 * compare register, no interrupt will be generated.
 *
 * There is a suggested workaround and also the erratum can't strike if
 * the compare interrupt isn't being used as the clock source device.
 * However for now the implementaton of this function doesn't get these
 * fine details right.
 */
static inline int can_use_mips_counter(unsigned int prid)
{
	int comp = (prid & PRID_COMP_MASK) != PRID_COMP_LEGACY;

	if (__builtin_constant_p(cpu_has_counter) && !cpu_has_counter)
		return 0;
	else if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r)
		return 1;
	else if (likely(!__builtin_constant_p(cpu_has_mips_r) && comp))
		return 1;
	/* Make sure we don't peek at cpu_data[0].options in the fast path! */
	if (!__builtin_constant_p(cpu_has_counter))
		asm volatile("" : "=m" (cpu_data[0].options));
	if (likely(cpu_has_counter &&
		   prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0))))
		return 1;
	else
		return 0;
}

static inline cycles_t get_cycles(void)
{
	if (can_use_mips_counter(read_c0_prid()))
		return read_c0_count();
	else
		return 0;	/* no usable counter */
}

/*
 * Like get_cycles - but where c0_count is not available we desperately
 * use c0_random in an attempt to get at least a little bit of entropy.
 *
 * R6000 and R6000A neither have a count register nor a random register.
 * That leaves no entropy source in the CPU itself.
 */
static inline unsigned long random_get_entropy(void)
{
	unsigned int prid = read_c0_prid();
	unsigned int imp = prid & PRID_IMP_MASK;

	if (can_use_mips_counter(prid))
		return read_c0_count();
	else if (likely(imp != PRID_IMP_R6000 && imp != PRID_IMP_R6000A))
		return read_c0_random();
	else
		return 0;	/* no usable register */
}
#define random_get_entropy random_get_entropy

#endif /* __KERNEL__ */

#endif /*  _ASM_TIMEX_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1998, 1999, 2003 by Ralf Baechle
06947aaa	7	* Copyright (C) 2014 by Maciej W. Rozycki
1da177e4 LT	8	*/
	9	#ifndef _ASM_TIMEX_H
	10	#define _ASM_TIMEX_H
	11
8f9a2b32 AN	12	#ifdef __KERNEL__
8f9a2b32 AN	13
06947aaa MR	14	#include <linux/compiler.h>
	15
	16	#include <asm/cpu.h>
9c9b415c	17	#include <asm/cpu-features.h>
1da177e4	18	#include <asm/mipsregs.h>
9c9b415c	19	#include <asm/cpu-type.h>
1da177e4 LT	20
1da177e4 LT	21	/*
72fc19ff RB	22	* This is the clock rate of the i8253 PIT. A MIPS system may not have
	23	* a PIT by the symbol is used all over the kernel including some APIs.
	24	* So keeping it defined to the number for the PIT is the only sane thing
	25	* for now.
1da177e4	26	*/
72fc19ff	27	#define CLOCK_TICK_RATE 1193182
1da177e4 LT	28
	29	/*
	30	* Standard way to access the cycle counter.
	31	* Currently only used on SMP for scheduling.
	32	*
	33	* Only the low 32 bits are available as a continuously counting entity.
	34	* But this only means we'll force a reschedule every 8 seconds or so,
	35	* which isn't an evil thing.
	36	*
	37	* We know that all SMP capable CPUs have cycle counters.
	38	*/
	39
	40	typedef unsigned int cycles_t;
	41
9c9b415c RB	42	/*
	43	* On R4000/R4400 before version 5.0 an erratum exists such that if the
	44	* cycle counter is read in the exact moment that it is matching the
	45	* compare register, no interrupt will be generated.
	46	*
	47	* There is a suggested workaround and also the erratum can't strike if
	48	* the compare interrupt isn't being used as the clock source device.
	49	* However for now the implementaton of this function doesn't get these
	50	* fine details right.
	51	*/
06947aaa	52	static inline int can_use_mips_counter(unsigned int prid)
1da177e4	53	{
06947aaa	54	int comp = (prid & PRID_COMP_MASK) != PRID_COMP_LEGACY;
9c9b415c	55
06947aaa MR	56	if (__builtin_constant_p(cpu_has_counter) && !cpu_has_counter)
	57	return 0;
	58	else if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r)
	59	return 1;
	60	else if (likely(!__builtin_constant_p(cpu_has_mips_r) && comp))
	61	return 1;
	62	/* Make sure we don't peek at cpu_data[0].options in the fast path! */
	63	if (!__builtin_constant_p(cpu_has_counter))
	64	asm volatile("" : "=m" (cpu_data[0].options));
	65	if (likely(cpu_has_counter &&
	66	prid >= (PRID_IMP_R4000 \| PRID_REV_ENCODE_44(5, 0))))
	67	return 1;
	68	else
	69	return 0;
	70	}
9c9b415c	71
06947aaa MR	72	static inline cycles_t get_cycles(void)
	73	{
	74	if (can_use_mips_counter(read_c0_prid()))
	75	return read_c0_count();
	76	else
	77	return 0; /* no usable counter */
	78	}
	79
	80	/*
	81	* Like get_cycles - but where c0_count is not available we desperately
	82	* use c0_random in an attempt to get at least a little bit of entropy.
	83	*
	84	* R6000 and R6000A neither have a count register nor a random register.
	85	* That leaves no entropy source in the CPU itself.
	86	*/
	87	static inline unsigned long random_get_entropy(void)
	88	{
	89	unsigned int prid = read_c0_prid();
	90	unsigned int imp = prid & PRID_IMP_MASK;
9c9b415c	91
06947aaa MR	92	if (can_use_mips_counter(prid))
	93	return read_c0_count();
	94	else if (likely(imp != PRID_IMP_R6000 && imp != PRID_IMP_R6000A))
	95	return read_c0_random();
	96	else
	97	return 0; /* no usable register */
1da177e4	98	}
06947aaa	99	#define random_get_entropy random_get_entropy
1da177e4	100
8f9a2b32 AN	101	#endif /* __KERNEL__ */
8f9a2b32 AN	102
1da177e4	103	#endif /* _ASM_TIMEX_H */