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1da177e4 LT |
1 | /* |
2 | * include/asm-mips/vr41xx/vr41xx.h | |
3 | * | |
4 | * Include file for NEC VR4100 series. | |
5 | * | |
6 | * Copyright (C) 1999 Michael Klar | |
7 | * Copyright (C) 2001, 2002 Paul Mundt | |
8 | * Copyright (C) 2002 MontaVista Software, Inc. | |
9 | * Copyright (C) 2002 TimeSys Corp. | |
ada8e951 | 10 | * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org> |
1da177e4 LT |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
17 | #ifndef __NEC_VR41XX_H | |
18 | #define __NEC_VR41XX_H | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | ||
22 | /* | |
23 | * CPU Revision | |
24 | */ | |
25 | /* VR4122 0x00000c70-0x00000c72 */ | |
26 | #define PRID_VR4122_REV1_0 0x00000c70 | |
27 | #define PRID_VR4122_REV2_0 0x00000c70 | |
28 | #define PRID_VR4122_REV2_1 0x00000c70 | |
29 | #define PRID_VR4122_REV3_0 0x00000c71 | |
30 | #define PRID_VR4122_REV3_1 0x00000c72 | |
31 | ||
32 | /* VR4181A 0x00000c73-0x00000c7f */ | |
33 | #define PRID_VR4181A_REV1_0 0x00000c73 | |
34 | #define PRID_VR4181A_REV1_1 0x00000c74 | |
35 | ||
36 | /* VR4131 0x00000c80-0x00000c83 */ | |
37 | #define PRID_VR4131_REV1_2 0x00000c80 | |
38 | #define PRID_VR4131_REV2_0 0x00000c81 | |
39 | #define PRID_VR4131_REV2_1 0x00000c82 | |
40 | #define PRID_VR4131_REV2_2 0x00000c83 | |
41 | ||
42 | /* VR4133 0x00000c84- */ | |
43 | #define PRID_VR4133 0x00000c84 | |
44 | ||
45 | /* | |
46 | * Bus Control Uint | |
47 | */ | |
48 | extern unsigned long vr41xx_calculate_clock_frequency(void); | |
49 | extern unsigned long vr41xx_get_vtclock_frequency(void); | |
50 | extern unsigned long vr41xx_get_tclock_frequency(void); | |
51 | ||
52 | /* | |
53 | * Clock Mask Unit | |
54 | */ | |
55 | typedef enum { | |
56 | PIU_CLOCK, | |
57 | SIU_CLOCK, | |
58 | AIU_CLOCK, | |
59 | KIU_CLOCK, | |
60 | FIR_CLOCK, | |
61 | DSIU_CLOCK, | |
62 | CSI_CLOCK, | |
63 | PCIU_CLOCK, | |
64 | HSP_CLOCK, | |
65 | PCI_CLOCK, | |
66 | CEU_CLOCK, | |
67 | ETHER0_CLOCK, | |
68 | ETHER1_CLOCK | |
69 | } vr41xx_clock_t; | |
70 | ||
71 | extern void vr41xx_supply_clock(vr41xx_clock_t clock); | |
72 | extern void vr41xx_mask_clock(vr41xx_clock_t clock); | |
73 | ||
74 | /* | |
75 | * Interrupt Control Unit | |
76 | */ | |
1da177e4 | 77 | extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); |
94399ea6 | 78 | extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int)); |
1da177e4 LT |
79 | |
80 | #define PIUINT_COMMAND 0x0040 | |
81 | #define PIUINT_DATA 0x0020 | |
82 | #define PIUINT_PAGE1 0x0010 | |
83 | #define PIUINT_PAGE0 0x0008 | |
84 | #define PIUINT_DATALOST 0x0004 | |
85 | #define PIUINT_STATUSCHANGE 0x0001 | |
86 | ||
87 | extern void vr41xx_enable_piuint(uint16_t mask); | |
88 | extern void vr41xx_disable_piuint(uint16_t mask); | |
89 | ||
90 | #define AIUINT_INPUT_DMAEND 0x0800 | |
91 | #define AIUINT_INPUT_DMAHALT 0x0400 | |
92 | #define AIUINT_INPUT_DATALOST 0x0200 | |
93 | #define AIUINT_INPUT_DATA 0x0100 | |
94 | #define AIUINT_OUTPUT_DMAEND 0x0008 | |
95 | #define AIUINT_OUTPUT_DMAHALT 0x0004 | |
96 | #define AIUINT_OUTPUT_NODATA 0x0002 | |
97 | ||
98 | extern void vr41xx_enable_aiuint(uint16_t mask); | |
99 | extern void vr41xx_disable_aiuint(uint16_t mask); | |
100 | ||
101 | #define KIUINT_DATALOST 0x0004 | |
102 | #define KIUINT_DATAREADY 0x0002 | |
103 | #define KIUINT_SCAN 0x0001 | |
104 | ||
105 | extern void vr41xx_enable_kiuint(uint16_t mask); | |
106 | extern void vr41xx_disable_kiuint(uint16_t mask); | |
107 | ||
108 | #define DSIUINT_CTS 0x0800 | |
109 | #define DSIUINT_RXERR 0x0400 | |
110 | #define DSIUINT_RX 0x0200 | |
111 | #define DSIUINT_TX 0x0100 | |
112 | #define DSIUINT_ALL 0x0f00 | |
113 | ||
114 | extern void vr41xx_enable_dsiuint(uint16_t mask); | |
115 | extern void vr41xx_disable_dsiuint(uint16_t mask); | |
116 | ||
117 | #define FIRINT_UNIT 0x0010 | |
118 | #define FIRINT_RX_DMAEND 0x0008 | |
119 | #define FIRINT_RX_DMAHALT 0x0004 | |
120 | #define FIRINT_TX_DMAEND 0x0002 | |
121 | #define FIRINT_TX_DMAHALT 0x0001 | |
122 | ||
123 | extern void vr41xx_enable_firint(uint16_t mask); | |
124 | extern void vr41xx_disable_firint(uint16_t mask); | |
125 | ||
126 | extern void vr41xx_enable_pciint(void); | |
127 | extern void vr41xx_disable_pciint(void); | |
128 | ||
129 | extern void vr41xx_enable_scuint(void); | |
130 | extern void vr41xx_disable_scuint(void); | |
131 | ||
132 | #define CSIINT_TX_DMAEND 0x0040 | |
133 | #define CSIINT_TX_DMAHALT 0x0020 | |
134 | #define CSIINT_TX_DATA 0x0010 | |
135 | #define CSIINT_TX_FIFOEMPTY 0x0008 | |
136 | #define CSIINT_RX_DMAEND 0x0004 | |
137 | #define CSIINT_RX_DMAHALT 0x0002 | |
138 | #define CSIINT_RX_FIFOEMPTY 0x0001 | |
139 | ||
140 | extern void vr41xx_enable_csiint(uint16_t mask); | |
141 | extern void vr41xx_disable_csiint(uint16_t mask); | |
142 | ||
143 | extern void vr41xx_enable_bcuint(void); | |
144 | extern void vr41xx_disable_bcuint(void); | |
145 | ||
fc3f341b YY |
146 | #ifdef CONFIG_SERIAL_VR41XX_CONSOLE |
147 | extern void vr41xx_siu_setup(void); | |
148 | #else | |
149 | static inline void vr41xx_siu_setup(void) {} | |
150 | #endif | |
151 | ||
1da177e4 | 152 | #endif /* __NEC_VR41XX_H */ |