Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <asm/asm.h> |
2 | #include <asm/mipsregs.h> | |
3 | #include <asm/regdef.h> | |
4 | #include <asm/stackframe.h> | |
5 | ||
6 | .text | |
7 | .set macro | |
8 | .set noat | |
9 | .align 5 | |
10 | ||
11 | NESTED(it8172_IRQ, PT_SIZE, sp) | |
12 | SAVE_ALL | |
13 | CLI # Important: mark KERNEL mode ! | |
14 | ||
15 | /* We're working with 'reorder' set at this point. */ | |
16 | /* | |
17 | * Get pending interrupts | |
18 | */ | |
19 | ||
20 | mfc0 t0,CP0_CAUSE # get pending interrupts | |
21 | mfc0 t1,CP0_STATUS # get enabled interrupts | |
22 | and t0,t1 # isolate allowed ones | |
23 | ||
24 | andi t0,0xff00 # isolate pending bits | |
25 | beqz t0, 3f # spurious interrupt | |
26 | ||
27 | andi a0, t0, CAUSEF_IP7 | |
28 | beq a0, zero, 1f | |
29 | ||
30 | li a0, 127 # MIPS_CPU_TIMER_IRQ = (NR_IRQS-1) | |
31 | move a1, sp | |
32 | jal ll_timer_interrupt | |
33 | j ret_from_irq | |
34 | nop | |
35 | ||
36 | 1: | |
37 | andi a0, t0, CAUSEF_IP2 # the only int we expect at this time | |
38 | beq a0, zero, 3f | |
39 | move a0,sp | |
40 | jal it8172_hw0_irqdispatch | |
41 | ||
42 | mfc0 t0,CP0_STATUS # disable interrupts | |
43 | ori t0,1 | |
44 | xori t0,1 | |
45 | mtc0 t0,CP0_STATUS | |
46 | nop | |
47 | nop | |
48 | nop | |
49 | ||
50 | la a1, ret_from_irq | |
51 | jr a1 | |
52 | nop | |
53 | ||
54 | 3: | |
55 | move a0, sp | |
56 | jal mips_spurious_interrupt | |
57 | nop | |
58 | la a1, ret_from_irq | |
59 | jr a1 | |
60 | nop | |
61 | ||
62 | END(it8172_IRQ) | |
63 |