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Merge tag 'yama-4.0' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux...
[deliverable/linux.git] / arch / mips / kernel / asm-offsets.c
CommitLineData
1da177e4
LT		 1/*
2 * offset.c: Calculate pt_regs and task_struct offsets.
3 *
4 * Copyright (C) 1996 David S. Miller
5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 *
8 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */
1da177e4
LT		 11#include <linux/compat.h>
12#include <linux/types.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
fd04d206 15#include <linux/kbuild.h>
363c55ca 16#include <linux/suspend.h>
74e91335 17#include <asm/pm.h>
1da177e4
LT		 18#include <asm/ptrace.h>
19#include <asm/processor.h>
0ee958e1 20#include <asm/smp-cps.h>
1da177e4 21
12e25f8e
SL		 22#include <linux/kvm_host.h>
23
1da177e4
LT		 24void output_ptreg_defines(void)
25{
fd04d206
CL		 26 COMMENT("MIPS pt_regs offsets.");
27 OFFSET(PT_R0, pt_regs, regs[0]);
28 OFFSET(PT_R1, pt_regs, regs[1]);
29 OFFSET(PT_R2, pt_regs, regs[2]);
30 OFFSET(PT_R3, pt_regs, regs[3]);
31 OFFSET(PT_R4, pt_regs, regs[4]);
32 OFFSET(PT_R5, pt_regs, regs[5]);
33 OFFSET(PT_R6, pt_regs, regs[6]);
34 OFFSET(PT_R7, pt_regs, regs[7]);
35 OFFSET(PT_R8, pt_regs, regs[8]);
36 OFFSET(PT_R9, pt_regs, regs[9]);
37 OFFSET(PT_R10, pt_regs, regs[10]);
38 OFFSET(PT_R11, pt_regs, regs[11]);
39 OFFSET(PT_R12, pt_regs, regs[12]);
40 OFFSET(PT_R13, pt_regs, regs[13]);
41 OFFSET(PT_R14, pt_regs, regs[14]);
42 OFFSET(PT_R15, pt_regs, regs[15]);
43 OFFSET(PT_R16, pt_regs, regs[16]);
44 OFFSET(PT_R17, pt_regs, regs[17]);
45 OFFSET(PT_R18, pt_regs, regs[18]);
46 OFFSET(PT_R19, pt_regs, regs[19]);
47 OFFSET(PT_R20, pt_regs, regs[20]);
48 OFFSET(PT_R21, pt_regs, regs[21]);
49 OFFSET(PT_R22, pt_regs, regs[22]);
50 OFFSET(PT_R23, pt_regs, regs[23]);
51 OFFSET(PT_R24, pt_regs, regs[24]);
52 OFFSET(PT_R25, pt_regs, regs[25]);
53 OFFSET(PT_R26, pt_regs, regs[26]);
54 OFFSET(PT_R27, pt_regs, regs[27]);
55 OFFSET(PT_R28, pt_regs, regs[28]);
56 OFFSET(PT_R29, pt_regs, regs[29]);
57 OFFSET(PT_R30, pt_regs, regs[30]);
58 OFFSET(PT_R31, pt_regs, regs[31]);
59 OFFSET(PT_LO, pt_regs, lo);
60 OFFSET(PT_HI, pt_regs, hi);
9693a853 61#ifdef CONFIG_CPU_HAS_SMARTMIPS
fd04d206 62 OFFSET(PT_ACX, pt_regs, acx);
9693a853 63#endif
fd04d206
CL		 64 OFFSET(PT_EPC, pt_regs, cp0_epc);
65 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
66 OFFSET(PT_STATUS, pt_regs, cp0_status);
67 OFFSET(PT_CAUSE, pt_regs, cp0_cause);
babed555
DD		 68#ifdef CONFIG_CPU_CAVIUM_OCTEON
69 OFFSET(PT_MPL, pt_regs, mpl);
70 OFFSET(PT_MTP, pt_regs, mtp);
71#endif /* CONFIG_CPU_CAVIUM_OCTEON */
fd04d206
CL		 72 DEFINE(PT_SIZE, sizeof(struct pt_regs));
73 BLANK();
1da177e4
LT		 74}
75
76void output_task_defines(void)
77{
fd04d206
CL		 78 COMMENT("MIPS task_struct offsets.");
79 OFFSET(TASK_STATE, task_struct, state);
80 OFFSET(TASK_THREAD_INFO, task_struct, stack);
81 OFFSET(TASK_FLAGS, task_struct, flags);
82 OFFSET(TASK_MM, task_struct, mm);
83 OFFSET(TASK_PID, task_struct, pid);
1400eb65
GF		 84#if defined(CONFIG_CC_STACKPROTECTOR)
85 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
86#endif
fd04d206
CL		 87 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
88 BLANK();
1da177e4
LT		 89}
90
91void output_thread_info_defines(void)
92{
fd04d206
CL		 93 COMMENT("MIPS thread_info offsets.");
94 OFFSET(TI_TASK, thread_info, task);
95 OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain);
96 OFFSET(TI_FLAGS, thread_info, flags);
97 OFFSET(TI_TP_VALUE, thread_info, tp_value);
98 OFFSET(TI_CPU, thread_info, cpu);
99 OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
7c151d3d 100 OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return);
fd04d206 101 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
fd04d206
CL		 102 OFFSET(TI_REGS, thread_info, regs);
103 DEFINE(_THREAD_SIZE, THREAD_SIZE);
104 DEFINE(_THREAD_MASK, THREAD_MASK);
105 BLANK();
1da177e4
LT		 106}
107
108void output_thread_defines(void)
109{
fd04d206
CL		 110 COMMENT("MIPS specific thread_struct offsets.");
111 OFFSET(THREAD_REG16, task_struct, thread.reg16);
112 OFFSET(THREAD_REG17, task_struct, thread.reg17);
113 OFFSET(THREAD_REG18, task_struct, thread.reg18);
114 OFFSET(THREAD_REG19, task_struct, thread.reg19);
115 OFFSET(THREAD_REG20, task_struct, thread.reg20);
116 OFFSET(THREAD_REG21, task_struct, thread.reg21);
117 OFFSET(THREAD_REG22, task_struct, thread.reg22);
118 OFFSET(THREAD_REG23, task_struct, thread.reg23);
119 OFFSET(THREAD_REG29, task_struct, thread.reg29);
120 OFFSET(THREAD_REG30, task_struct, thread.reg30);
121 OFFSET(THREAD_REG31, task_struct, thread.reg31);
122 OFFSET(THREAD_STATUS, task_struct,
1da177e4 123 thread.cp0_status);
fd04d206 124 OFFSET(THREAD_FPU, task_struct, thread.fpu);
1da177e4 125
fd04d206 126 OFFSET(THREAD_BVADDR, task_struct, \
1da177e4 127 thread.cp0_badvaddr);
fd04d206 128 OFFSET(THREAD_BUADDR, task_struct, \
1da177e4 129 thread.cp0_baduaddr);
fd04d206 130 OFFSET(THREAD_ECODE, task_struct, \
1da177e4 131 thread.error_code);
fd04d206 132 BLANK();
1da177e4
LT		 133}
134
135void output_thread_fpu_defines(void)
136{
fd04d206
CL		 137 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
138 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
139 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
140 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
141 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
142 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
143 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
144 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
145 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
146 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
147 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
148 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
149 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
150 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
151 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
152 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
153 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
154 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
155 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
156 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
157 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
158 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
159 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
160 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
161 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
162 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
163 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
164 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
165 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
166 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
167 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
168 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
1da177e4 169
02987633
PB		 170 /* the least significant 64 bits of each FP register */
171 OFFSET(THREAD_FPR0_LS64, task_struct,
172 thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
173 OFFSET(THREAD_FPR1_LS64, task_struct,
174 thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
175 OFFSET(THREAD_FPR2_LS64, task_struct,
176 thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
177 OFFSET(THREAD_FPR3_LS64, task_struct,
178 thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
179 OFFSET(THREAD_FPR4_LS64, task_struct,
180 thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
181 OFFSET(THREAD_FPR5_LS64, task_struct,
182 thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
183 OFFSET(THREAD_FPR6_LS64, task_struct,
184 thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
185 OFFSET(THREAD_FPR7_LS64, task_struct,
186 thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
187 OFFSET(THREAD_FPR8_LS64, task_struct,
188 thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
189 OFFSET(THREAD_FPR9_LS64, task_struct,
190 thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
191 OFFSET(THREAD_FPR10_LS64, task_struct,
192 thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
193 OFFSET(THREAD_FPR11_LS64, task_struct,
194 thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
195 OFFSET(THREAD_FPR12_LS64, task_struct,
196 thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
197 OFFSET(THREAD_FPR13_LS64, task_struct,
198 thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
199 OFFSET(THREAD_FPR14_LS64, task_struct,
200 thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
201 OFFSET(THREAD_FPR15_LS64, task_struct,
202 thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
203 OFFSET(THREAD_FPR16_LS64, task_struct,
204 thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
205 OFFSET(THREAD_FPR17_LS64, task_struct,
206 thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
207 OFFSET(THREAD_FPR18_LS64, task_struct,
208 thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
209 OFFSET(THREAD_FPR19_LS64, task_struct,
210 thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
211 OFFSET(THREAD_FPR20_LS64, task_struct,
212 thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
213 OFFSET(THREAD_FPR21_LS64, task_struct,
214 thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
215 OFFSET(THREAD_FPR22_LS64, task_struct,
216 thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
217 OFFSET(THREAD_FPR23_LS64, task_struct,
218 thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
219 OFFSET(THREAD_FPR24_LS64, task_struct,
220 thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
221 OFFSET(THREAD_FPR25_LS64, task_struct,
222 thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
223 OFFSET(THREAD_FPR26_LS64, task_struct,
224 thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
225 OFFSET(THREAD_FPR27_LS64, task_struct,
226 thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
227 OFFSET(THREAD_FPR28_LS64, task_struct,
228 thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
229 OFFSET(THREAD_FPR29_LS64, task_struct,
230 thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
231 OFFSET(THREAD_FPR30_LS64, task_struct,
232 thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
233 OFFSET(THREAD_FPR31_LS64, task_struct,
234 thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
235
fd04d206 236 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
f7a46fa7 237 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
fd04d206 238 BLANK();
1da177e4
LT		 239}
240
241void output_mm_defines(void)
242{
fd04d206
CL		 243 COMMENT("Size of struct page");
244 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
245 BLANK();
246 COMMENT("Linux mm_struct offsets.");
247 OFFSET(MM_USERS, mm_struct, mm_users);
248 OFFSET(MM_PGD, mm_struct, pgd);
249 OFFSET(MM_CONTEXT, mm_struct, context);
250 BLANK();
fd04d206
CL		 251 DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
252 DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
253 DEFINE(_PTE_T_SIZE, sizeof(pte_t));
254 BLANK();
255 DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
325f8a0a 256#ifndef __PAGETABLE_PMD_FOLDED
fd04d206 257 DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
325f8a0a 258#endif
fd04d206
CL		 259 DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
260 BLANK();
261 DEFINE(_PGD_ORDER, PGD_ORDER);
325f8a0a 262#ifndef __PAGETABLE_PMD_FOLDED
fd04d206 263 DEFINE(_PMD_ORDER, PMD_ORDER);
325f8a0a 264#endif
fd04d206
CL		 265 DEFINE(_PTE_ORDER, PTE_ORDER);
266 BLANK();
267 DEFINE(_PMD_SHIFT, PMD_SHIFT);
268 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
269 BLANK();
270 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
271 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
272 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
273 BLANK();
20082595
RB		 274 DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
275 DEFINE(_PAGE_SIZE, PAGE_SIZE);
276 BLANK();
1da177e4
LT		 277}
278
e50c0a8f 279#ifdef CONFIG_32BIT
1da177e4
LT		 280void output_sc_defines(void)
281{
fd04d206
CL		 282 COMMENT("Linux sigcontext offsets.");
283 OFFSET(SC_REGS, sigcontext, sc_regs);
284 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
285 OFFSET(SC_ACX, sigcontext, sc_acx);
286 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
287 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
288 OFFSET(SC_PC, sigcontext, sc_pc);
289 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
290 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
291 OFFSET(SC_HI1, sigcontext, sc_hi1);
292 OFFSET(SC_LO1, sigcontext, sc_lo1);
293 OFFSET(SC_HI2, sigcontext, sc_hi2);
294 OFFSET(SC_LO2, sigcontext, sc_lo2);
295 OFFSET(SC_HI3, sigcontext, sc_hi3);
296 OFFSET(SC_LO3, sigcontext, sc_lo3);
297 BLANK();
1da177e4 298}
e50c0a8f
RB		 299#endif
300
301#ifdef CONFIG_64BIT
302void output_sc_defines(void)
303{
fd04d206
CL		 304 COMMENT("Linux sigcontext offsets.");
305 OFFSET(SC_REGS, sigcontext, sc_regs);
306 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
307 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
308 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
309 OFFSET(SC_PC, sigcontext, sc_pc);
310 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
311 BLANK();
e50c0a8f
RB		 312}
313#endif
1da177e4
LT		 314
315#ifdef CONFIG_MIPS32_COMPAT
316void output_sc32_defines(void)
317{
fd04d206
CL		 318 COMMENT("Linux 32-bit sigcontext offsets.");
319 OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
320 OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
321 OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
322 BLANK();
1da177e4
LT		 323}
324#endif
325
326void output_signal_defined(void)
327{
fd04d206
CL		 328 COMMENT("Linux signal numbers.");
329 DEFINE(_SIGHUP, SIGHUP);
330 DEFINE(_SIGINT, SIGINT);
331 DEFINE(_SIGQUIT, SIGQUIT);
332 DEFINE(_SIGILL, SIGILL);
333 DEFINE(_SIGTRAP, SIGTRAP);
334 DEFINE(_SIGIOT, SIGIOT);
335 DEFINE(_SIGABRT, SIGABRT);
336 DEFINE(_SIGEMT, SIGEMT);
337 DEFINE(_SIGFPE, SIGFPE);
338 DEFINE(_SIGKILL, SIGKILL);
339 DEFINE(_SIGBUS, SIGBUS);
340 DEFINE(_SIGSEGV, SIGSEGV);
341 DEFINE(_SIGSYS, SIGSYS);
342 DEFINE(_SIGPIPE, SIGPIPE);
343 DEFINE(_SIGALRM, SIGALRM);
344 DEFINE(_SIGTERM, SIGTERM);
345 DEFINE(_SIGUSR1, SIGUSR1);
346 DEFINE(_SIGUSR2, SIGUSR2);
347 DEFINE(_SIGCHLD, SIGCHLD);
348 DEFINE(_SIGPWR, SIGPWR);
349 DEFINE(_SIGWINCH, SIGWINCH);
350 DEFINE(_SIGURG, SIGURG);
351 DEFINE(_SIGIO, SIGIO);
352 DEFINE(_SIGSTOP, SIGSTOP);
353 DEFINE(_SIGTSTP, SIGTSTP);
354 DEFINE(_SIGCONT, SIGCONT);
355 DEFINE(_SIGTTIN, SIGTTIN);
356 DEFINE(_SIGTTOU, SIGTTOU);
357 DEFINE(_SIGVTALRM, SIGVTALRM);
358 DEFINE(_SIGPROF, SIGPROF);
359 DEFINE(_SIGXCPU, SIGXCPU);
360 DEFINE(_SIGXFSZ, SIGXFSZ);
361 BLANK();
1da177e4
LT		 362}
363
babed555
DD		 364#ifdef CONFIG_CPU_CAVIUM_OCTEON
365void output_octeon_cop2_state_defines(void)
366{
367 COMMENT("Octeon specific octeon_cop2_state offsets.");
368 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
369 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
370 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
371 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
372 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
373 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
374 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
375 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
376 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
377 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
378 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
379 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
380 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
381 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
382 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
383 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
384 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
6b3a287e 385 OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
babed555
DD		 386 OFFSET(THREAD_CP2, task_struct, thread.cp2);
387 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
388 BLANK();
389}
390#endif
363c55ca
WZ		 391
392#ifdef CONFIG_HIBERNATION
393void output_pbe_defines(void)
394{
395 COMMENT(" Linux struct pbe offsets. ");
396 OFFSET(PBE_ADDRESS, pbe, address);
397 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
398 OFFSET(PBE_NEXT, pbe, next);
399 DEFINE(PBE_SIZE, sizeof(struct pbe));
400 BLANK();
401}
402#endif
12e25f8e 403
74e91335
JH		 404#ifdef CONFIG_CPU_PM
405void output_pm_defines(void)
406{
407 COMMENT(" PM offsets. ");
408#ifdef CONFIG_EVA
409 OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
410 OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
411 OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
412#endif
413 OFFSET(SSS_SP, mips_static_suspend_state, sp);
414 BLANK();
415}
416#endif
417
12e25f8e
SL		 418void output_kvm_defines(void)
419{
420 COMMENT(" KVM/MIPS Specfic offsets. ");
421 DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
422 OFFSET(VCPU_RUN, kvm_vcpu, run);
423 OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
424
425 OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
426 OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
427
428 OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
429 OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
430
431 OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
432 OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
433 OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
434 OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
435
436 OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
437
438 OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
439 OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
440 OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
441 OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
442 OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
443 OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
444 OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
445 OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
446 OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
447 OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
448 OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
449 OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
450 OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
451 OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
452 OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
453 OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
454 OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
455 OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
456 OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
457 OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
458 OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
459 OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
460 OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
461 OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
462 OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
463 OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
464 OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
465 OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
466 OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
467 OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
468 OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
469 OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
470 OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
471 OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
472 OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
473 OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
474 OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
475 OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
476
477 OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
478 OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
479 BLANK();
480}
0ee958e1
PB		 481
482#ifdef CONFIG_MIPS_CPS
483void output_cps_defines(void)
484{
485 COMMENT(" MIPS CPS offsets. ");
245a7868
PB		 486
487 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
488 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
489 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
490
491 OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
492 OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
493 OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
494 DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
0ee958e1
PB		 495}
496#endif
Linux kernel - Deliverables
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