Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * offset.c: Calculate pt_regs and task_struct offsets. | |
3 | * | |
4 | * Copyright (C) 1996 David S. Miller | |
5 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle | |
6 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
7 | * | |
8 | * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
9 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/compat.h> |
12 | #include <linux/types.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mm.h> | |
fd04d206 | 15 | #include <linux/kbuild.h> |
363c55ca | 16 | #include <linux/suspend.h> |
74e91335 | 17 | #include <asm/pm.h> |
1da177e4 LT |
18 | #include <asm/ptrace.h> |
19 | #include <asm/processor.h> | |
0ee958e1 | 20 | #include <asm/smp-cps.h> |
1da177e4 | 21 | |
12e25f8e SL |
22 | #include <linux/kvm_host.h> |
23 | ||
1da177e4 LT |
24 | void output_ptreg_defines(void) |
25 | { | |
fd04d206 CL |
26 | COMMENT("MIPS pt_regs offsets."); |
27 | OFFSET(PT_R0, pt_regs, regs[0]); | |
28 | OFFSET(PT_R1, pt_regs, regs[1]); | |
29 | OFFSET(PT_R2, pt_regs, regs[2]); | |
30 | OFFSET(PT_R3, pt_regs, regs[3]); | |
31 | OFFSET(PT_R4, pt_regs, regs[4]); | |
32 | OFFSET(PT_R5, pt_regs, regs[5]); | |
33 | OFFSET(PT_R6, pt_regs, regs[6]); | |
34 | OFFSET(PT_R7, pt_regs, regs[7]); | |
35 | OFFSET(PT_R8, pt_regs, regs[8]); | |
36 | OFFSET(PT_R9, pt_regs, regs[9]); | |
37 | OFFSET(PT_R10, pt_regs, regs[10]); | |
38 | OFFSET(PT_R11, pt_regs, regs[11]); | |
39 | OFFSET(PT_R12, pt_regs, regs[12]); | |
40 | OFFSET(PT_R13, pt_regs, regs[13]); | |
41 | OFFSET(PT_R14, pt_regs, regs[14]); | |
42 | OFFSET(PT_R15, pt_regs, regs[15]); | |
43 | OFFSET(PT_R16, pt_regs, regs[16]); | |
44 | OFFSET(PT_R17, pt_regs, regs[17]); | |
45 | OFFSET(PT_R18, pt_regs, regs[18]); | |
46 | OFFSET(PT_R19, pt_regs, regs[19]); | |
47 | OFFSET(PT_R20, pt_regs, regs[20]); | |
48 | OFFSET(PT_R21, pt_regs, regs[21]); | |
49 | OFFSET(PT_R22, pt_regs, regs[22]); | |
50 | OFFSET(PT_R23, pt_regs, regs[23]); | |
51 | OFFSET(PT_R24, pt_regs, regs[24]); | |
52 | OFFSET(PT_R25, pt_regs, regs[25]); | |
53 | OFFSET(PT_R26, pt_regs, regs[26]); | |
54 | OFFSET(PT_R27, pt_regs, regs[27]); | |
55 | OFFSET(PT_R28, pt_regs, regs[28]); | |
56 | OFFSET(PT_R29, pt_regs, regs[29]); | |
57 | OFFSET(PT_R30, pt_regs, regs[30]); | |
58 | OFFSET(PT_R31, pt_regs, regs[31]); | |
59 | OFFSET(PT_LO, pt_regs, lo); | |
60 | OFFSET(PT_HI, pt_regs, hi); | |
9693a853 | 61 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
fd04d206 | 62 | OFFSET(PT_ACX, pt_regs, acx); |
9693a853 | 63 | #endif |
fd04d206 CL |
64 | OFFSET(PT_EPC, pt_regs, cp0_epc); |
65 | OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr); | |
66 | OFFSET(PT_STATUS, pt_regs, cp0_status); | |
67 | OFFSET(PT_CAUSE, pt_regs, cp0_cause); | |
41c594ab | 68 | #ifdef CONFIG_MIPS_MT_SMTC |
fd04d206 | 69 | OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); |
41c594ab | 70 | #endif /* CONFIG_MIPS_MT_SMTC */ |
babed555 DD |
71 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
72 | OFFSET(PT_MPL, pt_regs, mpl); | |
73 | OFFSET(PT_MTP, pt_regs, mtp); | |
74 | #endif /* CONFIG_CPU_CAVIUM_OCTEON */ | |
fd04d206 CL |
75 | DEFINE(PT_SIZE, sizeof(struct pt_regs)); |
76 | BLANK(); | |
1da177e4 LT |
77 | } |
78 | ||
79 | void output_task_defines(void) | |
80 | { | |
fd04d206 CL |
81 | COMMENT("MIPS task_struct offsets."); |
82 | OFFSET(TASK_STATE, task_struct, state); | |
83 | OFFSET(TASK_THREAD_INFO, task_struct, stack); | |
84 | OFFSET(TASK_FLAGS, task_struct, flags); | |
85 | OFFSET(TASK_MM, task_struct, mm); | |
86 | OFFSET(TASK_PID, task_struct, pid); | |
1400eb65 GF |
87 | #if defined(CONFIG_CC_STACKPROTECTOR) |
88 | OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); | |
89 | #endif | |
fd04d206 CL |
90 | DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); |
91 | BLANK(); | |
1da177e4 LT |
92 | } |
93 | ||
94 | void output_thread_info_defines(void) | |
95 | { | |
fd04d206 CL |
96 | COMMENT("MIPS thread_info offsets."); |
97 | OFFSET(TI_TASK, thread_info, task); | |
98 | OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain); | |
99 | OFFSET(TI_FLAGS, thread_info, flags); | |
100 | OFFSET(TI_TP_VALUE, thread_info, tp_value); | |
101 | OFFSET(TI_CPU, thread_info, cpu); | |
102 | OFFSET(TI_PRE_COUNT, thread_info, preempt_count); | |
103 | OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); | |
104 | OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); | |
105 | OFFSET(TI_REGS, thread_info, regs); | |
106 | DEFINE(_THREAD_SIZE, THREAD_SIZE); | |
107 | DEFINE(_THREAD_MASK, THREAD_MASK); | |
108 | BLANK(); | |
1da177e4 LT |
109 | } |
110 | ||
111 | void output_thread_defines(void) | |
112 | { | |
fd04d206 CL |
113 | COMMENT("MIPS specific thread_struct offsets."); |
114 | OFFSET(THREAD_REG16, task_struct, thread.reg16); | |
115 | OFFSET(THREAD_REG17, task_struct, thread.reg17); | |
116 | OFFSET(THREAD_REG18, task_struct, thread.reg18); | |
117 | OFFSET(THREAD_REG19, task_struct, thread.reg19); | |
118 | OFFSET(THREAD_REG20, task_struct, thread.reg20); | |
119 | OFFSET(THREAD_REG21, task_struct, thread.reg21); | |
120 | OFFSET(THREAD_REG22, task_struct, thread.reg22); | |
121 | OFFSET(THREAD_REG23, task_struct, thread.reg23); | |
122 | OFFSET(THREAD_REG29, task_struct, thread.reg29); | |
123 | OFFSET(THREAD_REG30, task_struct, thread.reg30); | |
124 | OFFSET(THREAD_REG31, task_struct, thread.reg31); | |
125 | OFFSET(THREAD_STATUS, task_struct, | |
1da177e4 | 126 | thread.cp0_status); |
fd04d206 | 127 | OFFSET(THREAD_FPU, task_struct, thread.fpu); |
1da177e4 | 128 | |
fd04d206 | 129 | OFFSET(THREAD_BVADDR, task_struct, \ |
1da177e4 | 130 | thread.cp0_badvaddr); |
fd04d206 | 131 | OFFSET(THREAD_BUADDR, task_struct, \ |
1da177e4 | 132 | thread.cp0_baduaddr); |
fd04d206 | 133 | OFFSET(THREAD_ECODE, task_struct, \ |
1da177e4 | 134 | thread.error_code); |
fd04d206 | 135 | BLANK(); |
1da177e4 LT |
136 | } |
137 | ||
138 | void output_thread_fpu_defines(void) | |
139 | { | |
fd04d206 CL |
140 | OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]); |
141 | OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]); | |
142 | OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]); | |
143 | OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]); | |
144 | OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]); | |
145 | OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]); | |
146 | OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]); | |
147 | OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]); | |
148 | OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]); | |
149 | OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]); | |
150 | OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]); | |
151 | OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]); | |
152 | OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]); | |
153 | OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]); | |
154 | OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]); | |
155 | OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]); | |
156 | OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]); | |
157 | OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]); | |
158 | OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]); | |
159 | OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]); | |
160 | OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]); | |
161 | OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]); | |
162 | OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]); | |
163 | OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]); | |
164 | OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]); | |
165 | OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]); | |
166 | OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]); | |
167 | OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]); | |
168 | OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]); | |
169 | OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]); | |
170 | OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); | |
171 | OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); | |
1da177e4 | 172 | |
02987633 PB |
173 | /* the least significant 64 bits of each FP register */ |
174 | OFFSET(THREAD_FPR0_LS64, task_struct, | |
175 | thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]); | |
176 | OFFSET(THREAD_FPR1_LS64, task_struct, | |
177 | thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]); | |
178 | OFFSET(THREAD_FPR2_LS64, task_struct, | |
179 | thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]); | |
180 | OFFSET(THREAD_FPR3_LS64, task_struct, | |
181 | thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]); | |
182 | OFFSET(THREAD_FPR4_LS64, task_struct, | |
183 | thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]); | |
184 | OFFSET(THREAD_FPR5_LS64, task_struct, | |
185 | thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]); | |
186 | OFFSET(THREAD_FPR6_LS64, task_struct, | |
187 | thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]); | |
188 | OFFSET(THREAD_FPR7_LS64, task_struct, | |
189 | thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]); | |
190 | OFFSET(THREAD_FPR8_LS64, task_struct, | |
191 | thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]); | |
192 | OFFSET(THREAD_FPR9_LS64, task_struct, | |
193 | thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]); | |
194 | OFFSET(THREAD_FPR10_LS64, task_struct, | |
195 | thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]); | |
196 | OFFSET(THREAD_FPR11_LS64, task_struct, | |
197 | thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]); | |
198 | OFFSET(THREAD_FPR12_LS64, task_struct, | |
199 | thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]); | |
200 | OFFSET(THREAD_FPR13_LS64, task_struct, | |
201 | thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]); | |
202 | OFFSET(THREAD_FPR14_LS64, task_struct, | |
203 | thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]); | |
204 | OFFSET(THREAD_FPR15_LS64, task_struct, | |
205 | thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]); | |
206 | OFFSET(THREAD_FPR16_LS64, task_struct, | |
207 | thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]); | |
208 | OFFSET(THREAD_FPR17_LS64, task_struct, | |
209 | thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]); | |
210 | OFFSET(THREAD_FPR18_LS64, task_struct, | |
211 | thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]); | |
212 | OFFSET(THREAD_FPR19_LS64, task_struct, | |
213 | thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]); | |
214 | OFFSET(THREAD_FPR20_LS64, task_struct, | |
215 | thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]); | |
216 | OFFSET(THREAD_FPR21_LS64, task_struct, | |
217 | thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]); | |
218 | OFFSET(THREAD_FPR22_LS64, task_struct, | |
219 | thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]); | |
220 | OFFSET(THREAD_FPR23_LS64, task_struct, | |
221 | thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]); | |
222 | OFFSET(THREAD_FPR24_LS64, task_struct, | |
223 | thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]); | |
224 | OFFSET(THREAD_FPR25_LS64, task_struct, | |
225 | thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]); | |
226 | OFFSET(THREAD_FPR26_LS64, task_struct, | |
227 | thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]); | |
228 | OFFSET(THREAD_FPR27_LS64, task_struct, | |
229 | thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]); | |
230 | OFFSET(THREAD_FPR28_LS64, task_struct, | |
231 | thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]); | |
232 | OFFSET(THREAD_FPR29_LS64, task_struct, | |
233 | thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]); | |
234 | OFFSET(THREAD_FPR30_LS64, task_struct, | |
235 | thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]); | |
236 | OFFSET(THREAD_FPR31_LS64, task_struct, | |
237 | thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]); | |
238 | ||
fd04d206 CL |
239 | OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); |
240 | BLANK(); | |
1da177e4 LT |
241 | } |
242 | ||
243 | void output_mm_defines(void) | |
244 | { | |
fd04d206 CL |
245 | COMMENT("Size of struct page"); |
246 | DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page)); | |
247 | BLANK(); | |
248 | COMMENT("Linux mm_struct offsets."); | |
249 | OFFSET(MM_USERS, mm_struct, mm_users); | |
250 | OFFSET(MM_PGD, mm_struct, pgd); | |
251 | OFFSET(MM_CONTEXT, mm_struct, context); | |
252 | BLANK(); | |
fd04d206 CL |
253 | DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); |
254 | DEFINE(_PMD_T_SIZE, sizeof(pmd_t)); | |
255 | DEFINE(_PTE_T_SIZE, sizeof(pte_t)); | |
256 | BLANK(); | |
257 | DEFINE(_PGD_T_LOG2, PGD_T_LOG2); | |
325f8a0a | 258 | #ifndef __PAGETABLE_PMD_FOLDED |
fd04d206 | 259 | DEFINE(_PMD_T_LOG2, PMD_T_LOG2); |
325f8a0a | 260 | #endif |
fd04d206 CL |
261 | DEFINE(_PTE_T_LOG2, PTE_T_LOG2); |
262 | BLANK(); | |
263 | DEFINE(_PGD_ORDER, PGD_ORDER); | |
325f8a0a | 264 | #ifndef __PAGETABLE_PMD_FOLDED |
fd04d206 | 265 | DEFINE(_PMD_ORDER, PMD_ORDER); |
325f8a0a | 266 | #endif |
fd04d206 CL |
267 | DEFINE(_PTE_ORDER, PTE_ORDER); |
268 | BLANK(); | |
269 | DEFINE(_PMD_SHIFT, PMD_SHIFT); | |
270 | DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT); | |
271 | BLANK(); | |
272 | DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD); | |
273 | DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD); | |
274 | DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE); | |
275 | BLANK(); | |
20082595 RB |
276 | DEFINE(_PAGE_SHIFT, PAGE_SHIFT); |
277 | DEFINE(_PAGE_SIZE, PAGE_SIZE); | |
278 | BLANK(); | |
1da177e4 LT |
279 | } |
280 | ||
e50c0a8f | 281 | #ifdef CONFIG_32BIT |
1da177e4 LT |
282 | void output_sc_defines(void) |
283 | { | |
fd04d206 CL |
284 | COMMENT("Linux sigcontext offsets."); |
285 | OFFSET(SC_REGS, sigcontext, sc_regs); | |
286 | OFFSET(SC_FPREGS, sigcontext, sc_fpregs); | |
287 | OFFSET(SC_ACX, sigcontext, sc_acx); | |
288 | OFFSET(SC_MDHI, sigcontext, sc_mdhi); | |
289 | OFFSET(SC_MDLO, sigcontext, sc_mdlo); | |
290 | OFFSET(SC_PC, sigcontext, sc_pc); | |
291 | OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); | |
292 | OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir); | |
293 | OFFSET(SC_HI1, sigcontext, sc_hi1); | |
294 | OFFSET(SC_LO1, sigcontext, sc_lo1); | |
295 | OFFSET(SC_HI2, sigcontext, sc_hi2); | |
296 | OFFSET(SC_LO2, sigcontext, sc_lo2); | |
297 | OFFSET(SC_HI3, sigcontext, sc_hi3); | |
298 | OFFSET(SC_LO3, sigcontext, sc_lo3); | |
eec43a22 | 299 | OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); |
fd04d206 | 300 | BLANK(); |
1da177e4 | 301 | } |
e50c0a8f RB |
302 | #endif |
303 | ||
304 | #ifdef CONFIG_64BIT | |
305 | void output_sc_defines(void) | |
306 | { | |
fd04d206 CL |
307 | COMMENT("Linux sigcontext offsets."); |
308 | OFFSET(SC_REGS, sigcontext, sc_regs); | |
309 | OFFSET(SC_FPREGS, sigcontext, sc_fpregs); | |
310 | OFFSET(SC_MDHI, sigcontext, sc_mdhi); | |
311 | OFFSET(SC_MDLO, sigcontext, sc_mdlo); | |
312 | OFFSET(SC_PC, sigcontext, sc_pc); | |
313 | OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); | |
eec43a22 | 314 | OFFSET(SC_MSAREGS, sigcontext, sc_msaregs); |
fd04d206 | 315 | BLANK(); |
e50c0a8f RB |
316 | } |
317 | #endif | |
1da177e4 LT |
318 | |
319 | #ifdef CONFIG_MIPS32_COMPAT | |
320 | void output_sc32_defines(void) | |
321 | { | |
fd04d206 CL |
322 | COMMENT("Linux 32-bit sigcontext offsets."); |
323 | OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs); | |
324 | OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr); | |
325 | OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir); | |
eec43a22 | 326 | OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs); |
fd04d206 | 327 | BLANK(); |
1da177e4 LT |
328 | } |
329 | #endif | |
330 | ||
331 | void output_signal_defined(void) | |
332 | { | |
fd04d206 CL |
333 | COMMENT("Linux signal numbers."); |
334 | DEFINE(_SIGHUP, SIGHUP); | |
335 | DEFINE(_SIGINT, SIGINT); | |
336 | DEFINE(_SIGQUIT, SIGQUIT); | |
337 | DEFINE(_SIGILL, SIGILL); | |
338 | DEFINE(_SIGTRAP, SIGTRAP); | |
339 | DEFINE(_SIGIOT, SIGIOT); | |
340 | DEFINE(_SIGABRT, SIGABRT); | |
341 | DEFINE(_SIGEMT, SIGEMT); | |
342 | DEFINE(_SIGFPE, SIGFPE); | |
343 | DEFINE(_SIGKILL, SIGKILL); | |
344 | DEFINE(_SIGBUS, SIGBUS); | |
345 | DEFINE(_SIGSEGV, SIGSEGV); | |
346 | DEFINE(_SIGSYS, SIGSYS); | |
347 | DEFINE(_SIGPIPE, SIGPIPE); | |
348 | DEFINE(_SIGALRM, SIGALRM); | |
349 | DEFINE(_SIGTERM, SIGTERM); | |
350 | DEFINE(_SIGUSR1, SIGUSR1); | |
351 | DEFINE(_SIGUSR2, SIGUSR2); | |
352 | DEFINE(_SIGCHLD, SIGCHLD); | |
353 | DEFINE(_SIGPWR, SIGPWR); | |
354 | DEFINE(_SIGWINCH, SIGWINCH); | |
355 | DEFINE(_SIGURG, SIGURG); | |
356 | DEFINE(_SIGIO, SIGIO); | |
357 | DEFINE(_SIGSTOP, SIGSTOP); | |
358 | DEFINE(_SIGTSTP, SIGTSTP); | |
359 | DEFINE(_SIGCONT, SIGCONT); | |
360 | DEFINE(_SIGTTIN, SIGTTIN); | |
361 | DEFINE(_SIGTTOU, SIGTTOU); | |
362 | DEFINE(_SIGVTALRM, SIGVTALRM); | |
363 | DEFINE(_SIGPROF, SIGPROF); | |
364 | DEFINE(_SIGXCPU, SIGXCPU); | |
365 | DEFINE(_SIGXFSZ, SIGXFSZ); | |
366 | BLANK(); | |
1da177e4 LT |
367 | } |
368 | ||
babed555 DD |
369 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
370 | void output_octeon_cop2_state_defines(void) | |
371 | { | |
372 | COMMENT("Octeon specific octeon_cop2_state offsets."); | |
373 | OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); | |
374 | OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); | |
375 | OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); | |
376 | OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); | |
377 | OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); | |
378 | OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); | |
379 | OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); | |
380 | OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); | |
381 | OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); | |
382 | OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); | |
383 | OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); | |
384 | OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); | |
385 | OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); | |
386 | OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); | |
387 | OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); | |
388 | OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); | |
389 | OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); | |
390 | OFFSET(THREAD_CP2, task_struct, thread.cp2); | |
391 | OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); | |
392 | BLANK(); | |
393 | } | |
394 | #endif | |
363c55ca WZ |
395 | |
396 | #ifdef CONFIG_HIBERNATION | |
397 | void output_pbe_defines(void) | |
398 | { | |
399 | COMMENT(" Linux struct pbe offsets. "); | |
400 | OFFSET(PBE_ADDRESS, pbe, address); | |
401 | OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); | |
402 | OFFSET(PBE_NEXT, pbe, next); | |
403 | DEFINE(PBE_SIZE, sizeof(struct pbe)); | |
404 | BLANK(); | |
405 | } | |
406 | #endif | |
12e25f8e | 407 | |
74e91335 JH |
408 | #ifdef CONFIG_CPU_PM |
409 | void output_pm_defines(void) | |
410 | { | |
411 | COMMENT(" PM offsets. "); | |
412 | #ifdef CONFIG_EVA | |
413 | OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]); | |
414 | OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]); | |
415 | OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]); | |
416 | #endif | |
417 | OFFSET(SSS_SP, mips_static_suspend_state, sp); | |
418 | BLANK(); | |
419 | } | |
420 | #endif | |
421 | ||
12e25f8e SL |
422 | void output_kvm_defines(void) |
423 | { | |
424 | COMMENT(" KVM/MIPS Specfic offsets. "); | |
425 | DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch)); | |
426 | OFFSET(VCPU_RUN, kvm_vcpu, run); | |
427 | OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch); | |
428 | ||
429 | OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase); | |
430 | OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase); | |
431 | ||
432 | OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack); | |
433 | OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp); | |
434 | ||
435 | OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr); | |
436 | OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause); | |
437 | OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc); | |
438 | OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi); | |
439 | ||
440 | OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst); | |
441 | ||
442 | OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]); | |
443 | OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]); | |
444 | OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]); | |
445 | OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]); | |
446 | OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]); | |
447 | OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]); | |
448 | OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]); | |
449 | OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]); | |
450 | OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]); | |
451 | OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]); | |
452 | OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]); | |
453 | OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]); | |
454 | OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]); | |
455 | OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]); | |
456 | OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]); | |
457 | OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]); | |
458 | OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]); | |
459 | OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]); | |
460 | OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]); | |
461 | OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]); | |
462 | OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]); | |
463 | OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]); | |
464 | OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]); | |
465 | OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]); | |
466 | OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]); | |
467 | OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]); | |
468 | OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]); | |
469 | OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]); | |
470 | OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]); | |
471 | OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]); | |
472 | OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]); | |
473 | OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]); | |
474 | OFFSET(VCPU_LO, kvm_vcpu_arch, lo); | |
475 | OFFSET(VCPU_HI, kvm_vcpu_arch, hi); | |
476 | OFFSET(VCPU_PC, kvm_vcpu_arch, pc); | |
477 | OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0); | |
478 | OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid); | |
479 | OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid); | |
480 | ||
481 | OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]); | |
482 | OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]); | |
483 | BLANK(); | |
484 | } | |
0ee958e1 PB |
485 | |
486 | #ifdef CONFIG_MIPS_CPS | |
487 | void output_cps_defines(void) | |
488 | { | |
489 | COMMENT(" MIPS CPS offsets. "); | |
490 | OFFSET(BOOTCFG_CORE, boot_config, core); | |
491 | OFFSET(BOOTCFG_VPE, boot_config, vpe); | |
492 | OFFSET(BOOTCFG_PC, boot_config, pc); | |
493 | OFFSET(BOOTCFG_SP, boot_config, sp); | |
494 | OFFSET(BOOTCFG_GP, boot_config, gp); | |
495 | } | |
496 | #endif |