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42f77542 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2007 MIPS Technologies, Inc. | |
7 | * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> | |
8 | */ | |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/percpu.h> | |
631330f5 | 12 | #include <linux/smp.h> |
ca4d3e67 | 13 | #include <linux/irq.h> |
42f77542 | 14 | |
f887b93e | 15 | #include <asm/smtc_ipi.h> |
42f77542 | 16 | #include <asm/time.h> |
8531a35e | 17 | #include <asm/cevt-r4k.h> |
98b67c37 | 18 | #include <asm/gic.h> |
8531a35e KK |
19 | |
20 | /* | |
21 | * The SMTC Kernel for the 34K, 1004K, et. al. replaces several | |
22 | * of these routines with SMTC-specific variants. | |
23 | */ | |
24 | ||
25 | #ifndef CONFIG_MIPS_MT_SMTC | |
42f77542 | 26 | static int mips_next_event(unsigned long delta, |
70342287 | 27 | struct clock_event_device *evt) |
42f77542 RB |
28 | { |
29 | unsigned int cnt; | |
30 | int res; | |
31 | ||
42f77542 RB |
32 | cnt = read_c0_count(); |
33 | cnt += delta; | |
34 | write_c0_compare(cnt); | |
5878fc93 | 35 | res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; |
42f77542 RB |
36 | return res; |
37 | } | |
38 | ||
8531a35e KK |
39 | #endif /* CONFIG_MIPS_MT_SMTC */ |
40 | ||
41 | void mips_set_clock_mode(enum clock_event_mode mode, | |
42 | struct clock_event_device *evt) | |
42f77542 RB |
43 | { |
44 | /* Nothing to do ... */ | |
45 | } | |
46 | ||
8531a35e KK |
47 | DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
48 | int cp0_timer_irq_installed; | |
42f77542 | 49 | |
8531a35e | 50 | #ifndef CONFIG_MIPS_MT_SMTC |
8531a35e | 51 | irqreturn_t c0_compare_interrupt(int irq, void *dev_id) |
42f77542 RB |
52 | { |
53 | const int r2 = cpu_has_mips_r2; | |
54 | struct clock_event_device *cd; | |
55 | int cpu = smp_processor_id(); | |
56 | ||
57 | /* | |
58 | * Suckage alert: | |
59 | * Before R2 of the architecture there was no way to see if a | |
60 | * performance counter interrupt was pending, so we have to run | |
61 | * the performance counter interrupt handler anyway. | |
62 | */ | |
63 | if (handle_perf_irq(r2)) | |
64 | goto out; | |
65 | ||
66 | /* | |
70342287 | 67 | * The same applies to performance counter interrupts. But with the |
42f77542 RB |
68 | * above we now know that the reason we got here must be a timer |
69 | * interrupt. Being the paranoiacs we are we check anyway. | |
70 | */ | |
71 | if (!r2 || (read_c0_cause() & (1 << 30))) { | |
8531a35e KK |
72 | /* Clear Count/Compare Interrupt */ |
73 | write_c0_compare(read_c0_compare()); | |
42f77542 | 74 | cd = &per_cpu(mips_clockevent_device, cpu); |
0ab2b7d0 RG |
75 | #ifdef CONFIG_CEVT_GIC |
76 | if (!gic_present) | |
77 | #endif | |
42f77542 RB |
78 | cd->event_handler(cd); |
79 | } | |
80 | ||
81 | out: | |
82 | return IRQ_HANDLED; | |
83 | } | |
84 | ||
8531a35e KK |
85 | #endif /* Not CONFIG_MIPS_MT_SMTC */ |
86 | ||
87 | struct irqaction c0_compare_irqaction = { | |
42f77542 | 88 | .handler = c0_compare_interrupt, |
8b5690f8 | 89 | .flags = IRQF_PERCPU | IRQF_TIMER, |
42f77542 RB |
90 | .name = "timer", |
91 | }; | |
92 | ||
42f77542 | 93 | |
8531a35e | 94 | void mips_event_handler(struct clock_event_device *dev) |
42f77542 RB |
95 | { |
96 | } | |
97 | ||
98 | /* | |
99 | * FIXME: This doesn't hold for the relocated E9000 compare interrupt. | |
100 | */ | |
101 | static int c0_compare_int_pending(void) | |
102 | { | |
98b67c37 SH |
103 | #ifdef CONFIG_IRQ_GIC |
104 | if (cpu_has_veic) | |
105 | return gic_get_timer_pending(); | |
106 | #endif | |
010c108d | 107 | return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); |
42f77542 RB |
108 | } |
109 | ||
8531a35e KK |
110 | /* |
111 | * Compare interrupt can be routed and latched outside the core, | |
4f1a1eb5 AC |
112 | * so wait up to worst case number of cycle counter ticks for timer interrupt |
113 | * changes to propagate to the cause register. | |
8531a35e | 114 | */ |
4f1a1eb5 | 115 | #define COMPARE_INT_SEEN_TICKS 50 |
8531a35e KK |
116 | |
117 | int c0_compare_int_usable(void) | |
42f77542 | 118 | { |
3a6c43a7 | 119 | unsigned int delta; |
42f77542 RB |
120 | unsigned int cnt; |
121 | ||
9843b030 SL |
122 | #ifdef CONFIG_KVM_GUEST |
123 | return 1; | |
124 | #endif | |
125 | ||
42f77542 | 126 | /* |
70342287 | 127 | * IP7 already pending? Try to clear it by acking the timer. |
42f77542 RB |
128 | */ |
129 | if (c0_compare_int_pending()) { | |
4f1a1eb5 AC |
130 | cnt = read_c0_count(); |
131 | write_c0_compare(cnt); | |
132 | back_to_back_c0_hazard(); | |
133 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) | |
134 | if (!c0_compare_int_pending()) | |
135 | break; | |
42f77542 RB |
136 | if (c0_compare_int_pending()) |
137 | return 0; | |
138 | } | |
139 | ||
3a6c43a7 AN |
140 | for (delta = 0x10; delta <= 0x400000; delta <<= 1) { |
141 | cnt = read_c0_count(); | |
142 | cnt += delta; | |
143 | write_c0_compare(cnt); | |
4f1a1eb5 | 144 | back_to_back_c0_hazard(); |
3a6c43a7 AN |
145 | if ((int)(read_c0_count() - cnt) < 0) |
146 | break; | |
147 | /* increase delta if the timer was already expired */ | |
148 | } | |
42f77542 | 149 | |
c637fecb | 150 | while ((int)(read_c0_count() - cnt) <= 0) |
42f77542 RB |
151 | ; /* Wait for expiry */ |
152 | ||
4f1a1eb5 AC |
153 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
154 | if (c0_compare_int_pending()) | |
155 | break; | |
42f77542 RB |
156 | if (!c0_compare_int_pending()) |
157 | return 0; | |
4f1a1eb5 AC |
158 | cnt = read_c0_count(); |
159 | write_c0_compare(cnt); | |
160 | back_to_back_c0_hazard(); | |
161 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) | |
162 | if (!c0_compare_int_pending()) | |
163 | break; | |
42f77542 RB |
164 | if (c0_compare_int_pending()) |
165 | return 0; | |
166 | ||
167 | /* | |
168 | * Feels like a real count / compare timer. | |
169 | */ | |
170 | return 1; | |
171 | } | |
172 | ||
8531a35e | 173 | #ifndef CONFIG_MIPS_MT_SMTC |
078a55fc | 174 | int r4k_clockevent_init(void) |
42f77542 | 175 | { |
42f77542 RB |
176 | unsigned int cpu = smp_processor_id(); |
177 | struct clock_event_device *cd; | |
38760d40 | 178 | unsigned int irq; |
42f77542 | 179 | |
22df3f53 | 180 | if (!cpu_has_counter || !mips_hpt_frequency) |
5aa85c9f | 181 | return -ENXIO; |
42f77542 | 182 | |
42f77542 | 183 | if (!c0_compare_int_usable()) |
5aa85c9f | 184 | return -ENXIO; |
42f77542 | 185 | |
38760d40 RB |
186 | /* |
187 | * With vectored interrupts things are getting platform specific. | |
188 | * get_c0_compare_int is a hook to allow a platform to return the | |
189 | * interrupt number of it's liking. | |
190 | */ | |
191 | irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
192 | if (get_c0_compare_int) | |
193 | irq = get_c0_compare_int(); | |
194 | ||
42f77542 RB |
195 | cd = &per_cpu(mips_clockevent_device, cpu); |
196 | ||
197 | cd->name = "MIPS"; | |
198 | cd->features = CLOCK_EVT_FEAT_ONESHOT; | |
199 | ||
4d2b1125 DD |
200 | clockevent_set_clock(cd, mips_hpt_frequency); |
201 | ||
42f77542 | 202 | /* Calculate the min / max delta */ |
42f77542 RB |
203 | cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); |
204 | cd->min_delta_ns = clockevent_delta2ns(0x300, cd); | |
205 | ||
206 | cd->rating = 300; | |
207 | cd->irq = irq; | |
320ab2b0 | 208 | cd->cpumask = cpumask_of(cpu); |
42f77542 | 209 | cd->set_next_event = mips_next_event; |
8531a35e | 210 | cd->set_mode = mips_set_clock_mode; |
42f77542 RB |
211 | cd->event_handler = mips_event_handler; |
212 | ||
0ab2b7d0 RG |
213 | #ifdef CONFIG_CEVT_GIC |
214 | if (!gic_present) | |
215 | #endif | |
42f77542 RB |
216 | clockevents_register_device(cd); |
217 | ||
aea68639 | 218 | if (cp0_timer_irq_installed) |
5aa85c9f | 219 | return 0; |
38760d40 RB |
220 | |
221 | cp0_timer_irq_installed = 1; | |
222 | ||
38760d40 | 223 | setup_irq(irq, &c0_compare_irqaction); |
5aa85c9f RB |
224 | |
225 | return 0; | |
42f77542 | 226 | } |
8531a35e KK |
227 | |
228 | #endif /* Not CONFIG_MIPS_MT_SMTC */ |