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217dd11e RB |
1 | /* |
2 | * Copyright (C) 2000, 2001 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/percpu.h> | |
21 | ||
22 | #include <asm/addrspace.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/time.h> | |
25 | ||
26 | #include <asm/sibyte/sb1250.h> | |
27 | #include <asm/sibyte/sb1250_regs.h> | |
28 | #include <asm/sibyte/sb1250_int.h> | |
29 | #include <asm/sibyte/sb1250_scd.h> | |
30 | ||
31 | #define IMR_IP2_VAL K_INT_MAP_I0 | |
32 | #define IMR_IP3_VAL K_INT_MAP_I1 | |
33 | #define IMR_IP4_VAL K_INT_MAP_I2 | |
34 | ||
35 | /* | |
36 | * The general purpose timer ticks at 1MHz independent if | |
37 | * the rest of the system | |
38 | */ | |
39 | static void sibyte_set_mode(enum clock_event_mode mode, | |
40 | struct clock_event_device *evt) | |
41 | { | |
42 | unsigned int cpu = smp_processor_id(); | |
43 | void __iomem *cfg, *init; | |
44 | ||
45 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
46 | init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | |
47 | ||
48 | switch (mode) { | |
49 | case CLOCK_EVT_MODE_PERIODIC: | |
50 | __raw_writeq(0, cfg); | |
51 | __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); | |
52 | __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | |
53 | cfg); | |
54 | break; | |
55 | ||
56 | case CLOCK_EVT_MODE_ONESHOT: | |
57 | /* Stop the timer until we actually program a shot */ | |
58 | case CLOCK_EVT_MODE_SHUTDOWN: | |
59 | __raw_writeq(0, cfg); | |
60 | break; | |
61 | ||
62 | case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ | |
63 | case CLOCK_EVT_MODE_RESUME: | |
64 | ; | |
65 | } | |
66 | } | |
67 | ||
68 | static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) | |
69 | { | |
70 | unsigned int cpu = smp_processor_id(); | |
71 | void __iomem *cfg, *init; | |
72 | ||
73 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
74 | init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | |
75 | ||
76 | __raw_writeq(delta - 1, init); | |
77 | __raw_writeq(M_SCD_TIMER_ENABLE, cfg); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) | |
83 | { | |
84 | unsigned int cpu = smp_processor_id(); | |
85 | struct clock_event_device *cd = dev_id; | |
86 | void __iomem *cfg; | |
87 | unsigned long tmode; | |
88 | ||
89 | if (cd->mode == CLOCK_EVT_MODE_PERIODIC) | |
90 | tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; | |
91 | else | |
92 | tmode = 0; | |
93 | ||
94 | /* ACK interrupt */ | |
95 | cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | |
96 | ____raw_writeq(tmode, cfg); | |
97 | ||
98 | cd->event_handler(cd); | |
99 | ||
100 | return IRQ_HANDLED; | |
101 | } | |
102 | ||
103 | static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); | |
104 | static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); | |
105 | static DEFINE_PER_CPU(char [18], sibyte_hpt_name); | |
106 | ||
107 | void __cpuinit sb1250_clockevent_init(void) | |
108 | { | |
109 | unsigned int cpu = smp_processor_id(); | |
110 | unsigned int irq = K_INT_TIMER_0 + cpu; | |
111 | struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); | |
112 | struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); | |
113 | unsigned char *name = per_cpu(sibyte_hpt_name, cpu); | |
114 | ||
115 | /* Only have 4 general purpose timers, and we use last one as hpt */ | |
116 | BUG_ON(cpu > 2); | |
117 | ||
118 | sprintf(name, "sb1250-counter-%d", cpu); | |
119 | cd->name = name; | |
120 | cd->features = CLOCK_EVT_FEAT_PERIODIC | | |
121 | CLOCK_EVT_FEAT_ONESHOT; | |
122 | clockevent_set_clock(cd, V_SCD_TIMER_FREQ); | |
123 | cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); | |
124 | cd->min_delta_ns = clockevent_delta2ns(1, cd); | |
125 | cd->rating = 200; | |
126 | cd->irq = irq; | |
127 | cd->cpumask = cpumask_of_cpu(cpu); | |
128 | cd->set_next_event = sibyte_next_event; | |
129 | cd->set_mode = sibyte_set_mode; | |
130 | clockevents_register_device(cd); | |
131 | ||
132 | sb1250_mask_irq(cpu, irq); | |
133 | ||
134 | /* | |
135 | * Map the timer interrupt to IP[4] of this cpu | |
136 | */ | |
137 | __raw_writeq(IMR_IP4_VAL, | |
138 | IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + | |
139 | (irq << 3))); | |
140 | ||
141 | sb1250_unmask_irq(cpu, irq); | |
142 | ||
143 | action->handler = sibyte_counter_handler; | |
144 | action->flags = IRQF_DISABLED | IRQF_PERCPU; | |
07a80e49 | 145 | action->mask = cpumask_of_cpu(cpu); |
217dd11e RB |
146 | action->name = name; |
147 | action->dev_id = cd; | |
07a80e49 RB |
148 | |
149 | irq_set_affinity(irq, cpumask_of_cpu(cpu)); | |
217dd11e RB |
150 | setup_irq(irq, action); |
151 | } |