[deliverable/linux.git] / arch / mips / kernel / cevt-txx9.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Based on linux/arch/mips/kernel/cevt-r4k.c,
 *	    linux/arch/mips/jmr3927/rbhma3100/setup.c
 *
 * Copyright 2001 MontaVista Software Inc.
 * Copyright (C) 2000-2001 Toshiba Corporation
 * Copyright (C) 2007 MIPS Technologies, Inc.
 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <asm/time.h>
#include <asm/txx9tmr.h>

#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
#define TIMER_CCD	0	/* 1/2 */
#define TIMER_CLK(imclk)	((imclk) / (2 << TIMER_CCD))

struct txx9_clocksource {
	struct clocksource cs;
	struct txx9_tmr_reg __iomem *tmrptr;
};

static cycle_t txx9_cs_read(struct clocksource *cs)
{
	struct txx9_clocksource *txx9_cs =
		container_of(cs, struct txx9_clocksource, cs);
	return __raw_readl(&txx9_cs->tmrptr->trr);
}

/* Use 1 bit smaller width to use full bits in that width */
#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)

static struct txx9_clocksource txx9_clocksource = {
	.cs = {
		.name		= "TXx9",
		.rating		= 200,
		.read		= txx9_cs_read,
		.mask		= CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
		.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

static u64 notrace txx9_read_sched_clock(void)
{
	return __raw_readl(&txx9_clocksource.tmrptr->trr);
}

void __init txx9_clocksource_init(unsigned long baseaddr,
				  unsigned int imbusclk)
{
	struct txx9_tmr_reg __iomem *tmrptr;

	clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	__raw_writel(TCR_BASE, &tmrptr->tcr);
	__raw_writel(0, &tmrptr->tisr);
	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	txx9_clocksource.tmrptr = tmrptr;

	sched_clock_register(txx9_read_sched_clock, TXX9_CLOCKSOURCE_BITS,
			     TIMER_CLK(imbusclk));
}

struct txx9_clock_event_device {
	struct clock_event_device cd;
	struct txx9_tmr_reg __iomem *tmrptr;
};

static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
{
	/* stop and reset counter */
	__raw_writel(TCR_BASE, &tmrptr->tcr);
	/* clear pending interrupt */
	__raw_writel(0, &tmrptr->tisr);
}

static int txx9tmr_set_state_periodic(struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);

	__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr);
	/* start timer */
	__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift,
		     &tmrptr->cpra);
	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	return 0;
}

static int txx9tmr_set_state_oneshot(struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
	return 0;
}

static int txx9tmr_set_state_shutdown(struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	__raw_writel(0, &tmrptr->itmr);
	return 0;
}

static int txx9tmr_tick_resume(struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	__raw_writel(0, &tmrptr->itmr);
	return 0;
}

static int txx9tmr_set_next_event(unsigned long delta,
				  struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	/* start timer */
	__raw_writel(delta, &tmrptr->cpra);
	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	return 0;
}

static struct txx9_clock_event_device txx9_clock_event_device = {
	.cd = {
		.name			= "TXx9",
		.features		= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT,
		.rating			= 200,
		.set_state_shutdown	= txx9tmr_set_state_shutdown,
		.set_state_periodic	= txx9tmr_set_state_periodic,
		.set_state_oneshot	= txx9tmr_set_state_oneshot,
		.tick_resume		= txx9tmr_tick_resume,
		.set_next_event		= txx9tmr_set_next_event,
	},
};

static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
{
	struct txx9_clock_event_device *txx9_cd = dev_id;
	struct clock_event_device *cd = &txx9_cd->cd;
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

static struct irqaction txx9tmr_irq = {
	.handler	= txx9tmr_interrupt,
	.flags		= IRQF_PERCPU | IRQF_TIMER,
	.name		= "txx9tmr",
	.dev_id		= &txx9_clock_event_device,
};

void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
				 unsigned int imbusclk)
{
	struct clock_event_device *cd = &txx9_clock_event_device.cd;
	struct txx9_tmr_reg __iomem *tmrptr;

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	txx9tmr_stop_and_clear(tmrptr);
	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	__raw_writel(0, &tmrptr->itmr);
	txx9_clock_event_device.tmrptr = tmrptr;

	clockevent_set_clock(cd, TIMER_CLK(imbusclk));
	cd->max_delta_ns =
		clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
	cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
	cd->irq = irq;
	cd->cpumask = cpumask_of(0),
	clockevents_register_device(cd);
	setup_irq(irq, &txx9tmr_irq);
	printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
	       baseaddr, irq);
}

void __init txx9_tmr_init(unsigned long baseaddr)
{
	struct txx9_tmr_reg __iomem *tmrptr;

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	/* Start once to make CounterResetEnable effective */
	__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	/* Stop and reset the counter */
	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
	__raw_writel(0, &tmrptr->tisr);
	__raw_writel(0xffffffff, &tmrptr->cpra);
	__raw_writel(0, &tmrptr->itmr);
	__raw_writel(0, &tmrptr->ccdr);
	__raw_writel(0, &tmrptr->pgmr);
	iounmap(tmrptr);
}
Commit	Line	Data
229f773e AN	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Based on linux/arch/mips/kernel/cevt-r4k.c,
70342287	7	* linux/arch/mips/jmr3927/rbhma3100/setup.c
229f773e AN	8	*
	9	* Copyright 2001 MontaVista Software Inc.
	10	* Copyright (C) 2000-2001 Toshiba Corporation
	11	* Copyright (C) 2007 MIPS Technologies, Inc.
	12	* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
	13	*/
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
ca4d3e67	16	#include <linux/irq.h>
a6071af9	17	#include <linux/sched_clock.h>
229f773e AN	18	#include <asm/time.h>
	19	#include <asm/txx9tmr.h>
	20
	21	#define TCR_BASE (TXx9_TMTCR_CCDE \| TXx9_TMTCR_CRE \| TXx9_TMTCR_TMODE_ITVL)
	22	#define TIMER_CCD 0 /* 1/2 */
	23	#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
	24
a43da03c AN	25	struct txx9_clocksource {
	26	struct clocksource cs;
	27	struct txx9_tmr_reg __iomem *tmrptr;
	28	};
229f773e	29
8e19608e	30	static cycle_t txx9_cs_read(struct clocksource *cs)
229f773e	31	{
a43da03c AN	32	struct txx9_clocksource *txx9_cs =
	33	container_of(cs, struct txx9_clocksource, cs);
	34	return __raw_readl(&txx9_cs->tmrptr->trr);
229f773e AN	35	}
	36
	37	/* Use 1 bit smaller width to use full bits in that width */
	38	#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
	39
a43da03c AN	40	static struct txx9_clocksource txx9_clocksource = {
	41	.cs = {
	42	.name = "TXx9",
	43	.rating = 200,
	44	.read = txx9_cs_read,
	45	.mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
	46	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	47	},
229f773e AN	48	};
229f773e AN	49
a6071af9 DCZ	50	static u64 notrace txx9_read_sched_clock(void)
	51	{
	52	return __raw_readl(&txx9_clocksource.tmrptr->trr);
	53	}
	54
229f773e AN	55	void __init txx9_clocksource_init(unsigned long baseaddr,
	56	unsigned int imbusclk)
	57	{
	58	struct txx9_tmr_reg __iomem *tmrptr;
	59
75c4fd8c	60	clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
229f773e AN	61
	62	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	63	__raw_writel(TCR_BASE, &tmrptr->tcr);
	64	__raw_writel(0, &tmrptr->tisr);
	65	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	66	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
	67	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
	68	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
a43da03c	69	txx9_clocksource.tmrptr = tmrptr;
a6071af9 DCZ	70
	71	sched_clock_register(txx9_read_sched_clock, TXX9_CLOCKSOURCE_BITS,
	72	TIMER_CLK(imbusclk));
229f773e AN	73	}
229f773e AN	74
a43da03c AN	75	struct txx9_clock_event_device {
	76	struct clock_event_device cd;
	77	struct txx9_tmr_reg __iomem *tmrptr;
	78	};
229f773e AN	79
	80	static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
	81	{
	82	/* stop and reset counter */
	83	__raw_writel(TCR_BASE, &tmrptr->tcr);
	84	/* clear pending interrupt */
	85	__raw_writel(0, &tmrptr->tisr);
	86	}
	87
d199da55	88	static int txx9tmr_set_state_periodic(struct clock_event_device *evt)
229f773e	89	{
a43da03c AN	90	struct txx9_clock_event_device *txx9_cd =
	91	container_of(evt, struct txx9_clock_event_device, cd);
	92	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e AN	93
229f773e AN	94	txx9tmr_stop_and_clear(tmrptr);
d199da55 VK	95
	96	__raw_writel(TXx9_TMITMR_TIIE \| TXx9_TMITMR_TZCE, &tmrptr->itmr);
	97	/* start timer */
	98	__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift,
	99	&tmrptr->cpra);
	100	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	101	return 0;
	102	}
	103
	104	static int txx9tmr_set_state_oneshot(struct clock_event_device *evt)
	105	{
	106	struct txx9_clock_event_device *txx9_cd =
	107	container_of(evt, struct txx9_clock_event_device, cd);
	108	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
	109
	110	txx9tmr_stop_and_clear(tmrptr);
	111	__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
	112	return 0;
	113	}
	114
	115	static int txx9tmr_set_state_shutdown(struct clock_event_device *evt)
	116	{
	117	struct txx9_clock_event_device *txx9_cd =
	118	container_of(evt, struct txx9_clock_event_device, cd);
	119	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
	120
	121	txx9tmr_stop_and_clear(tmrptr);
	122	__raw_writel(0, &tmrptr->itmr);
	123	return 0;
	124	}
	125
	126	static int txx9tmr_tick_resume(struct clock_event_device *evt)
	127	{
	128	struct txx9_clock_event_device *txx9_cd =
	129	container_of(evt, struct txx9_clock_event_device, cd);
	130	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
	131
	132	txx9tmr_stop_and_clear(tmrptr);
	133	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	134	__raw_writel(0, &tmrptr->itmr);
	135	return 0;
229f773e AN	136	}
	137
	138	static int txx9tmr_set_next_event(unsigned long delta,
	139	struct clock_event_device *evt)
	140	{
a43da03c AN	141	struct txx9_clock_event_device *txx9_cd =
	142	container_of(evt, struct txx9_clock_event_device, cd);
	143	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e AN	144
	145	txx9tmr_stop_and_clear(tmrptr);
	146	/* start timer */
	147	__raw_writel(delta, &tmrptr->cpra);
	148	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	149	return 0;
	150	}
	151
a43da03c AN	152	static struct txx9_clock_event_device txx9_clock_event_device = {
a43da03c AN	153	.cd = {
d199da55 VK	154	.name = "TXx9",
	155	.features = CLOCK_EVT_FEAT_PERIODIC \|
	156	CLOCK_EVT_FEAT_ONESHOT,
	157	.rating = 200,
	158	.set_state_shutdown = txx9tmr_set_state_shutdown,
	159	.set_state_periodic = txx9tmr_set_state_periodic,
	160	.set_state_oneshot = txx9tmr_set_state_oneshot,
	161	.tick_resume = txx9tmr_tick_resume,
	162	.set_next_event = txx9tmr_set_next_event,
a43da03c	163	},
229f773e AN	164	};
	165
	166	static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
	167	{
a43da03c AN	168	struct txx9_clock_event_device *txx9_cd = dev_id;
	169	struct clock_event_device *cd = &txx9_cd->cd;
	170	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e	171
70342287	172	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
229f773e AN	173	cd->event_handler(cd);
	174	return IRQ_HANDLED;
	175	}
	176
	177	static struct irqaction txx9tmr_irq = {
	178	.handler = txx9tmr_interrupt,
8b5690f8	179	.flags = IRQF_PERCPU \| IRQF_TIMER,
229f773e	180	.name = "txx9tmr",
a43da03c	181	.dev_id = &txx9_clock_event_device,
229f773e AN	182	};
	183
	184	void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
	185	unsigned int imbusclk)
	186	{
a43da03c	187	struct clock_event_device *cd = &txx9_clock_event_device.cd;
229f773e AN	188	struct txx9_tmr_reg __iomem *tmrptr;
	189
	190	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	191	txx9tmr_stop_and_clear(tmrptr);
	192	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	193	__raw_writel(0, &tmrptr->itmr);
a43da03c	194	txx9_clock_event_device.tmrptr = tmrptr;
229f773e AN	195
	196	clockevent_set_clock(cd, TIMER_CLK(imbusclk));
	197	cd->max_delta_ns =
	198	clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
	199	cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
	200	cd->irq = irq;
320ab2b0	201	cd->cpumask = cpumask_of(0),
229f773e AN	202	clockevents_register_device(cd);
	203	setup_irq(irq, &txx9tmr_irq);
	204	printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
	205	baseaddr, irq);
	206	}
	207
	208	void __init txx9_tmr_init(unsigned long baseaddr)
	209	{
	210	struct txx9_tmr_reg __iomem *tmrptr;
	211
	212	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
8986d2f5 AN	213	/* Start once to make CounterResetEnable effective */
	214	__raw_writel(TXx9_TMTCR_CRE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	215	/* Stop and reset the counter */
229f773e AN	216	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
	217	__raw_writel(0, &tmrptr->tisr);
	218	__raw_writel(0xffffffff, &tmrptr->cpra);
	219	__raw_writel(0, &tmrptr->itmr);
	220	__raw_writel(0, &tmrptr->ccdr);
	221	__raw_writel(0, &tmrptr->pgmr);
	222	iounmap(tmrptr);
	223	}