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MIPS: Add IEEE Std 754 conformance mode selection
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
912708c2 355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
912708c2
MC		 369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
97f4ad29
MC		 373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
9267a30d
MSJ		 412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = &current_cpu_data;
415
69f24d17 416 switch (current_cpu_type()) {
9267a30d
MSJ		 417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 420 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
1da177e4
LT		 431void __init check_bugs32(void)
432{
9267a30d 433 check_errata();
1da177e4
LT		 434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
c094c99e
RM		 458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
91dfc423
GR		 464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
5b7efa89 467 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 468 back_to_back_c0_hazard();
5b7efa89 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 470#endif
471}
472
078a55fc 473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
1990e542 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 486 break;
487
8b8aa636
LY		 488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
a96102be
SH		 495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 501 break;
502 }
503}
504
078a55fc 505static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 506 "Unsupported ISA type, c0.config0: %d.";
507
cf0a8aa0
MC		 508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
912708c2 534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 535{
20a7f7e5 536 unsigned int config;
d83b0e82
JH		 537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
542 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 543 config = read_c0_config6();
cf0a8aa0 544 /* Clear the old probability value */
20a7f7e5 545 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 546 if (enable)
547 /* Enable FTLB */
20a7f7e5 548 write_c0_config6(config |
cf0a8aa0
MC		 549 (calculate_ftlb_probability(c)
550 << MIPS_CONF6_FTLBP_SHIFT)
551 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 552 else
553 /* Disable FTLB */
20a7f7e5
MC		 554 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
555 break;
556 case CPU_I6400:
557 /* I6400 & related cores use Config7 to configure FTLB */
558 config = read_c0_config7();
559 /* Clear the old probability value */
560 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
561 write_c0_config7(config | (calculate_ftlb_probability(c)
562 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 563 break;
912708c2
MC		 564 default:
565 return 1;
75b5b5e0 566 }
912708c2
MC		 567
568 return 0;
75b5b5e0
LY		 569}
570
2fa36399
KC		 571static inline unsigned int decode_config0(struct cpuinfo_mips *c)
572{
573 unsigned int config0;
2f6f3136 574 int isa, mt;
2fa36399
KC		 575
576 config0 = read_c0_config();
577
75b5b5e0
LY		 578 /*
579 * Look for Standard TLB or Dual VTLB and FTLB
580 */
2f6f3136
JH		 581 mt = config0 & MIPS_CONF_MT;
582 if (mt == MIPS_CONF_MT_TLB)
2fa36399 583 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 584 else if (mt == MIPS_CONF_MT_FTLB)
585 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 586
2fa36399
KC		 587 isa = (config0 & MIPS_CONF_AT) >> 13;
588 switch (isa) {
589 case 0:
590 switch ((config0 & MIPS_CONF_AR) >> 10) {
591 case 0:
a96102be 592 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 593 break;
594 case 1:
a96102be 595 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 596 break;
8b8aa636
LY		 597 case 2:
598 set_isa(c, MIPS_CPU_ISA_M32R6);
599 break;
2fa36399
KC		 600 default:
601 goto unknown;
602 }
603 break;
604 case 2:
605 switch ((config0 & MIPS_CONF_AR) >> 10) {
606 case 0:
a96102be 607 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 608 break;
609 case 1:
a96102be 610 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 611 break;
8b8aa636
LY		 612 case 2:
613 set_isa(c, MIPS_CPU_ISA_M64R6);
614 break;
2fa36399
KC		 615 default:
616 goto unknown;
617 }
618 break;
619 default:
620 goto unknown;
621 }
622
623 return config0 & MIPS_CONF_M;
624
625unknown:
626 panic(unknown_isa, config0);
627}
628
629static inline unsigned int decode_config1(struct cpuinfo_mips *c)
630{
631 unsigned int config1;
632
633 config1 = read_c0_config1();
634
635 if (config1 & MIPS_CONF1_MD)
636 c->ases |= MIPS_ASE_MDMX;
637 if (config1 & MIPS_CONF1_WR)
638 c->options |= MIPS_CPU_WATCH;
639 if (config1 & MIPS_CONF1_CA)
640 c->ases |= MIPS_ASE_MIPS16;
641 if (config1 & MIPS_CONF1_EP)
642 c->options |= MIPS_CPU_EJTAG;
643 if (config1 & MIPS_CONF1_FP) {
644 c->options |= MIPS_CPU_FPU;
645 c->options |= MIPS_CPU_32FPR;
646 }
75b5b5e0 647 if (cpu_has_tlb) {
2fa36399 648 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 649 c->tlbsizevtlb = c->tlbsize;
650 c->tlbsizeftlbsets = 0;
651 }
2fa36399
KC		 652
653 return config1 & MIPS_CONF_M;
654}
655
656static inline unsigned int decode_config2(struct cpuinfo_mips *c)
657{
658 unsigned int config2;
659
660 config2 = read_c0_config2();
661
662 if (config2 & MIPS_CONF2_SL)
663 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
664
665 return config2 & MIPS_CONF_M;
666}
667
668static inline unsigned int decode_config3(struct cpuinfo_mips *c)
669{
670 unsigned int config3;
671
672 config3 = read_c0_config3();
673
b2ab4f08 674 if (config3 & MIPS_CONF3_SM) {
2fa36399 675 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 676 c->options |= MIPS_CPU_RIXI;
677 }
678 if (config3 & MIPS_CONF3_RXI)
679 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 680 if (config3 & MIPS_CONF3_DSP)
681 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 682 if (config3 & MIPS_CONF3_DSP2P)
683 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 684 if (config3 & MIPS_CONF3_VINT)
685 c->options |= MIPS_CPU_VINT;
686 if (config3 & MIPS_CONF3_VEIC)
687 c->options |= MIPS_CPU_VEIC;
688 if (config3 & MIPS_CONF3_MT)
689 c->ases |= MIPS_ASE_MIPSMT;
690 if (config3 & MIPS_CONF3_ULRI)
691 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 692 if (config3 & MIPS_CONF3_ISA)
693 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 694 if (config3 & MIPS_CONF3_VZ)
695 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 696 if (config3 & MIPS_CONF3_SC)
697 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 698 if (config3 & MIPS_CONF3_MSA)
699 c->ases |= MIPS_ASE_MSA;
cab25bc7 700 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 701 c->htw_seq = 0;
3d528b32 702 c->options |= MIPS_CPU_HTW;
ed4cbc81 703 }
9b3274bd
JH		 704 if (config3 & MIPS_CONF3_CDMM)
705 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 706 if (config3 & MIPS_CONF3_SP)
707 c->options |= MIPS_CPU_SP;
2fa36399
KC		 708
709 return config3 & MIPS_CONF_M;
710}
711
712static inline unsigned int decode_config4(struct cpuinfo_mips *c)
713{
714 unsigned int config4;
75b5b5e0
LY		 715 unsigned int newcf4;
716 unsigned int mmuextdef;
717 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 718
719 config4 = read_c0_config4();
720
1745c1ef
LY		 721 if (cpu_has_tlb) {
722 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
723 c->options |= MIPS_CPU_TLBINV;
43d104db 724
e87569cd 725 /*
43d104db
JH		 726 * R6 has dropped the MMUExtDef field from config4.
727 * On R6 the fields always describe the FTLB, and only if it is
728 * present according to Config.MT.
e87569cd 729 */
43d104db
JH		 730 if (!cpu_has_mips_r6)
731 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
732 else if (cpu_has_ftlb)
e87569cd
MC		 733 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
734 else
43d104db 735 mmuextdef = 0;
e87569cd 736
75b5b5e0
LY		 737 switch (mmuextdef) {
738 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
739 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
740 c->tlbsizevtlb = c->tlbsize;
741 break;
742 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
743 c->tlbsizevtlb +=
744 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
745 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
746 c->tlbsize = c->tlbsizevtlb;
747 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
748 /* fall through */
749 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 750 if (mips_ftlb_disabled)
751 break;
75b5b5e0
LY		 752 newcf4 = (config4 & ~ftlb_page) |
753 (page_size_ftlb(mmuextdef) <<
754 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
755 write_c0_config4(newcf4);
756 back_to_back_c0_hazard();
757 config4 = read_c0_config4();
758 if (config4 != newcf4) {
759 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
760 PAGE_SIZE, config4);
761 /* Switch FTLB off */
762 set_ftlb_enable(c, 0);
763 break;
764 }
765 c->tlbsizeftlbsets = 1 <<
766 ((config4 & MIPS_CONF4_FTLBSETS) >>
767 MIPS_CONF4_FTLBSETS_SHIFT);
768 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
769 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
770 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 771 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 772 break;
773 }
1745c1ef
LY		 774 }
775
2fa36399
KC		 776 c->kscratch_mask = (config4 >> 16) & 0xff;
777
778 return config4 & MIPS_CONF_M;
779}
780
8b8a7634
RB		 781static inline unsigned int decode_config5(struct cpuinfo_mips *c)
782{
783 unsigned int config5;
784
785 config5 = read_c0_config5();
d175ed2b 786 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 787 write_c0_config5(config5);
788
49016748
MC		 789 if (config5 & MIPS_CONF5_EVA)
790 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 791 if (config5 & MIPS_CONF5_MRP)
792 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 793 if (config5 & MIPS_CONF5_LLB)
794 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 795#ifdef CONFIG_XPA
796 if (config5 & MIPS_CONF5_MVH)
797 c->options |= MIPS_CPU_XPA;
798#endif
49016748 799
8b8a7634
RB		 800 return config5 & MIPS_CONF_M;
801}
802
078a55fc 803static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 804{
805 int ok;
806
807 /* MIPS32 or MIPS64 compliant CPU. */
808 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
809 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
810
811 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
812
97f4ad29
MC		 813 /* Enable FTLB if present and not disabled */
814 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 815
2fa36399 816 ok = decode_config0(c); /* Read Config registers. */
70342287 817 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 818 if (ok)
819 ok = decode_config1(c);
820 if (ok)
821 ok = decode_config2(c);
822 if (ok)
823 ok = decode_config3(c);
824 if (ok)
825 ok = decode_config4(c);
8b8a7634
RB		 826 if (ok)
827 ok = decode_config5(c);
2fa36399
KC		 828
829 mips_probe_watch_registers(c);
830
6575b1d4
LY		 831 if (cpu_has_rixi) {
832 /* Enable the RIXI exceptions */
a5770df0 833 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 834 back_to_back_c0_hazard();
835 /* Verify the IEC bit is set */
836 if (read_c0_pagegrain() & PG_IEC)
837 c->options |= MIPS_CPU_RIXIEX;
838 }
839
0ee958e1 840#ifndef CONFIG_MIPS_CPS
8b8aa636 841 if (cpu_has_mips_r2_r6) {
45b585c8 842 c->core = get_ebase_cpunum();
30ee615b
PB		 843 if (cpu_has_mipsmt)
844 c->core >>= fls(core_nvpes()) - 1;
845 }
0ee958e1 846#endif
2fa36399
KC		 847}
848
02cf2119 849#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 850 | MIPS_CPU_COUNTER)
851
cea7e2df 852static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 853{
8ff374b9 854 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 855 case PRID_IMP_R2000:
856 c->cputype = CPU_R2000;
cea7e2df 857 __cpu_name[cpu] = "R2000";
9b26616c 858 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 859 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 860 MIPS_CPU_NOFPUEX;
1da177e4
LT		 861 if (__cpu_has_fpu())
862 c->options |= MIPS_CPU_FPU;
863 c->tlbsize = 64;
864 break;
865 case PRID_IMP_R3000:
8ff374b9 866 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 867 if (cpu_has_confreg()) {
1da177e4 868 c->cputype = CPU_R3081E;
cea7e2df
RB		 869 __cpu_name[cpu] = "R3081";
870 } else {
1da177e4 871 c->cputype = CPU_R3000A;
cea7e2df
RB		 872 __cpu_name[cpu] = "R3000A";
873 }
cea7e2df 874 } else {
1da177e4 875 c->cputype = CPU_R3000;
cea7e2df
RB		 876 __cpu_name[cpu] = "R3000";
877 }
9b26616c 878 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 879 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 880 MIPS_CPU_NOFPUEX;
1da177e4
LT		 881 if (__cpu_has_fpu())
882 c->options |= MIPS_CPU_FPU;
883 c->tlbsize = 64;
884 break;
885 case PRID_IMP_R4000:
886 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 887 if ((c->processor_id & PRID_REV_MASK) >=
888 PRID_REV_R4400) {
1da177e4 889 c->cputype = CPU_R4400PC;
cea7e2df
RB		 890 __cpu_name[cpu] = "R4400PC";
891 } else {
1da177e4 892 c->cputype = CPU_R4000PC;
cea7e2df
RB		 893 __cpu_name[cpu] = "R4000PC";
894 }
1da177e4 895 } else {
7f177a52
MR		 896 int cca = read_c0_config() & CONF_CM_CMASK;
897 int mc;
898
899 /*
900 * SC and MC versions can't be reliably told apart,
901 * but only the latter support coherent caching
902 * modes so assume the firmware has set the KSEG0
903 * coherency attribute reasonably (if uncached, we
904 * assume SC).
905 */
906 switch (cca) {
907 case CONF_CM_CACHABLE_CE:
908 case CONF_CM_CACHABLE_COW:
909 case CONF_CM_CACHABLE_CUW:
910 mc = 1;
911 break;
912 default:
913 mc = 0;
914 break;
915 }
8ff374b9
MR		 916 if ((c->processor_id & PRID_REV_MASK) >=
917 PRID_REV_R4400) {
7f177a52
MR		 918 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
919 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 920 } else {
7f177a52
MR		 921 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
922 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 923 }
1da177e4
LT		 924 }
925
a96102be 926 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 927 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 928 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 929 MIPS_CPU_WATCH | MIPS_CPU_VCE |
930 MIPS_CPU_LLSC;
1da177e4
LT		 931 c->tlbsize = 48;
932 break;
933 case PRID_IMP_VR41XX:
9f91e506 934 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 935 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 936 c->options = R4K_OPTS;
937 c->tlbsize = 32;
1da177e4 938 switch (c->processor_id & 0xf0) {
1da177e4
LT		 939 case PRID_REV_VR4111:
940 c->cputype = CPU_VR4111;
cea7e2df 941 __cpu_name[cpu] = "NEC VR4111";
1da177e4 942 break;
1da177e4
LT		 943 case PRID_REV_VR4121:
944 c->cputype = CPU_VR4121;
cea7e2df 945 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 946 break;
947 case PRID_REV_VR4122:
cea7e2df 948 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 949 c->cputype = CPU_VR4122;
cea7e2df
RB		 950 __cpu_name[cpu] = "NEC VR4122";
951 } else {
1da177e4 952 c->cputype = CPU_VR4181A;
cea7e2df
RB		 953 __cpu_name[cpu] = "NEC VR4181A";
954 }
1da177e4
LT		 955 break;
956 case PRID_REV_VR4130:
cea7e2df 957 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 958 c->cputype = CPU_VR4131;
cea7e2df
RB		 959 __cpu_name[cpu] = "NEC VR4131";
960 } else {
1da177e4 961 c->cputype = CPU_VR4133;
9f91e506 962 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 963 __cpu_name[cpu] = "NEC VR4133";
964 }
1da177e4
LT		 965 break;
966 default:
967 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
968 c->cputype = CPU_VR41XX;
cea7e2df 969 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 970 break;
971 }
1da177e4
LT		 972 break;
973 case PRID_IMP_R4300:
974 c->cputype = CPU_R4300;
cea7e2df 975 __cpu_name[cpu] = "R4300";
a96102be 976 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 977 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 978 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 979 MIPS_CPU_LLSC;
1da177e4
LT		 980 c->tlbsize = 32;
981 break;
982 case PRID_IMP_R4600:
983 c->cputype = CPU_R4600;
cea7e2df 984 __cpu_name[cpu] = "R4600";
a96102be 985 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 986 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 987 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
988 MIPS_CPU_LLSC;
1da177e4
LT		 989 c->tlbsize = 48;
990 break;
991 #if 0
03751e79 992 case PRID_IMP_R4650:
1da177e4
LT		 993 /*
994 * This processor doesn't have an MMU, so it's not
995 * "real easy" to run Linux on it. It is left purely
996 * for documentation. Commented out because it shares
997 * it's c0_prid id number with the TX3900.
998 */
a3dddd56 999 c->cputype = CPU_R4650;
cea7e2df 1000 __cpu_name[cpu] = "R4650";
a96102be 1001 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1002 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1003 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1004 c->tlbsize = 48;
1da177e4
LT		 1005 break;
1006 #endif
1007 case PRID_IMP_TX39:
9b26616c 1008 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1009 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1010
1011 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1012 c->cputype = CPU_TX3927;
cea7e2df 1013 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1014 c->tlbsize = 64;
1015 } else {
8ff374b9 1016 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1017 case PRID_REV_TX3912:
1018 c->cputype = CPU_TX3912;
cea7e2df 1019 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1020 c->tlbsize = 32;
1021 break;
1022 case PRID_REV_TX3922:
1023 c->cputype = CPU_TX3922;
cea7e2df 1024 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1025 c->tlbsize = 64;
1026 break;
1da177e4
LT		 1027 }
1028 }
1029 break;
1030 case PRID_IMP_R4700:
1031 c->cputype = CPU_R4700;
cea7e2df 1032 __cpu_name[cpu] = "R4700";
a96102be 1033 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1034 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1035 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1036 MIPS_CPU_LLSC;
1da177e4
LT		 1037 c->tlbsize = 48;
1038 break;
1039 case PRID_IMP_TX49:
1040 c->cputype = CPU_TX49XX;
cea7e2df 1041 __cpu_name[cpu] = "R49XX";
a96102be 1042 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1043 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1044 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1045 if (!(c->processor_id & 0x08))
1046 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1047 c->tlbsize = 48;
1048 break;
1049 case PRID_IMP_R5000:
1050 c->cputype = CPU_R5000;
cea7e2df 1051 __cpu_name[cpu] = "R5000";
a96102be 1052 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1053 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1054 MIPS_CPU_LLSC;
1da177e4
LT		 1055 c->tlbsize = 48;
1056 break;
1057 case PRID_IMP_R5432:
1058 c->cputype = CPU_R5432;
cea7e2df 1059 __cpu_name[cpu] = "R5432";
a96102be 1060 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1061 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1062 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1063 c->tlbsize = 48;
1064 break;
1065 case PRID_IMP_R5500:
1066 c->cputype = CPU_R5500;
cea7e2df 1067 __cpu_name[cpu] = "R5500";
a96102be 1068 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1069 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1070 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1071 c->tlbsize = 48;
1072 break;
1073 case PRID_IMP_NEVADA:
1074 c->cputype = CPU_NEVADA;
cea7e2df 1075 __cpu_name[cpu] = "Nevada";
a96102be 1076 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1077 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1078 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1079 c->tlbsize = 48;
1080 break;
1081 case PRID_IMP_R6000:
1082 c->cputype = CPU_R6000;
cea7e2df 1083 __cpu_name[cpu] = "R6000";
a96102be 1084 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1085 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1086 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1087 MIPS_CPU_LLSC;
1da177e4
LT		 1088 c->tlbsize = 32;
1089 break;
1090 case PRID_IMP_R6000A:
1091 c->cputype = CPU_R6000A;
cea7e2df 1092 __cpu_name[cpu] = "R6000A";
a96102be 1093 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1094 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1095 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1096 MIPS_CPU_LLSC;
1da177e4
LT		 1097 c->tlbsize = 32;
1098 break;
1099 case PRID_IMP_RM7000:
1100 c->cputype = CPU_RM7000;
cea7e2df 1101 __cpu_name[cpu] = "RM7000";
a96102be 1102 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1103 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1104 MIPS_CPU_LLSC;
1da177e4 1105 /*
70342287 1106 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1107 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1108 * entries.
1109 *
70342287
RB		 1110 * 29 1 => 64 entry JTLB
1111 * 0 => 48 entry JTLB
1da177e4
LT		 1112 */
1113 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1114 break;
1115 case PRID_IMP_R8000:
1116 c->cputype = CPU_R8000;
cea7e2df 1117 __cpu_name[cpu] = "RM8000";
a96102be 1118 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1119 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1120 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1121 MIPS_CPU_LLSC;
1da177e4
LT		 1122 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1123 break;
1124 case PRID_IMP_R10000:
1125 c->cputype = CPU_R10000;
cea7e2df 1126 __cpu_name[cpu] = "R10000";
a96102be 1127 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1128 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1129 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1130 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1131 MIPS_CPU_LLSC;
1da177e4
LT		 1132 c->tlbsize = 64;
1133 break;
1134 case PRID_IMP_R12000:
1135 c->cputype = CPU_R12000;
cea7e2df 1136 __cpu_name[cpu] = "R12000";
a96102be 1137 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1138 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1139 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1140 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1141 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1142 c->tlbsize = 64;
1143 break;
44d921b2 1144 case PRID_IMP_R14000:
30577391
JK		 1145 if (((c->processor_id >> 4) & 0x0f) > 2) {
1146 c->cputype = CPU_R16000;
1147 __cpu_name[cpu] = "R16000";
1148 } else {
1149 c->cputype = CPU_R14000;
1150 __cpu_name[cpu] = "R14000";
1151 }
a96102be 1152 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1153 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1154 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1155 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1156 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1157 c->tlbsize = 64;
1158 break;
26859198 1159 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1160 switch (c->processor_id & PRID_REV_MASK) {
1161 case PRID_REV_LOONGSON2E:
c579d310
HC		 1162 c->cputype = CPU_LOONGSON2;
1163 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1164 set_elf_platform(cpu, "loongson2e");
7352c8b1 1165 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1166 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1167 break;
1168 case PRID_REV_LOONGSON2F:
c579d310
HC		 1169 c->cputype = CPU_LOONGSON2;
1170 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1171 set_elf_platform(cpu, "loongson2f");
7352c8b1 1172 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1173 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1174 break;
c579d310
HC		 1175 case PRID_REV_LOONGSON3A:
1176 c->cputype = CPU_LOONGSON3;
1177 __cpu_name[cpu] = "ICT Loongson-3";
1178 set_elf_platform(cpu, "loongson3a");
7352c8b1 1179 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1180 break;
e7841be5
HC		 1181 case PRID_REV_LOONGSON3B_R1:
1182 case PRID_REV_LOONGSON3B_R2:
1183 c->cputype = CPU_LOONGSON3;
1184 __cpu_name[cpu] = "ICT Loongson-3";
1185 set_elf_platform(cpu, "loongson3b");
7352c8b1 1186 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1187 break;
5aac1e8a
RM		 1188 }
1189
2a21c730
FZ		 1190 c->options = R4K_OPTS |
1191 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1192 MIPS_CPU_32FPR;
1193 c->tlbsize = 64;
cc94ea31 1194 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1195 break;
26859198 1196 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1197 decode_configs(c);
b4672d37 1198
2fa36399 1199 c->cputype = CPU_LOONGSON1;
1da177e4 1200
2fa36399
KC		 1201 switch (c->processor_id & PRID_REV_MASK) {
1202 case PRID_REV_LOONGSON1B:
1203 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1204 break;
b4672d37 1205 }
4194318c 1206
2fa36399 1207 break;
1da177e4 1208 }
1da177e4
LT		 1209}
1210
cea7e2df 1211static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1212{
4f12b91d 1213 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1214 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1215 case PRID_IMP_QEMU_GENERIC:
1216 c->writecombine = _CACHE_UNCACHED;
1217 c->cputype = CPU_QEMU_GENERIC;
1218 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1219 break;
1da177e4
LT		 1220 case PRID_IMP_4KC:
1221 c->cputype = CPU_4KC;
4f12b91d 1222 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1223 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1224 break;
1225 case PRID_IMP_4KEC:
2b07bd02
RB		 1226 case PRID_IMP_4KECR2:
1227 c->cputype = CPU_4KEC;
4f12b91d 1228 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1229 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1230 break;
1da177e4 1231 case PRID_IMP_4KSC:
8afcb5d8 1232 case PRID_IMP_4KSD:
1da177e4 1233 c->cputype = CPU_4KSC;
4f12b91d 1234 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1235 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1236 break;
1237 case PRID_IMP_5KC:
1238 c->cputype = CPU_5KC;
4f12b91d 1239 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1240 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1241 break;
78d4803f
LY		 1242 case PRID_IMP_5KE:
1243 c->cputype = CPU_5KE;
4f12b91d 1244 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1245 __cpu_name[cpu] = "MIPS 5KE";
1246 break;
1da177e4
LT		 1247 case PRID_IMP_20KC:
1248 c->cputype = CPU_20KC;
4f12b91d 1249 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1250 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1251 break;
1252 case PRID_IMP_24K:
1253 c->cputype = CPU_24K;
4f12b91d 1254 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1255 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1256 break;
42f3caef
JC		 1257 case PRID_IMP_24KE:
1258 c->cputype = CPU_24K;
4f12b91d 1259 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1260 __cpu_name[cpu] = "MIPS 24KEc";
1261 break;
1da177e4
LT		 1262 case PRID_IMP_25KF:
1263 c->cputype = CPU_25KF;
4f12b91d 1264 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1265 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1266 break;
bbc7f22f
RB		 1267 case PRID_IMP_34K:
1268 c->cputype = CPU_34K;
4f12b91d 1269 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1270 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1271 break;
c620953c
CD		 1272 case PRID_IMP_74K:
1273 c->cputype = CPU_74K;
4f12b91d 1274 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1275 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1276 break;
113c62d9
SH		 1277 case PRID_IMP_M14KC:
1278 c->cputype = CPU_M14KC;
4f12b91d 1279 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1280 __cpu_name[cpu] = "MIPS M14Kc";
1281 break;
f8fa4811
SH		 1282 case PRID_IMP_M14KEC:
1283 c->cputype = CPU_M14KEC;
4f12b91d 1284 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1285 __cpu_name[cpu] = "MIPS M14KEc";
1286 break;
39b8d525
RB		 1287 case PRID_IMP_1004K:
1288 c->cputype = CPU_1004K;
4f12b91d 1289 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1290 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1291 break;
006a851b 1292 case PRID_IMP_1074K:
442e14a2 1293 c->cputype = CPU_1074K;
4f12b91d 1294 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1295 __cpu_name[cpu] = "MIPS 1074Kc";
1296 break;
b5f065e7
LY		 1297 case PRID_IMP_INTERAPTIV_UP:
1298 c->cputype = CPU_INTERAPTIV;
1299 __cpu_name[cpu] = "MIPS interAptiv";
1300 break;
1301 case PRID_IMP_INTERAPTIV_MP:
1302 c->cputype = CPU_INTERAPTIV;
1303 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1304 break;
b0d4d300
LY		 1305 case PRID_IMP_PROAPTIV_UP:
1306 c->cputype = CPU_PROAPTIV;
1307 __cpu_name[cpu] = "MIPS proAptiv";
1308 break;
1309 case PRID_IMP_PROAPTIV_MP:
1310 c->cputype = CPU_PROAPTIV;
1311 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1312 break;
829dcc0a
JH		 1313 case PRID_IMP_P5600:
1314 c->cputype = CPU_P5600;
1315 __cpu_name[cpu] = "MIPS P5600";
1316 break;
e57f9a2d
MC		 1317 case PRID_IMP_I6400:
1318 c->cputype = CPU_I6400;
1319 __cpu_name[cpu] = "MIPS I6400";
1320 break;
9943ed92
LY		 1321 case PRID_IMP_M5150:
1322 c->cputype = CPU_M5150;
1323 __cpu_name[cpu] = "MIPS M5150";
1324 break;
1da177e4 1325 }
0b6d497f 1326
75b5b5e0
LY		 1327 decode_configs(c);
1328
0b6d497f 1329 spram_config();
1da177e4
LT		 1330}
1331
cea7e2df 1332static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1333{
4194318c 1334 decode_configs(c);
8ff374b9 1335 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1336 case PRID_IMP_AU1_REV1:
1337 case PRID_IMP_AU1_REV2:
270717a8 1338 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1339 switch ((c->processor_id >> 24) & 0xff) {
1340 case 0:
cea7e2df 1341 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1342 break;
1343 case 1:
cea7e2df 1344 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1345 break;
1346 case 2:
cea7e2df 1347 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1348 break;
1349 case 3:
cea7e2df 1350 __cpu_name[cpu] = "Au1550";
1da177e4 1351 break;
e3ad1c23 1352 case 4:
cea7e2df 1353 __cpu_name[cpu] = "Au1200";
8ff374b9 1354 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1355 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1356 break;
1357 case 5:
cea7e2df 1358 __cpu_name[cpu] = "Au1210";
e3ad1c23 1359 break;
1da177e4 1360 default:
270717a8 1361 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1362 break;
1363 }
1da177e4
LT		 1364 break;
1365 }
1366}
1367
cea7e2df 1368static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1369{
4194318c 1370 decode_configs(c);
02cf2119 1371
4f12b91d 1372 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1373 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1374 case PRID_IMP_SB1:
1375 c->cputype = CPU_SB1;
cea7e2df 1376 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1377 /* FPU in pass1 is known to have issues. */
8ff374b9 1378 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1379 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1380 break;
93ce2f52
AI		 1381 case PRID_IMP_SB1A:
1382 c->cputype = CPU_SB1A;
cea7e2df 1383 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1384 break;
1da177e4
LT		 1385 }
1386}
1387
cea7e2df 1388static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1389{
4194318c 1390 decode_configs(c);
8ff374b9 1391 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1392 case PRID_IMP_SR71000:
1393 c->cputype = CPU_SR71000;
cea7e2df 1394 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1395 c->scache.ways = 8;
1396 c->tlbsize = 64;
1397 break;
1398 }
1399}
1400
cea7e2df 1401static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1402{
1403 decode_configs(c);
8ff374b9 1404 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1405 case PRID_IMP_PR4450:
1406 c->cputype = CPU_PR4450;
cea7e2df 1407 __cpu_name[cpu] = "Philips PR4450";
a96102be 1408 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1409 break;
bdf21b18
PP		 1410 }
1411}
1412
cea7e2df 1413static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1414{
1415 decode_configs(c);
8ff374b9 1416 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1417 case PRID_IMP_BMIPS32_REV4:
1418 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1419 c->cputype = CPU_BMIPS32;
1420 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1421 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1422 break;
1423 case PRID_IMP_BMIPS3300:
1424 case PRID_IMP_BMIPS3300_ALT:
1425 case PRID_IMP_BMIPS3300_BUG:
1426 c->cputype = CPU_BMIPS3300;
1427 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1428 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1429 break;
1430 case PRID_IMP_BMIPS43XX: {
8ff374b9 1431 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1432
1433 if (rev >= PRID_REV_BMIPS4380_LO &&
1434 rev <= PRID_REV_BMIPS4380_HI) {
1435 c->cputype = CPU_BMIPS4380;
1436 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1437 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1438 } else {
1439 c->cputype = CPU_BMIPS4350;
1440 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1441 set_elf_platform(cpu, "bmips4350");
602977b0 1442 }
0de663ef 1443 break;
602977b0
KC		 1444 }
1445 case PRID_IMP_BMIPS5000:
68e6a783 1446 case PRID_IMP_BMIPS5200:
602977b0
KC		 1447 c->cputype = CPU_BMIPS5000;
1448 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1449 set_elf_platform(cpu, "bmips5000");
602977b0 1450 c->options |= MIPS_CPU_ULRI;
0de663ef 1451 break;
1c0c13eb
AJ		 1452 }
1453}
1454
0dd4781b
DD		 1455static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1456{
1457 decode_configs(c);
8ff374b9 1458 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1459 case PRID_IMP_CAVIUM_CN38XX:
1460 case PRID_IMP_CAVIUM_CN31XX:
1461 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1462 c->cputype = CPU_CAVIUM_OCTEON;
1463 __cpu_name[cpu] = "Cavium Octeon";
1464 goto platform;
0dd4781b
DD		 1465 case PRID_IMP_CAVIUM_CN58XX:
1466 case PRID_IMP_CAVIUM_CN56XX:
1467 case PRID_IMP_CAVIUM_CN50XX:
1468 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1469 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1470 __cpu_name[cpu] = "Cavium Octeon+";
1471platform:
c094c99e 1472 set_elf_platform(cpu, "octeon");
0dd4781b 1473 break;
a1431b61 1474 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1475 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1476 case PRID_IMP_CAVIUM_CN66XX:
1477 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1478 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1479 c->cputype = CPU_CAVIUM_OCTEON2;
1480 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1481 set_elf_platform(cpu, "octeon2");
0e56b385 1482 break;
af04bb85
DD		 1483 case PRID_IMP_CAVIUM_CN70XX:
1484 case PRID_IMP_CAVIUM_CN78XX:
1485 c->cputype = CPU_CAVIUM_OCTEON3;
1486 __cpu_name[cpu] = "Cavium Octeon III";
1487 set_elf_platform(cpu, "octeon3");
1488 break;
0dd4781b
DD		 1489 default:
1490 printk(KERN_INFO "Unknown Octeon chip!\n");
1491 c->cputype = CPU_UNKNOWN;
1492 break;
1493 }
1494}
1495
83ccf69d
LPC		 1496static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1497{
1498 decode_configs(c);
1499 /* JZRISC does not implement the CP0 counter. */
1500 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1501 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1502 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1503 case PRID_IMP_JZRISC:
1504 c->cputype = CPU_JZRISC;
4f12b91d 1505 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1506 __cpu_name[cpu] = "Ingenic JZRISC";
1507 break;
1508 default:
1509 panic("Unknown Ingenic Processor ID!");
1510 break;
1511 }
1512}
1513
a7117c6b
J		 1514static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1515{
1516 decode_configs(c);
1517
8ff374b9 1518 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1519 c->cputype = CPU_ALCHEMY;
1520 __cpu_name[cpu] = "Au1300";
1521 /* following stuff is not for Alchemy */
1522 return;
1523 }
1524
70342287
RB		 1525 c->options = (MIPS_CPU_TLB |
1526 MIPS_CPU_4KEX |
a7117c6b 1527 MIPS_CPU_COUNTER |
70342287
RB		 1528 MIPS_CPU_DIVEC |
1529 MIPS_CPU_WATCH |
1530 MIPS_CPU_EJTAG |
a7117c6b
J		 1531 MIPS_CPU_LLSC);
1532
8ff374b9 1533 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1534 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1535 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1536 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1537 c->cputype = CPU_XLP;
1538 __cpu_name[cpu] = "Broadcom XLPII";
1539 break;
1540
2aa54b20
J		 1541 case PRID_IMP_NETLOGIC_XLP8XX:
1542 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1543 c->cputype = CPU_XLP;
1544 __cpu_name[cpu] = "Netlogic XLP";
1545 break;
1546
a7117c6b
J		 1547 case PRID_IMP_NETLOGIC_XLR732:
1548 case PRID_IMP_NETLOGIC_XLR716:
1549 case PRID_IMP_NETLOGIC_XLR532:
1550 case PRID_IMP_NETLOGIC_XLR308:
1551 case PRID_IMP_NETLOGIC_XLR532C:
1552 case PRID_IMP_NETLOGIC_XLR516C:
1553 case PRID_IMP_NETLOGIC_XLR508C:
1554 case PRID_IMP_NETLOGIC_XLR308C:
1555 c->cputype = CPU_XLR;
1556 __cpu_name[cpu] = "Netlogic XLR";
1557 break;
1558
1559 case PRID_IMP_NETLOGIC_XLS608:
1560 case PRID_IMP_NETLOGIC_XLS408:
1561 case PRID_IMP_NETLOGIC_XLS404:
1562 case PRID_IMP_NETLOGIC_XLS208:
1563 case PRID_IMP_NETLOGIC_XLS204:
1564 case PRID_IMP_NETLOGIC_XLS108:
1565 case PRID_IMP_NETLOGIC_XLS104:
1566 case PRID_IMP_NETLOGIC_XLS616B:
1567 case PRID_IMP_NETLOGIC_XLS608B:
1568 case PRID_IMP_NETLOGIC_XLS416B:
1569 case PRID_IMP_NETLOGIC_XLS412B:
1570 case PRID_IMP_NETLOGIC_XLS408B:
1571 case PRID_IMP_NETLOGIC_XLS404B:
1572 c->cputype = CPU_XLR;
1573 __cpu_name[cpu] = "Netlogic XLS";
1574 break;
1575
1576 default:
a3d4fb2d 1577 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1578 c->processor_id);
1579 c->cputype = CPU_XLR;
1580 break;
1581 }
1582
a3d4fb2d 1583 if (c->cputype == CPU_XLP) {
a96102be 1584 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1585 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1586 /* This will be updated again after all threads are woken up */
1587 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1588 } else {
a96102be 1589 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1590 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1591 }
7777b939 1592 c->kscratch_mask = 0xf;
a7117c6b
J		 1593}
1594
949e51be
DD		 1595#ifdef CONFIG_64BIT
1596/* For use by uaccess.h */
1597u64 __ua_limit;
1598EXPORT_SYMBOL(__ua_limit);
1599#endif
1600
9966db25 1601const char *__cpu_name[NR_CPUS];
874fd3b5 1602const char *__elf_platform;
9966db25 1603
078a55fc 1604void cpu_probe(void)
1da177e4
LT		 1605{
1606 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1607 unsigned int cpu = smp_processor_id();
1da177e4 1608
70342287 1609 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1610 c->fpu_id = FPIR_IMP_NONE;
1611 c->cputype = CPU_UNKNOWN;
4f12b91d 1612 c->writecombine = _CACHE_UNCACHED;
1da177e4 1613
9b26616c
MR		 1614 c->fpu_csr31 = FPU_CSR_RN;
1615 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1616
1da177e4 1617 c->processor_id = read_c0_prid();
8ff374b9 1618 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1619 case PRID_COMP_LEGACY:
cea7e2df 1620 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1621 break;
1622 case PRID_COMP_MIPS:
cea7e2df 1623 cpu_probe_mips(c, cpu);
1da177e4
LT		 1624 break;
1625 case PRID_COMP_ALCHEMY:
cea7e2df 1626 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1627 break;
1628 case PRID_COMP_SIBYTE:
cea7e2df 1629 cpu_probe_sibyte(c, cpu);
1da177e4 1630 break;
1c0c13eb 1631 case PRID_COMP_BROADCOM:
cea7e2df 1632 cpu_probe_broadcom(c, cpu);
1c0c13eb 1633 break;
1da177e4 1634 case PRID_COMP_SANDCRAFT:
cea7e2df 1635 cpu_probe_sandcraft(c, cpu);
1da177e4 1636 break;
a92b0588 1637 case PRID_COMP_NXP:
cea7e2df 1638 cpu_probe_nxp(c, cpu);
a3dddd56 1639 break;
0dd4781b
DD		 1640 case PRID_COMP_CAVIUM:
1641 cpu_probe_cavium(c, cpu);
1642 break;
252617a4
PB		 1643 case PRID_COMP_INGENIC_D0:
1644 case PRID_COMP_INGENIC_D1:
1645 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1646 cpu_probe_ingenic(c, cpu);
1647 break;
a7117c6b
J		 1648 case PRID_COMP_NETLOGIC:
1649 cpu_probe_netlogic(c, cpu);
1650 break;
1da177e4 1651 }
dec8b1ca 1652
cea7e2df
RB		 1653 BUG_ON(!__cpu_name[cpu]);
1654 BUG_ON(c->cputype == CPU_UNKNOWN);
1655
dec8b1ca
FBH		 1656 /*
1657 * Platform code can force the cpu type to optimize code
1658 * generation. In that case be sure the cpu type is correctly
1659 * manually setup otherwise it could trigger some nasty bugs.
1660 */
1661 BUG_ON(current_cpu_type() != c->cputype);
1662
0103d23f
KC		 1663 if (mips_fpu_disabled)
1664 c->options &= ~MIPS_CPU_FPU;
1665
1666 if (mips_dsp_disabled)
ee80f7c7 1667 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1668
3d528b32
MC		 1669 if (mips_htw_disabled) {
1670 c->options &= ~MIPS_CPU_HTW;
1671 write_c0_pwctl(read_c0_pwctl() &
1672 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1673 }
1674
7aecd5ca
MR		 1675 if (c->options & MIPS_CPU_FPU)
1676 cpu_set_fpu_opts(c);
1677 else
1678 cpu_set_nofpu_opts(c);
9966db25 1679
8d5ded16
JK		 1680 if (cpu_has_bp_ghist)
1681 write_c0_r10k_diag(read_c0_r10k_diag() |
1682 R10K_DIAG_E_GHIST);
1683
8b8aa636 1684 if (cpu_has_mips_r2_r6) {
f6771dbb 1685 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1686 /* R2 has Performance Counter Interrupt indicator */
1687 c->options |= MIPS_CPU_PCI;
1688 }
f6771dbb
RB		 1689 else
1690 c->srsets = 1;
91dfc423 1691
4c063034
PB		 1692 if (cpu_has_mips_r6)
1693 elf_hwcap |= HWCAP_MIPS_R6;
1694
a8ad1367 1695 if (cpu_has_msa) {
a5e9a69e 1696 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1697 WARN(c->msa_id & MSA_IR_WRPF,
1698 "Vector register partitioning unimplemented!");
3cc9fa7f 1699 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 1700 }
a5e9a69e 1701
91dfc423 1702 cpu_probe_vmbits(c);
949e51be
DD		 1703
1704#ifdef CONFIG_64BIT
1705 if (cpu == 0)
1706 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1707#endif
1da177e4
LT		 1708}
1709
078a55fc 1710void cpu_report(void)
1da177e4
LT		 1711{
1712 struct cpuinfo_mips *c = &current_cpu_data;
1713
d9f897c9
LY		 1714 pr_info("CPU%d revision is: %08x (%s)\n",
1715 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1716 if (c->options & MIPS_CPU_FPU)
9966db25 1717 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1718 if (cpu_has_msa)
1719 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1720}
Linux kernel - Deliverables
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