[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c

/*
 * Processor capabilities determination functions.
 *
 * Copyright (C) xxxx  the Anonymous
 * Copyright (C) 1994 - 2006 Ralf Baechle
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 * Copyright (C) 2001, 2004  MIPS Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/stddef.h>

#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

/*
 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 * the implementation of the "wait" feature differs between CPU families. This
 * points to the function that implements CPU specific wait.
 * The wait instruction stops the pipeline and reduces the power consumption of
 * the CPU very much.
 */
void (*cpu_wait)(void) = NULL;

static void r3081_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | R30XX_CONF_HALT);
}

static void r39xx_wait(void)
{
	local_irq_disable();
	if (!need_resched())
		write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
	local_irq_enable();
}

/*
 * There is a race when WAIT instruction executed with interrupt
 * enabled.
 * But it is implementation-dependent wheter the pipelie restarts when
 * a non-enabled interrupt is requested.
 */
static void r4k_wait(void)
{
	__asm__("	.set	mips3			\n"
		"	wait				\n"
		"	.set	mips0			\n");
}

/*
 * This variant is preferable as it allows testing need_resched and going to
 * sleep depending on the outcome atomically.  Unfortunately the "It is
 * implementation-dependent whether the pipeline restarts when a non-enabled
 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
 * using this version a gamble.
 */
static void r4k_wait_irqoff(void)
{
	local_irq_disable();
	if (!need_resched())
		__asm__("	.set	mips3		\n"
			"	wait			\n"
			"	.set	mips0		\n");
	local_irq_enable();
}

/* The Au1xxx wait is available only if using 32khz counter or
 * external timer source, but specifically not CP0 Counter. */
int allow_au1k_wait;

static void au1k_wait(void)
{
	/* using the wait instruction makes CP0 counter unusable */
	__asm__("	.set	mips3			\n"
		"	cache	0x14, 0(%0)		\n"
		"	cache	0x14, 32(%0)		\n"
		"	sync				\n"
		"	nop				\n"
		"	wait				\n"
		"	nop				\n"
		"	nop				\n"
		"	nop				\n"
		"	nop				\n"
		"	.set	mips0			\n"
		: : "r" (au1k_wait));
}

static int __initdata nowait = 0;

int __init wait_disable(char *s)
{
	nowait = 1;

	return 1;
}

__setup("nowait", wait_disable);

static inline void check_wait(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	if (nowait) {
		printk("Wait instruction disabled.\n");
		return;
	}

	switch (c->cputype) {
	case CPU_R3081:
	case CPU_R3081E:
		cpu_wait = r3081_wait;
		break;
	case CPU_TX3927:
		cpu_wait = r39xx_wait;
		break;
	case CPU_R4200:
/*	case CPU_R4300: */
	case CPU_R4600:
	case CPU_R4640:
	case CPU_R4650:
	case CPU_R4700:
	case CPU_R5000:
	case CPU_NEVADA:
	case CPU_RM7000:
	case CPU_4KC:
	case CPU_4KEC:
	case CPU_4KSC:
	case CPU_5KC:
/*	case CPU_20KC:*/
	case CPU_24K:
	case CPU_25KF:
	case CPU_34K:
	case CPU_74K:
 	case CPU_PR4450:
		cpu_wait = r4k_wait;
		break;
	case CPU_TX49XX:
		cpu_wait = r4k_wait_irqoff;
		break;
	case CPU_AU1000:
	case CPU_AU1100:
	case CPU_AU1500:
	case CPU_AU1550:
	case CPU_AU1200:
		if (allow_au1k_wait)
			cpu_wait = au1k_wait;
		break;
	case CPU_RM9000:
		if ((c->processor_id & 0x00ff) >= 0x40)
			cpu_wait = r4k_wait;
		break;
	default:
		break;
	}
}

void __init check_bugs32(void)
{
	check_wait();
}

/*
 * Probe whether cpu has config register by trying to play with
 * alternate cache bit and see whether it matters.
 * It's used by cpu_probe to distinguish between R3000A and R3081.
 */
static inline int cpu_has_confreg(void)
{
#ifdef CONFIG_CPU_R3000
	extern unsigned long r3k_cache_size(unsigned long);
	unsigned long size1, size2;
	unsigned long cfg = read_c0_conf();

	size1 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg ^ R30XX_CONF_AC);
	size2 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg);
	return size1 != size2;
#else
	return 0;
#endif
}

/*
 * Get the FPU Implementation/Revision.
 */
static inline unsigned long cpu_get_fpu_id(void)
{
	unsigned long tmp, fpu_id;

	tmp = read_c0_status();
	__enable_fpu();
	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	write_c0_status(tmp);
	return fpu_id;
}

/*
 * Check the CPU has an FPU the official way.
 */
static inline int __cpu_has_fpu(void)
{
	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}

#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
		| MIPS_CPU_COUNTER)

static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
{
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_R2000:
		c->cputype = CPU_R2000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R3000:
		if ((c->processor_id & 0xff) == PRID_REV_R3000A)
			if (cpu_has_confreg())
				c->cputype = CPU_R3081E;
			else
				c->cputype = CPU_R3000A;
		else
			c->cputype = CPU_R3000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R4000:
		if (read_c0_config() & CONF_SC) {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400PC;
			else
				c->cputype = CPU_R4000PC;
		} else {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400SC;
			else
				c->cputype = CPU_R4000SC;
		}

		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_VR41XX:
		switch (c->processor_id & 0xf0) {
		case PRID_REV_VR4111:
			c->cputype = CPU_VR4111;
			break;
		case PRID_REV_VR4121:
			c->cputype = CPU_VR4121;
			break;
		case PRID_REV_VR4122:
			if ((c->processor_id & 0xf) < 0x3)
				c->cputype = CPU_VR4122;
			else
				c->cputype = CPU_VR4181A;
			break;
		case PRID_REV_VR4130:
			if ((c->processor_id & 0xf) < 0x4)
				c->cputype = CPU_VR4131;
			else
				c->cputype = CPU_VR4133;
			break;
		default:
			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
			c->cputype = CPU_VR41XX;
			break;
		}
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4300:
		c->cputype = CPU_R4300;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4600:
		c->cputype = CPU_R4600;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	#if 0
 	case PRID_IMP_R4650:
		/*
		 * This processor doesn't have an MMU, so it's not
		 * "real easy" to run Linux on it. It is left purely
		 * for documentation.  Commented out because it shares
		 * it's c0_prid id number with the TX3900.
		 */
		c->cputype = CPU_R4650;
	 	c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
	        c->tlbsize = 48;
		break;
	#endif
	case PRID_IMP_TX39:
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;

		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
			c->cputype = CPU_TX3927;
			c->tlbsize = 64;
		} else {
			switch (c->processor_id & 0xff) {
			case PRID_REV_TX3912:
				c->cputype = CPU_TX3912;
				c->tlbsize = 32;
				break;
			case PRID_REV_TX3922:
				c->cputype = CPU_TX3922;
				c->tlbsize = 64;
				break;
			default:
				c->cputype = CPU_UNKNOWN;
				break;
			}
		}
		break;
	case PRID_IMP_R4700:
		c->cputype = CPU_R4700;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_TX49:
		c->cputype = CPU_TX49XX;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_LLSC;
		if (!(c->processor_id & 0x08))
			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5000:
		c->cputype = CPU_R5000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5432:
		c->cputype = CPU_R5432;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5500:
		c->cputype = CPU_R5500;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_NEVADA:
		c->cputype = CPU_NEVADA;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R6000:
		c->cputype = CPU_R6000;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R6000A:
		c->cputype = CPU_R6000A;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_RM7000:
		c->cputype = CPU_RM7000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Undocumented RM7000:  Bit 29 in the info register of
		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
		 * entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_RM9000:
		c->cputype = CPU_RM9000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Bit 29 in the info register of the RM9000
		 * indicates if the TLB has 48 or 64 entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_R8000:
		c->cputype = CPU_R8000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
		break;
	case PRID_IMP_R10000:
		c->cputype = CPU_R10000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R12000:
		c->cputype = CPU_R12000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R14000:
		c->cputype = CPU_R14000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	}
}

static char unknown_isa[] __initdata = KERN_ERR \
	"Unsupported ISA type, c0.config0: %d.";

static inline unsigned int decode_config0(struct cpuinfo_mips *c)
{
	unsigned int config0;
	int isa;

	config0 = read_c0_config();

	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
		c->options |= MIPS_CPU_TLB;
	isa = (config0 & MIPS_CONF_AT) >> 13;
	switch (isa) {
	case 0:
		switch ((config0 & MIPS_CONF_AR) >> 10) {
		case 0:
			c->isa_level = MIPS_CPU_ISA_M32R1;
			break;
		case 1:
			c->isa_level = MIPS_CPU_ISA_M32R2;
			break;
		default:
			goto unknown;
		}
		break;
	case 2:
		switch ((config0 & MIPS_CONF_AR) >> 10) {
		case 0:
			c->isa_level = MIPS_CPU_ISA_M64R1;
			break;
		case 1:
			c->isa_level = MIPS_CPU_ISA_M64R2;
			break;
		default:
			goto unknown;
		}
		break;
	default:
		goto unknown;
	}

	return config0 & MIPS_CONF_M;

unknown:
	panic(unknown_isa, config0);
}

static inline unsigned int decode_config1(struct cpuinfo_mips *c)
{
	unsigned int config1;

	config1 = read_c0_config1();

	if (config1 & MIPS_CONF1_MD)
		c->ases |= MIPS_ASE_MDMX;
	if (config1 & MIPS_CONF1_WR)
		c->options |= MIPS_CPU_WATCH;
	if (config1 & MIPS_CONF1_CA)
		c->ases |= MIPS_ASE_MIPS16;
	if (config1 & MIPS_CONF1_EP)
		c->options |= MIPS_CPU_EJTAG;
	if (config1 & MIPS_CONF1_FP) {
		c->options |= MIPS_CPU_FPU;
		c->options |= MIPS_CPU_32FPR;
	}
	if (cpu_has_tlb)
		c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;

	return config1 & MIPS_CONF_M;
}

static inline unsigned int decode_config2(struct cpuinfo_mips *c)
{
	unsigned int config2;

	config2 = read_c0_config2();

	if (config2 & MIPS_CONF2_SL)
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return config2 & MIPS_CONF_M;
}

static inline unsigned int decode_config3(struct cpuinfo_mips *c)
{
	unsigned int config3;

	config3 = read_c0_config3();

	if (config3 & MIPS_CONF3_SM)
		c->ases |= MIPS_ASE_SMARTMIPS;
	if (config3 & MIPS_CONF3_DSP)
		c->ases |= MIPS_ASE_DSP;
	if (config3 & MIPS_CONF3_VINT)
		c->options |= MIPS_CPU_VINT;
	if (config3 & MIPS_CONF3_VEIC)
		c->options |= MIPS_CPU_VEIC;
	if (config3 & MIPS_CONF3_MT)
	        c->ases |= MIPS_ASE_MIPSMT;

	return config3 & MIPS_CONF_M;
}

static void __init decode_configs(struct cpuinfo_mips *c)
{
	/* MIPS32 or MIPS64 compliant CPU.  */
	c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
	             MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;

	c->scache.flags = MIPS_CACHE_NOT_PRESENT;

	/* Read Config registers.  */
	if (!decode_config0(c))
		return;			/* actually worth a panic() */
	if (!decode_config1(c))
		return;
	if (!decode_config2(c))
		return;
	if (!decode_config3(c))
		return;
}

static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_4KC:
		c->cputype = CPU_4KC;
		break;
	case PRID_IMP_4KEC:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KECR2:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KSC:
	case PRID_IMP_4KSD:
		c->cputype = CPU_4KSC;
		break;
	case PRID_IMP_5KC:
		c->cputype = CPU_5KC;
		break;
	case PRID_IMP_20KC:
		c->cputype = CPU_20KC;
		break;
	case PRID_IMP_24K:
	case PRID_IMP_24KE:
		c->cputype = CPU_24K;
		break;
	case PRID_IMP_25KF:
		c->cputype = CPU_25KF;
		break;
	case PRID_IMP_34K:
		c->cputype = CPU_34K;
		break;
	case PRID_IMP_74K:
		c->cputype = CPU_74K;
		break;
	}
}

static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_AU1_REV1:
	case PRID_IMP_AU1_REV2:
		switch ((c->processor_id >> 24) & 0xff) {
		case 0:
			c->cputype = CPU_AU1000;
			break;
		case 1:
			c->cputype = CPU_AU1500;
			break;
		case 2:
			c->cputype = CPU_AU1100;
			break;
		case 3:
			c->cputype = CPU_AU1550;
			break;
		case 4:
			c->cputype = CPU_AU1200;
			break;
		default:
			panic("Unknown Au Core!");
			break;
		}
		break;
	}
}

static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
	decode_configs(c);

	/*
	 * For historical reasons the SB1 comes with it's own variant of
	 * cache code which eventually will be folded into c-r4k.c.  Until
	 * then we pretend it's got it's own cache architecture.
	 */
	c->options &= ~MIPS_CPU_4K_CACHE;
	c->options |= MIPS_CPU_SB1_CACHE;

	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SB1:
		c->cputype = CPU_SB1;
		/* FPU in pass1 is known to have issues. */
		if ((c->processor_id & 0xff) < 0x02)
			c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
		break;
	case PRID_IMP_SB1A:
		c->cputype = CPU_SB1A;
		break;
	}
}

static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SR71000:
		c->cputype = CPU_SR71000;
		c->scache.ways = 8;
		c->tlbsize = 64;
		break;
	}
}

static inline void cpu_probe_philips(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_PR4450:
		c->cputype = CPU_PR4450;
		c->isa_level = MIPS_CPU_ISA_M32R1;
		break;
	default:
		panic("Unknown Philips Core!"); /* REVISIT: die? */
		break;
	}
}


__init void cpu_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	c->processor_id	= PRID_IMP_UNKNOWN;
	c->fpu_id	= FPIR_IMP_NONE;
	c->cputype	= CPU_UNKNOWN;

	c->processor_id = read_c0_prid();
	switch (c->processor_id & 0xff0000) {
	case PRID_COMP_LEGACY:
		cpu_probe_legacy(c);
		break;
	case PRID_COMP_MIPS:
		cpu_probe_mips(c);
		break;
	case PRID_COMP_ALCHEMY:
		cpu_probe_alchemy(c);
		break;
	case PRID_COMP_SIBYTE:
		cpu_probe_sibyte(c);
		break;
	case PRID_COMP_SANDCRAFT:
		cpu_probe_sandcraft(c);
		break;
 	case PRID_COMP_PHILIPS:
		cpu_probe_philips(c);
		break;
	default:
		c->cputype = CPU_UNKNOWN;
	}
	if (c->options & MIPS_CPU_FPU) {
		c->fpu_id = cpu_get_fpu_id();

		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
		    c->isa_level == MIPS_CPU_ISA_M64R2) {
			if (c->fpu_id & MIPS_FPIR_3D)
				c->ases |= MIPS_ASE_MIPS3D;
		}
	}
}

__init void cpu_report(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("CPU revision is: %08x\n", c->processor_id);
	if (c->options & MIPS_CPU_FPU)
		printk("FPU revision is: %08x\n", c->fpu_id);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Processor capabilities determination functions.
	3	*
	4	* Copyright (C) xxxx the Anonymous
010b853b	5	* Copyright (C) 1994 - 2006 Ralf Baechle
4194318c	6	* Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c	7	* Copyright (C) 2001, 2004 MIPS Inc.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
1da177e4 LT	14	#include <linux/init.h>
	15	#include <linux/kernel.h>
	16	#include <linux/ptrace.h>
	17	#include <linux/stddef.h>
	18
5759906c	19	#include <asm/bugs.h>
1da177e4 LT	20	#include <asm/cpu.h>
	21	#include <asm/fpu.h>
	22	#include <asm/mipsregs.h>
	23	#include <asm/system.h>
	24
	25	/*
	26	* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
	27	* the implementation of the "wait" feature differs between CPU families. This
	28	* points to the function that implements CPU specific wait.
	29	* The wait instruction stops the pipeline and reduces the power consumption of
	30	* the CPU very much.
	31	*/
	32	void (*cpu_wait)(void) = NULL;
	33
	34	static void r3081_wait(void)
	35	{
	36	unsigned long cfg = read_c0_conf();
	37	write_c0_conf(cfg \| R30XX_CONF_HALT);
	38	}
	39
	40	static void r39xx_wait(void)
	41	{
60a6c377 AN	42	local_irq_disable();
	43	if (!need_resched())
	44	write_c0_conf(read_c0_conf() \| TX39_CONF_HALT);
	45	local_irq_enable();
1da177e4 LT	46	}
1da177e4 LT	47
60a6c377 AN	48	/*
	49	* There is a race when WAIT instruction executed with interrupt
	50	* enabled.
	51	* But it is implementation-dependent wheter the pipelie restarts when
	52	* a non-enabled interrupt is requested.
	53	*/
1da177e4 LT	54	static void r4k_wait(void)
1da177e4 LT	55	{
60a6c377 AN	56	__asm__(" .set mips3 \n"
	57	" wait \n"
	58	" .set mips0 \n");
	59	}
	60
	61	/*
	62	* This variant is preferable as it allows testing need_resched and going to
	63	* sleep depending on the outcome atomically. Unfortunately the "It is
	64	* implementation-dependent whether the pipeline restarts when a non-enabled
	65	* interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
	66	* using this version a gamble.
	67	*/
	68	static void r4k_wait_irqoff(void)
	69	{
	70	local_irq_disable();
	71	if (!need_resched())
	72	__asm__(" .set mips3 \n"
	73	" wait \n"
	74	" .set mips0 \n");
	75	local_irq_enable();
1da177e4 LT	76	}
1da177e4 LT	77
494900af PP	78	/* The Au1xxx wait is available only if using 32khz counter or
494900af PP	79	* external timer source, but specifically not CP0 Counter. */
fe359bf5	80	int allow_au1k_wait;
10f650db	81
494900af	82	static void au1k_wait(void)
1da177e4	83	{
1da177e4	84	/* using the wait instruction makes CP0 counter unusable */
60a6c377 AN	85	__asm__(" .set mips3 \n"
	86	" cache 0x14, 0(%0) \n"
	87	" cache 0x14, 32(%0) \n"
	88	" sync \n"
	89	" nop \n"
	90	" wait \n"
	91	" nop \n"
	92	" nop \n"
	93	" nop \n"
	94	" nop \n"
	95	" .set mips0 \n"
10f650db	96	: : "r" (au1k_wait));
1da177e4 LT	97	}
1da177e4 LT	98
55d04dff RB	99	static int __initdata nowait = 0;
	100
	101	int __init wait_disable(char *s)
	102	{
	103	nowait = 1;
	104
	105	return 1;
	106	}
	107
	108	__setup("nowait", wait_disable);
	109
1da177e4 LT	110	static inline void check_wait(void)
	111	{
	112	struct cpuinfo_mips *c = &current_cpu_data;
	113
55d04dff	114	if (nowait) {
c2379230	115	printk("Wait instruction disabled.\n");
55d04dff RB	116	return;
	117	}
	118
1da177e4 LT	119	switch (c->cputype) {
	120	case CPU_R3081:
	121	case CPU_R3081E:
	122	cpu_wait = r3081_wait;
1da177e4 LT	123	break;
	124	case CPU_TX3927:
	125	cpu_wait = r39xx_wait;
1da177e4 LT	126	break;
	127	case CPU_R4200:
	128	/* case CPU_R4300: */
	129	case CPU_R4600:
	130	case CPU_R4640:
	131	case CPU_R4650:
	132	case CPU_R4700:
	133	case CPU_R5000:
	134	case CPU_NEVADA:
	135	case CPU_RM7000:
1da177e4 LT	136	case CPU_4KC:
	137	case CPU_4KEC:
	138	case CPU_4KSC:
	139	case CPU_5KC:
	140	/* case CPU_20KC:*/
	141	case CPU_24K:
	142	case CPU_25KF:
bbc7f22f	143	case CPU_34K:
c620953c	144	case CPU_74K:
bdf21b18	145	case CPU_PR4450:
1da177e4	146	cpu_wait = r4k_wait;
1da177e4	147	break;
60a6c377 AN	148	case CPU_TX49XX:
60a6c377 AN	149	cpu_wait = r4k_wait_irqoff;
60a6c377	150	break;
1da177e4 LT	151	case CPU_AU1000:
	152	case CPU_AU1100:
	153	case CPU_AU1500:
e3ad1c23 PP	154	case CPU_AU1550:
e3ad1c23 PP	155	case CPU_AU1200:
c2379230	156	if (allow_au1k_wait)
fe359bf5	157	cpu_wait = au1k_wait;
1da177e4	158	break;
441ee341	159	case CPU_RM9000:
c2379230	160	if ((c->processor_id & 0x00ff) >= 0x40)
441ee341	161	cpu_wait = r4k_wait;
441ee341	162	break;
1da177e4	163	default:
1da177e4 LT	164	break;
	165	}
	166	}
	167
	168	void __init check_bugs32(void)
	169	{
	170	check_wait();
	171	}
	172
	173	/*
	174	* Probe whether cpu has config register by trying to play with
	175	* alternate cache bit and see whether it matters.
	176	* It's used by cpu_probe to distinguish between R3000A and R3081.
	177	*/
	178	static inline int cpu_has_confreg(void)
	179	{
	180	#ifdef CONFIG_CPU_R3000
	181	extern unsigned long r3k_cache_size(unsigned long);
	182	unsigned long size1, size2;
	183	unsigned long cfg = read_c0_conf();
	184
	185	size1 = r3k_cache_size(ST0_ISC);
	186	write_c0_conf(cfg ^ R30XX_CONF_AC);
	187	size2 = r3k_cache_size(ST0_ISC);
	188	write_c0_conf(cfg);
	189	return size1 != size2;
	190	#else
	191	return 0;
	192	#endif
	193	}
	194
	195	/*
	196	* Get the FPU Implementation/Revision.
	197	*/
	198	static inline unsigned long cpu_get_fpu_id(void)
	199	{
	200	unsigned long tmp, fpu_id;
	201
	202	tmp = read_c0_status();
	203	__enable_fpu();
	204	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	205	write_c0_status(tmp);
	206	return fpu_id;
	207	}
	208
	209	/*
	210	* Check the CPU has an FPU the official way.
	211	*/
	212	static inline int __cpu_has_fpu(void)
	213	{
	214	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
	215	}
	216
02cf2119	217	#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \
1da177e4 LT	218	\| MIPS_CPU_COUNTER)
	219
	220	static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
	221	{
	222	switch (c->processor_id & 0xff00) {
	223	case PRID_IMP_R2000:
	224	c->cputype = CPU_R2000;
	225	c->isa_level = MIPS_CPU_ISA_I;
02cf2119 RB	226	c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
02cf2119 RB	227	MIPS_CPU_NOFPUEX;
1da177e4 LT	228	if (__cpu_has_fpu())
	229	c->options \|= MIPS_CPU_FPU;
	230	c->tlbsize = 64;
	231	break;
	232	case PRID_IMP_R3000:
	233	if ((c->processor_id & 0xff) == PRID_REV_R3000A)
	234	if (cpu_has_confreg())
	235	c->cputype = CPU_R3081E;
	236	else
	237	c->cputype = CPU_R3000A;
	238	else
	239	c->cputype = CPU_R3000;
	240	c->isa_level = MIPS_CPU_ISA_I;
02cf2119 RB	241	c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
02cf2119 RB	242	MIPS_CPU_NOFPUEX;
1da177e4 LT	243	if (__cpu_has_fpu())
	244	c->options \|= MIPS_CPU_FPU;
	245	c->tlbsize = 64;
	246	break;
	247	case PRID_IMP_R4000:
	248	if (read_c0_config() & CONF_SC) {
	249	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
	250	c->cputype = CPU_R4400PC;
	251	else
	252	c->cputype = CPU_R4000PC;
	253	} else {
	254	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
	255	c->cputype = CPU_R4400SC;
	256	else
	257	c->cputype = CPU_R4000SC;
	258	}
	259
	260	c->isa_level = MIPS_CPU_ISA_III;
	261	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	262	MIPS_CPU_WATCH \| MIPS_CPU_VCE \|
	263	MIPS_CPU_LLSC;
	264	c->tlbsize = 48;
	265	break;
	266	case PRID_IMP_VR41XX:
	267	switch (c->processor_id & 0xf0) {
1da177e4 LT	268	case PRID_REV_VR4111:
	269	c->cputype = CPU_VR4111;
	270	break;
1da177e4 LT	271	case PRID_REV_VR4121:
	272	c->cputype = CPU_VR4121;
	273	break;
	274	case PRID_REV_VR4122:
	275	if ((c->processor_id & 0xf) < 0x3)
	276	c->cputype = CPU_VR4122;
	277	else
	278	c->cputype = CPU_VR4181A;
	279	break;
	280	case PRID_REV_VR4130:
	281	if ((c->processor_id & 0xf) < 0x4)
	282	c->cputype = CPU_VR4131;
	283	else
	284	c->cputype = CPU_VR4133;
	285	break;
	286	default:
	287	printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
	288	c->cputype = CPU_VR41XX;
	289	break;
	290	}
	291	c->isa_level = MIPS_CPU_ISA_III;
	292	c->options = R4K_OPTS;
	293	c->tlbsize = 32;
	294	break;
	295	case PRID_IMP_R4300:
	296	c->cputype = CPU_R4300;
	297	c->isa_level = MIPS_CPU_ISA_III;
	298	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	299	MIPS_CPU_LLSC;
	300	c->tlbsize = 32;
	301	break;
	302	case PRID_IMP_R4600:
	303	c->cputype = CPU_R4600;
	304	c->isa_level = MIPS_CPU_ISA_III;
075e7502 TS	305	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
075e7502 TS	306	MIPS_CPU_LLSC;
1da177e4 LT	307	c->tlbsize = 48;
	308	break;
	309	#if 0
	310	case PRID_IMP_R4650:
	311	/*
	312	* This processor doesn't have an MMU, so it's not
	313	* "real easy" to run Linux on it. It is left purely
	314	* for documentation. Commented out because it shares
	315	* it's c0_prid id number with the TX3900.
	316	*/
a3dddd56	317	c->cputype = CPU_R4650;
1da177e4 LT	318	c->isa_level = MIPS_CPU_ISA_III;
	319	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	320	c->tlbsize = 48;
	321	break;
	322	#endif
	323	case PRID_IMP_TX39:
	324	c->isa_level = MIPS_CPU_ISA_I;
02cf2119	325	c->options = MIPS_CPU_TLB \| MIPS_CPU_TX39_CACHE;
1da177e4 LT	326
	327	if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
	328	c->cputype = CPU_TX3927;
	329	c->tlbsize = 64;
	330	} else {
	331	switch (c->processor_id & 0xff) {
	332	case PRID_REV_TX3912:
	333	c->cputype = CPU_TX3912;
	334	c->tlbsize = 32;
	335	break;
	336	case PRID_REV_TX3922:
	337	c->cputype = CPU_TX3922;
	338	c->tlbsize = 64;
	339	break;
	340	default:
	341	c->cputype = CPU_UNKNOWN;
	342	break;
	343	}
	344	}
	345	break;
	346	case PRID_IMP_R4700:
	347	c->cputype = CPU_R4700;
	348	c->isa_level = MIPS_CPU_ISA_III;
	349	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	350	MIPS_CPU_LLSC;
	351	c->tlbsize = 48;
	352	break;
	353	case PRID_IMP_TX49:
	354	c->cputype = CPU_TX49XX;
	355	c->isa_level = MIPS_CPU_ISA_III;
	356	c->options = R4K_OPTS \| MIPS_CPU_LLSC;
	357	if (!(c->processor_id & 0x08))
	358	c->options \|= MIPS_CPU_FPU \| MIPS_CPU_32FPR;
	359	c->tlbsize = 48;
	360	break;
	361	case PRID_IMP_R5000:
	362	c->cputype = CPU_R5000;
	363	c->isa_level = MIPS_CPU_ISA_IV;
	364	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	365	MIPS_CPU_LLSC;
	366	c->tlbsize = 48;
	367	break;
	368	case PRID_IMP_R5432:
	369	c->cputype = CPU_R5432;
	370	c->isa_level = MIPS_CPU_ISA_IV;
	371	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	372	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
	373	c->tlbsize = 48;
	374	break;
	375	case PRID_IMP_R5500:
	376	c->cputype = CPU_R5500;
	377	c->isa_level = MIPS_CPU_ISA_IV;
	378	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	379	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
	380	c->tlbsize = 48;
	381	break;
	382	case PRID_IMP_NEVADA:
	383	c->cputype = CPU_NEVADA;
	384	c->isa_level = MIPS_CPU_ISA_IV;
	385	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	386	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC;
	387	c->tlbsize = 48;
	388	break;
	389	case PRID_IMP_R6000:
390	c->cputype = CPU_R6000;
391	c->isa_level = MIPS_CPU_ISA_II;
392	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
393	MIPS_CPU_LLSC;
394	c->tlbsize = 32;
395	break;
396	case PRID_IMP_R6000A:
397	c->cputype = CPU_R6000A;
398	c->isa_level = MIPS_CPU_ISA_II;
399	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
400	MIPS_CPU_LLSC;
401	c->tlbsize = 32;
402	break;
403	case PRID_IMP_RM7000:
404	c->cputype = CPU_RM7000;
405	c->isa_level = MIPS_CPU_ISA_IV;
406	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
407	MIPS_CPU_LLSC;
408	/*
409	* Undocumented RM7000: Bit 29 in the info register of
410	* the RM7000 v2.0 indicates if the TLB has 48 or 64
411	* entries.
412	*
413	* 29 1 => 64 entry JTLB
414	* 0 => 48 entry JTLB
415	*/
416	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
417	break;
418	case PRID_IMP_RM9000:
419	c->cputype = CPU_RM9000;
420	c->isa_level = MIPS_CPU_ISA_IV;
421	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
422	MIPS_CPU_LLSC;
423	/*
424	* Bit 29 in the info register of the RM9000
425	* indicates if the TLB has 48 or 64 entries.
426	*
427	* 29 1 => 64 entry JTLB
428	* 0 => 48 entry JTLB
429	*/
430	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
431	break;
432	case PRID_IMP_R8000:
433	c->cputype = CPU_R8000;
434	c->isa_level = MIPS_CPU_ISA_IV;
435	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
436	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
437	MIPS_CPU_LLSC;
438	c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
439	break;
440	case PRID_IMP_R10000:
441	c->cputype = CPU_R10000;
442	c->isa_level = MIPS_CPU_ISA_IV;
8b36612a	443	c->options = MIPS_CPU_TLB \| MIPS_CPU_4K_CACHE \| MIPS_CPU_4KEX \|
1da177e4 LT	444	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	445	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
	446	MIPS_CPU_LLSC;
	447	c->tlbsize = 64;
	448	break;
	449	case PRID_IMP_R12000:
	450	c->cputype = CPU_R12000;
	451	c->isa_level = MIPS_CPU_ISA_IV;
8b36612a	452	c->options = MIPS_CPU_TLB \| MIPS_CPU_4K_CACHE \| MIPS_CPU_4KEX \|
1da177e4 LT	453	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	454	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
	455	MIPS_CPU_LLSC;
	456	c->tlbsize = 64;
	457	break;
44d921b2 K	458	case PRID_IMP_R14000:
	459	c->cputype = CPU_R14000;
	460	c->isa_level = MIPS_CPU_ISA_IV;
	461	c->options = MIPS_CPU_TLB \| MIPS_CPU_4K_CACHE \| MIPS_CPU_4KEX \|
	462	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	463	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
	464	MIPS_CPU_LLSC;
	465	c->tlbsize = 64;
	466	break;
1da177e4 LT	467	}
	468	}
	469
b4672d37 RB	470	static char unknown_isa[] __initdata = KERN_ERR \
	471	"Unsupported ISA type, c0.config0: %d.";
	472
4194318c	473	static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4	474	{
4194318c RB	475	unsigned int config0;
4194318c RB	476	int isa;
1da177e4	477
4194318c RB	478	config0 = read_c0_config();
	479
	480	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119	481	c->options \|= MIPS_CPU_TLB;
4194318c RB	482	isa = (config0 & MIPS_CONF_AT) >> 13;
	483	switch (isa) {
	484	case 0:
3a01c49a	485	switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37 RB	486	case 0:
	487	c->isa_level = MIPS_CPU_ISA_M32R1;
	488	break;
	489	case 1:
	490	c->isa_level = MIPS_CPU_ISA_M32R2;
	491	break;
	492	default:
	493	goto unknown;
	494	}
4194318c RB	495	break;
4194318c RB	496	case 2:
3a01c49a	497	switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37 RB	498	case 0:
	499	c->isa_level = MIPS_CPU_ISA_M64R1;
	500	break;
	501	case 1:
	502	c->isa_level = MIPS_CPU_ISA_M64R2;
	503	break;
	504	default:
	505	goto unknown;
	506	}
4194318c RB	507	break;
4194318c RB	508	default:
b4672d37	509	goto unknown;
4194318c RB	510	}
	511
	512	return config0 & MIPS_CONF_M;
b4672d37 RB	513
	514	unknown:
	515	panic(unknown_isa, config0);
4194318c RB	516	}
	517
	518	static inline unsigned int decode_config1(struct cpuinfo_mips *c)
	519	{
	520	unsigned int config1;
1da177e4	521
1da177e4	522	config1 = read_c0_config1();
4194318c RB	523
	524	if (config1 & MIPS_CONF1_MD)
	525	c->ases \|= MIPS_ASE_MDMX;
	526	if (config1 & MIPS_CONF1_WR)
1da177e4	527	c->options \|= MIPS_CPU_WATCH;
4194318c RB	528	if (config1 & MIPS_CONF1_CA)
	529	c->ases \|= MIPS_ASE_MIPS16;
	530	if (config1 & MIPS_CONF1_EP)
1da177e4	531	c->options \|= MIPS_CPU_EJTAG;
4194318c	532	if (config1 & MIPS_CONF1_FP) {
1da177e4 LT	533	c->options \|= MIPS_CPU_FPU;
	534	c->options \|= MIPS_CPU_32FPR;
	535	}
4194318c RB	536	if (cpu_has_tlb)
	537	c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
	538
	539	return config1 & MIPS_CONF_M;
	540	}
	541
	542	static inline unsigned int decode_config2(struct cpuinfo_mips *c)
	543	{
	544	unsigned int config2;
	545
	546	config2 = read_c0_config2();
	547
	548	if (config2 & MIPS_CONF2_SL)
	549	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	550
	551	return config2 & MIPS_CONF_M;
	552	}
	553
	554	static inline unsigned int decode_config3(struct cpuinfo_mips *c)
	555	{
	556	unsigned int config3;
	557
	558	config3 = read_c0_config3();
	559
	560	if (config3 & MIPS_CONF3_SM)
	561	c->ases \|= MIPS_ASE_SMARTMIPS;
e50c0a8f RB	562	if (config3 & MIPS_CONF3_DSP)
e50c0a8f RB	563	c->ases \|= MIPS_ASE_DSP;
8f40611d RB	564	if (config3 & MIPS_CONF3_VINT)
	565	c->options \|= MIPS_CPU_VINT;
	566	if (config3 & MIPS_CONF3_VEIC)
	567	c->options \|= MIPS_CPU_VEIC;
	568	if (config3 & MIPS_CONF3_MT)
e0daad44	569	c->ases \|= MIPS_ASE_MIPSMT;
4194318c RB	570
	571	return config3 & MIPS_CONF_M;
	572	}
	573
c36cd4ba	574	static void __init decode_configs(struct cpuinfo_mips *c)
4194318c RB	575	{
4194318c RB	576	/* MIPS32 or MIPS64 compliant CPU. */
02cf2119 RB	577	c->options = MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \| MIPS_CPU_COUNTER \|
02cf2119 RB	578	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
4194318c	579
1da177e4 LT	580	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1da177e4 LT	581
4194318c RB	582	/* Read Config registers. */
	583	if (!decode_config0(c))
	584	return; /* actually worth a panic() */
	585	if (!decode_config1(c))
	586	return;
	587	if (!decode_config2(c))
	588	return;
	589	if (!decode_config3(c))
	590	return;
1da177e4 LT	591	}
	592
	593	static inline void cpu_probe_mips(struct cpuinfo_mips *c)
	594	{
4194318c	595	decode_configs(c);
1da177e4 LT	596	switch (c->processor_id & 0xff00) {
	597	case PRID_IMP_4KC:
	598	c->cputype = CPU_4KC;
1da177e4 LT	599	break;
	600	case PRID_IMP_4KEC:
	601	c->cputype = CPU_4KEC;
1da177e4	602	break;
2b07bd02 RB	603	case PRID_IMP_4KECR2:
2b07bd02 RB	604	c->cputype = CPU_4KEC;
2b07bd02	605	break;
1da177e4	606	case PRID_IMP_4KSC:
8afcb5d8	607	case PRID_IMP_4KSD:
1da177e4	608	c->cputype = CPU_4KSC;
1da177e4 LT	609	break;
	610	case PRID_IMP_5KC:
	611	c->cputype = CPU_5KC;
1da177e4 LT	612	break;
	613	case PRID_IMP_20KC:
	614	c->cputype = CPU_20KC;
1da177e4 LT	615	break;
1da177e4 LT	616	case PRID_IMP_24K:
e50c0a8f	617	case PRID_IMP_24KE:
1da177e4	618	c->cputype = CPU_24K;
1da177e4 LT	619	break;
	620	case PRID_IMP_25KF:
	621	c->cputype = CPU_25KF;
1da177e4	622	break;
bbc7f22f RB	623	case PRID_IMP_34K:
bbc7f22f RB	624	c->cputype = CPU_34K;
bbc7f22f	625	break;
c620953c CD	626	case PRID_IMP_74K:
	627	c->cputype = CPU_74K;
	628	break;
1da177e4 LT	629	}
	630	}
	631
	632	static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
	633	{
4194318c	634	decode_configs(c);
1da177e4 LT	635	switch (c->processor_id & 0xff00) {
	636	case PRID_IMP_AU1_REV1:
	637	case PRID_IMP_AU1_REV2:
	638	switch ((c->processor_id >> 24) & 0xff) {
	639	case 0:
a3dddd56	640	c->cputype = CPU_AU1000;
1da177e4 LT	641	break;
	642	case 1:
	643	c->cputype = CPU_AU1500;
	644	break;
	645	case 2:
	646	c->cputype = CPU_AU1100;
	647	break;
	648	case 3:
	649	c->cputype = CPU_AU1550;
	650	break;
e3ad1c23 PP	651	case 4:
	652	c->cputype = CPU_AU1200;
	653	break;
1da177e4 LT	654	default:
	655	panic("Unknown Au Core!");
	656	break;
	657	}
1da177e4 LT	658	break;
	659	}
	660	}
	661
	662	static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
	663	{
4194318c	664	decode_configs(c);
02cf2119 RB	665
	666	/*
	667	* For historical reasons the SB1 comes with it's own variant of
	668	* cache code which eventually will be folded into c-r4k.c. Until
	669	* then we pretend it's got it's own cache architecture.
	670	*/
d121ced2	671	c->options &= ~MIPS_CPU_4K_CACHE;
02cf2119 RB	672	c->options \|= MIPS_CPU_SB1_CACHE;
02cf2119 RB	673
1da177e4 LT	674	switch (c->processor_id & 0xff00) {
	675	case PRID_IMP_SB1:
	676	c->cputype = CPU_SB1;
1da177e4	677	/* FPU in pass1 is known to have issues. */
aa32374a	678	if ((c->processor_id & 0xff) < 0x02)
010b853b	679	c->options &= ~(MIPS_CPU_FPU \| MIPS_CPU_32FPR);
1da177e4	680	break;
93ce2f52 AI	681	case PRID_IMP_SB1A:
	682	c->cputype = CPU_SB1A;
	683	break;
1da177e4 LT	684	}
	685	}
	686
	687	static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
	688	{
4194318c	689	decode_configs(c);
1da177e4 LT	690	switch (c->processor_id & 0xff00) {
	691	case PRID_IMP_SR71000:
	692	c->cputype = CPU_SR71000;
1da177e4 LT	693	c->scache.ways = 8;
	694	c->tlbsize = 64;
	695	break;
	696	}
	697	}
	698
bdf21b18 PP	699	static inline void cpu_probe_philips(struct cpuinfo_mips *c)
	700	{
	701	decode_configs(c);
	702	switch (c->processor_id & 0xff00) {
	703	case PRID_IMP_PR4450:
	704	c->cputype = CPU_PR4450;
e7958bb9	705	c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 PP	706	break;
	707	default:
	708	panic("Unknown Philips Core!"); /* REVISIT: die? */
	709	break;
	710	}
	711	}
	712
	713
1da177e4 LT	714	__init void cpu_probe(void)
	715	{
	716	struct cpuinfo_mips *c = &current_cpu_data;
	717
	718	c->processor_id = PRID_IMP_UNKNOWN;
	719	c->fpu_id = FPIR_IMP_NONE;
	720	c->cputype = CPU_UNKNOWN;
	721
	722	c->processor_id = read_c0_prid();
	723	switch (c->processor_id & 0xff0000) {
	724	case PRID_COMP_LEGACY:
	725	cpu_probe_legacy(c);
	726	break;
	727	case PRID_COMP_MIPS:
	728	cpu_probe_mips(c);
	729	break;
	730	case PRID_COMP_ALCHEMY:
	731	cpu_probe_alchemy(c);
	732	break;
	733	case PRID_COMP_SIBYTE:
	734	cpu_probe_sibyte(c);
	735	break;
1da177e4 LT	736	case PRID_COMP_SANDCRAFT:
	737	cpu_probe_sandcraft(c);
	738	break;
bdf21b18 PP	739	case PRID_COMP_PHILIPS:
bdf21b18 PP	740	cpu_probe_philips(c);
a3dddd56	741	break;
1da177e4 LT	742	default:
	743	c->cputype = CPU_UNKNOWN;
	744	}
4194318c	745	if (c->options & MIPS_CPU_FPU) {
1da177e4	746	c->fpu_id = cpu_get_fpu_id();
4194318c	747
e7958bb9	748	if (c->isa_level == MIPS_CPU_ISA_M32R1 \|\|
b4672d37 RB	749	c->isa_level == MIPS_CPU_ISA_M32R2 \|\|
	750	c->isa_level == MIPS_CPU_ISA_M64R1 \|\|
	751	c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c RB	752	if (c->fpu_id & MIPS_FPIR_3D)
	753	c->ases \|= MIPS_ASE_MIPS3D;
	754	}
	755	}
1da177e4 LT	756	}
	757
	758	__init void cpu_report(void)
	759	{
	760	struct cpuinfo_mips *c = &current_cpu_data;
	761
	762	printk("CPU revision is: %08x\n", c->processor_id);
	763	if (c->options & MIPS_CPU_FPU)
	764	printk("FPU revision is: %08x\n", c->fpu_id);
	765	}