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MIPS: Fix build error cavium-octeon without CONFIG_SMP
[deliverable/linux.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
654f57bf 25#include <asm/watch.h>
06372a63 26#include <asm/elf.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
1da177e4
LT		 30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
982f6ffe 37void (*cpu_wait)(void);
f8ede0f7 38EXPORT_SYMBOL(cpu_wait);
1da177e4
LT		 39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
60a6c377
AN		 48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
1da177e4
LT		 52}
53
c65a5480 54extern void r4k_wait(void);
60a6c377
AN		 55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
8531a35e 63void r4k_wait_irqoff(void)
60a6c377
AN		 64{
65 local_irq_disable();
66 if (!need_resched())
8531a35e
KK		 67 __asm__(" .set push \n"
68 " .set mips3 \n"
60a6c377 69 " wait \n"
8531a35e 70 " .set pop \n");
60a6c377 71 local_irq_enable();
70342287 72 __asm__(" .globl __pastwait \n"
8531a35e 73 "__pastwait: \n");
1da177e4
LT		 74}
75
5a812999 76/*
70342287 77 * The RM7000 variant has to handle erratum 38. The workaround is to not
5a812999
RB		 78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
2882b0c6
ML		 97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
494900af 102static void au1k_wait(void)
1da177e4 103{
60a6c377
AN		 104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
10f650db 115 : : "r" (au1k_wait));
1da177e4
LT		 116}
117
982f6ffe 118static int __initdata nowait;
55d04dff 119
f49a747c 120static int __init wait_disable(char *s)
55d04dff
RB		 121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
0103d23f
KC		 129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
ee80f7c7 145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
c65a5480 153void __init check_wait(void)
1da177e4
LT		 154{
155 struct cpuinfo_mips *c = &current_cpu_data;
156
55d04dff 157 if (nowait) {
c2379230 158 printk("Wait instruction disabled.\n");
55d04dff
RB		 159 return;
160 }
161
1da177e4
LT		 162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
1da177e4
LT		 166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
1da177e4
LT		 169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
a644b277 177 case CPU_R5500:
1da177e4 178 case CPU_NEVADA:
1da177e4
LT		 179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
1da177e4 183 case CPU_25KF:
4b3e975e 184 case CPU_PR4450:
602977b0
KC		 185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
0dd4781b 189 case CPU_CAVIUM_OCTEON:
6f329468 190 case CPU_CAVIUM_OCTEON_PLUS:
0e56b385 191 case CPU_CAVIUM_OCTEON2:
83ccf69d 192 case CPU_JZRISC:
2fa36399 193 case CPU_LOONGSON1:
11d48aac 194 case CPU_XLR:
a3d4fb2d 195 case CPU_XLP:
4b3e975e
RB		 196 cpu_wait = r4k_wait;
197 break;
198
5a812999
RB		 199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
113c62d9 203 case CPU_M14KC:
f8fa4811 204 case CPU_M14KEC:
4b3e975e 205 case CPU_24K:
bbc7f22f 206 case CPU_34K:
39b8d525 207 case CPU_1004K:
4b3e975e
RB		 208 cpu_wait = r4k_wait;
209 if (read_c0_config7() & MIPS_CONF7_WII)
210 cpu_wait = r4k_wait_irqoff;
211 break;
212
c620953c 213 case CPU_74K:
1da177e4 214 cpu_wait = r4k_wait;
4b3e975e
RB		 215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
216 cpu_wait = r4k_wait_irqoff;
1da177e4 217 break;
4b3e975e 218
60a6c377
AN		 219 case CPU_TX49XX:
220 cpu_wait = r4k_wait_irqoff;
60a6c377 221 break;
270717a8 222 case CPU_ALCHEMY:
0c694de1 223 cpu_wait = au1k_wait;
1da177e4 224 break;
c8eae71d
RB		 225 case CPU_20KC:
226 /*
227 * WAIT on Rev1.0 has E1, E2, E3 and E16.
228 * WAIT on Rev2.0 and Rev3.0 has E16.
229 * Rev3.1 WAIT is nop, why bother
230 */
231 if ((c->processor_id & 0xff) <= 0x64)
232 break;
233
50da469a
RB		 234 /*
235 * Another rev is incremeting c0_count at a reduced clock
236 * rate while in WAIT mode. So we basically have the choice
237 * between using the cp0 timer as clocksource or avoiding
238 * the WAIT instruction. Until more details are known,
239 * disable the use of WAIT for 20Kc entirely.
240 cpu_wait = r4k_wait;
241 */
c8eae71d 242 break;
441ee341 243 case CPU_RM9000:
c2379230 244 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 245 cpu_wait = r4k_wait;
441ee341 246 break;
1da177e4 247 default:
1da177e4
LT		 248 break;
249 }
250}
251
9267a30d
MSJ		 252static inline void check_errata(void)
253{
254 struct cpuinfo_mips *c = &current_cpu_data;
255
256 switch (c->cputype) {
257 case CPU_34K:
258 /*
259 * Erratum "RPS May Cause Incorrect Instruction Execution"
260 * This code only handles VPE0, any SMP/SMTC/RTOS code
261 * making use of VPE1 will be responsable for that VPE.
262 */
263 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
265 break;
266 default:
267 break;
268 }
269}
270
1da177e4
LT		 271void __init check_bugs32(void)
272{
9267a30d 273 check_errata();
1da177e4
LT		 274}
275
276/*
277 * Probe whether cpu has config register by trying to play with
278 * alternate cache bit and see whether it matters.
279 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 */
281static inline int cpu_has_confreg(void)
282{
283#ifdef CONFIG_CPU_R3000
284 extern unsigned long r3k_cache_size(unsigned long);
285 unsigned long size1, size2;
286 unsigned long cfg = read_c0_conf();
287
288 size1 = r3k_cache_size(ST0_ISC);
289 write_c0_conf(cfg ^ R30XX_CONF_AC);
290 size2 = r3k_cache_size(ST0_ISC);
291 write_c0_conf(cfg);
292 return size1 != size2;
293#else
294 return 0;
295#endif
296}
297
c094c99e
RM		 298static inline void set_elf_platform(int cpu, const char *plat)
299{
300 if (cpu == 0)
301 __elf_platform = plat;
302}
303
1da177e4
LT		 304/*
305 * Get the FPU Implementation/Revision.
306 */
307static inline unsigned long cpu_get_fpu_id(void)
308{
309 unsigned long tmp, fpu_id;
310
311 tmp = read_c0_status();
312 __enable_fpu();
313 fpu_id = read_32bit_cp1_register(CP1_REVISION);
314 write_c0_status(tmp);
315 return fpu_id;
316}
317
318/*
319 * Check the CPU has an FPU the official way.
320 */
321static inline int __cpu_has_fpu(void)
322{
323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
324}
325
91dfc423
GR		 326static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
327{
328#ifdef __NEED_VMBITS_PROBE
5b7efa89 329 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 330 back_to_back_c0_hazard();
5b7efa89 331 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 332#endif
333}
334
a96102be
SH		 335static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
336{
337 switch (isa) {
338 case MIPS_CPU_ISA_M64R2:
339 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
340 case MIPS_CPU_ISA_M64R1:
341 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
342 case MIPS_CPU_ISA_V:
343 c->isa_level |= MIPS_CPU_ISA_V;
344 case MIPS_CPU_ISA_IV:
345 c->isa_level |= MIPS_CPU_ISA_IV;
346 case MIPS_CPU_ISA_III:
347 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
348 MIPS_CPU_ISA_III;
349 break;
350
351 case MIPS_CPU_ISA_M32R2:
352 c->isa_level |= MIPS_CPU_ISA_M32R2;
353 case MIPS_CPU_ISA_M32R1:
354 c->isa_level |= MIPS_CPU_ISA_M32R1;
355 case MIPS_CPU_ISA_II:
356 c->isa_level |= MIPS_CPU_ISA_II;
357 case MIPS_CPU_ISA_I:
358 c->isa_level |= MIPS_CPU_ISA_I;
359 break;
360 }
361}
362
2fa36399
KC		 363static char unknown_isa[] __cpuinitdata = KERN_ERR \
364 "Unsupported ISA type, c0.config0: %d.";
365
366static inline unsigned int decode_config0(struct cpuinfo_mips *c)
367{
368 unsigned int config0;
369 int isa;
370
371 config0 = read_c0_config();
372
373 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
374 c->options |= MIPS_CPU_TLB;
375 isa = (config0 & MIPS_CONF_AT) >> 13;
376 switch (isa) {
377 case 0:
378 switch ((config0 & MIPS_CONF_AR) >> 10) {
379 case 0:
a96102be 380 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 381 break;
382 case 1:
a96102be 383 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 384 break;
385 default:
386 goto unknown;
387 }
388 break;
389 case 2:
390 switch ((config0 & MIPS_CONF_AR) >> 10) {
391 case 0:
a96102be 392 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 393 break;
394 case 1:
a96102be 395 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 396 break;
397 default:
398 goto unknown;
399 }
400 break;
401 default:
402 goto unknown;
403 }
404
405 return config0 & MIPS_CONF_M;
406
407unknown:
408 panic(unknown_isa, config0);
409}
410
411static inline unsigned int decode_config1(struct cpuinfo_mips *c)
412{
413 unsigned int config1;
414
415 config1 = read_c0_config1();
416
417 if (config1 & MIPS_CONF1_MD)
418 c->ases |= MIPS_ASE_MDMX;
419 if (config1 & MIPS_CONF1_WR)
420 c->options |= MIPS_CPU_WATCH;
421 if (config1 & MIPS_CONF1_CA)
422 c->ases |= MIPS_ASE_MIPS16;
423 if (config1 & MIPS_CONF1_EP)
424 c->options |= MIPS_CPU_EJTAG;
425 if (config1 & MIPS_CONF1_FP) {
426 c->options |= MIPS_CPU_FPU;
427 c->options |= MIPS_CPU_32FPR;
428 }
429 if (cpu_has_tlb)
430 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
431
432 return config1 & MIPS_CONF_M;
433}
434
435static inline unsigned int decode_config2(struct cpuinfo_mips *c)
436{
437 unsigned int config2;
438
439 config2 = read_c0_config2();
440
441 if (config2 & MIPS_CONF2_SL)
442 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
443
444 return config2 & MIPS_CONF_M;
445}
446
447static inline unsigned int decode_config3(struct cpuinfo_mips *c)
448{
449 unsigned int config3;
450
451 config3 = read_c0_config3();
452
b2ab4f08 453 if (config3 & MIPS_CONF3_SM) {
2fa36399 454 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 455 c->options |= MIPS_CPU_RIXI;
456 }
457 if (config3 & MIPS_CONF3_RXI)
458 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 459 if (config3 & MIPS_CONF3_DSP)
460 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 461 if (config3 & MIPS_CONF3_DSP2P)
462 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 463 if (config3 & MIPS_CONF3_VINT)
464 c->options |= MIPS_CPU_VINT;
465 if (config3 & MIPS_CONF3_VEIC)
466 c->options |= MIPS_CPU_VEIC;
467 if (config3 & MIPS_CONF3_MT)
468 c->ases |= MIPS_ASE_MIPSMT;
469 if (config3 & MIPS_CONF3_ULRI)
470 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 471 if (config3 & MIPS_CONF3_ISA)
472 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 473 if (config3 & MIPS_CONF3_VZ)
474 c->ases |= MIPS_ASE_VZ;
2fa36399
KC		 475
476 return config3 & MIPS_CONF_M;
477}
478
479static inline unsigned int decode_config4(struct cpuinfo_mips *c)
480{
481 unsigned int config4;
482
483 config4 = read_c0_config4();
484
485 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
486 && cpu_has_tlb)
487 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
488
489 c->kscratch_mask = (config4 >> 16) & 0xff;
490
491 return config4 & MIPS_CONF_M;
492}
493
494static void __cpuinit decode_configs(struct cpuinfo_mips *c)
495{
496 int ok;
497
498 /* MIPS32 or MIPS64 compliant CPU. */
499 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
500 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
501
502 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
503
504 ok = decode_config0(c); /* Read Config registers. */
70342287 505 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 506 if (ok)
507 ok = decode_config1(c);
508 if (ok)
509 ok = decode_config2(c);
510 if (ok)
511 ok = decode_config3(c);
512 if (ok)
513 ok = decode_config4(c);
514
515 mips_probe_watch_registers(c);
516
517 if (cpu_has_mips_r2)
518 c->core = read_c0_ebase() & 0x3ff;
519}
520
02cf2119 521#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 522 | MIPS_CPU_COUNTER)
523
cea7e2df 524static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 525{
526 switch (c->processor_id & 0xff00) {
527 case PRID_IMP_R2000:
528 c->cputype = CPU_R2000;
cea7e2df 529 __cpu_name[cpu] = "R2000";
a96102be 530 set_isa(c, MIPS_CPU_ISA_I);
02cf2119 531 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 532 MIPS_CPU_NOFPUEX;
1da177e4
LT		 533 if (__cpu_has_fpu())
534 c->options |= MIPS_CPU_FPU;
535 c->tlbsize = 64;
536 break;
537 case PRID_IMP_R3000:
cea7e2df
RB		 538 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
539 if (cpu_has_confreg()) {
1da177e4 540 c->cputype = CPU_R3081E;
cea7e2df
RB		 541 __cpu_name[cpu] = "R3081";
542 } else {
1da177e4 543 c->cputype = CPU_R3000A;
cea7e2df
RB		 544 __cpu_name[cpu] = "R3000A";
545 }
cea7e2df 546 } else {
1da177e4 547 c->cputype = CPU_R3000;
cea7e2df
RB		 548 __cpu_name[cpu] = "R3000";
549 }
a96102be 550 set_isa(c, MIPS_CPU_ISA_I);
02cf2119 551 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 552 MIPS_CPU_NOFPUEX;
1da177e4
LT		 553 if (__cpu_has_fpu())
554 c->options |= MIPS_CPU_FPU;
555 c->tlbsize = 64;
556 break;
557 case PRID_IMP_R4000:
558 if (read_c0_config() & CONF_SC) {
cea7e2df 559 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 560 c->cputype = CPU_R4400PC;
cea7e2df
RB		 561 __cpu_name[cpu] = "R4400PC";
562 } else {
1da177e4 563 c->cputype = CPU_R4000PC;
cea7e2df
RB		 564 __cpu_name[cpu] = "R4000PC";
565 }
1da177e4 566 } else {
cea7e2df 567 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 568 c->cputype = CPU_R4400SC;
cea7e2df
RB		 569 __cpu_name[cpu] = "R4400SC";
570 } else {
1da177e4 571 c->cputype = CPU_R4000SC;
cea7e2df
RB		 572 __cpu_name[cpu] = "R4000SC";
573 }
1da177e4
LT		 574 }
575
a96102be 576 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 577 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 578 MIPS_CPU_WATCH | MIPS_CPU_VCE |
579 MIPS_CPU_LLSC;
1da177e4
LT		 580 c->tlbsize = 48;
581 break;
582 case PRID_IMP_VR41XX:
583 switch (c->processor_id & 0xf0) {
1da177e4
LT		 584 case PRID_REV_VR4111:
585 c->cputype = CPU_VR4111;
cea7e2df 586 __cpu_name[cpu] = "NEC VR4111";
1da177e4 587 break;
1da177e4
LT		 588 case PRID_REV_VR4121:
589 c->cputype = CPU_VR4121;
cea7e2df 590 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 591 break;
592 case PRID_REV_VR4122:
cea7e2df 593 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 594 c->cputype = CPU_VR4122;
cea7e2df
RB		 595 __cpu_name[cpu] = "NEC VR4122";
596 } else {
1da177e4 597 c->cputype = CPU_VR4181A;
cea7e2df
RB		 598 __cpu_name[cpu] = "NEC VR4181A";
599 }
1da177e4
LT		 600 break;
601 case PRID_REV_VR4130:
cea7e2df 602 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 603 c->cputype = CPU_VR4131;
cea7e2df
RB		 604 __cpu_name[cpu] = "NEC VR4131";
605 } else {
1da177e4 606 c->cputype = CPU_VR4133;
cea7e2df
RB		 607 __cpu_name[cpu] = "NEC VR4133";
608 }
1da177e4
LT		 609 break;
610 default:
611 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
612 c->cputype = CPU_VR41XX;
cea7e2df 613 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 614 break;
615 }
a96102be 616 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 617 c->options = R4K_OPTS;
618 c->tlbsize = 32;
619 break;
620 case PRID_IMP_R4300:
621 c->cputype = CPU_R4300;
cea7e2df 622 __cpu_name[cpu] = "R4300";
a96102be 623 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 624 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 625 MIPS_CPU_LLSC;
1da177e4
LT		 626 c->tlbsize = 32;
627 break;
628 case PRID_IMP_R4600:
629 c->cputype = CPU_R4600;
cea7e2df 630 __cpu_name[cpu] = "R4600";
a96102be 631 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 632 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
633 MIPS_CPU_LLSC;
1da177e4
LT		 634 c->tlbsize = 48;
635 break;
636 #if 0
03751e79 637 case PRID_IMP_R4650:
1da177e4
LT		 638 /*
639 * This processor doesn't have an MMU, so it's not
640 * "real easy" to run Linux on it. It is left purely
641 * for documentation. Commented out because it shares
642 * it's c0_prid id number with the TX3900.
643 */
a3dddd56 644 c->cputype = CPU_R4650;
cea7e2df 645 __cpu_name[cpu] = "R4650";
a96102be 646 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 648 c->tlbsize = 48;
1da177e4
LT		 649 break;
650 #endif
651 case PRID_IMP_TX39:
a96102be 652 set_isa(c, MIPS_CPU_ISA_I);
02cf2119 653 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 654
655 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
656 c->cputype = CPU_TX3927;
cea7e2df 657 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 658 c->tlbsize = 64;
659 } else {
660 switch (c->processor_id & 0xff) {
661 case PRID_REV_TX3912:
662 c->cputype = CPU_TX3912;
cea7e2df 663 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 664 c->tlbsize = 32;
665 break;
666 case PRID_REV_TX3922:
667 c->cputype = CPU_TX3922;
cea7e2df 668 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 669 c->tlbsize = 64;
670 break;
1da177e4
LT		 671 }
672 }
673 break;
674 case PRID_IMP_R4700:
675 c->cputype = CPU_R4700;
cea7e2df 676 __cpu_name[cpu] = "R4700";
a96102be 677 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 679 MIPS_CPU_LLSC;
1da177e4
LT		 680 c->tlbsize = 48;
681 break;
682 case PRID_IMP_TX49:
683 c->cputype = CPU_TX49XX;
cea7e2df 684 __cpu_name[cpu] = "R49XX";
a96102be 685 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 686 c->options = R4K_OPTS | MIPS_CPU_LLSC;
687 if (!(c->processor_id & 0x08))
688 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
689 c->tlbsize = 48;
690 break;
691 case PRID_IMP_R5000:
692 c->cputype = CPU_R5000;
cea7e2df 693 __cpu_name[cpu] = "R5000";
a96102be 694 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 695 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 696 MIPS_CPU_LLSC;
1da177e4
LT		 697 c->tlbsize = 48;
698 break;
699 case PRID_IMP_R5432:
700 c->cputype = CPU_R5432;
cea7e2df 701 __cpu_name[cpu] = "R5432";
a96102be 702 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 704 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 705 c->tlbsize = 48;
706 break;
707 case PRID_IMP_R5500:
708 c->cputype = CPU_R5500;
cea7e2df 709 __cpu_name[cpu] = "R5500";
a96102be 710 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 711 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 712 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 713 c->tlbsize = 48;
714 break;
715 case PRID_IMP_NEVADA:
716 c->cputype = CPU_NEVADA;
cea7e2df 717 __cpu_name[cpu] = "Nevada";
a96102be 718 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 719 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 720 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 721 c->tlbsize = 48;
722 break;
723 case PRID_IMP_R6000:
724 c->cputype = CPU_R6000;
cea7e2df 725 __cpu_name[cpu] = "R6000";
a96102be 726 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 727 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 728 MIPS_CPU_LLSC;
1da177e4
LT		 729 c->tlbsize = 32;
730 break;
731 case PRID_IMP_R6000A:
732 c->cputype = CPU_R6000A;
cea7e2df 733 __cpu_name[cpu] = "R6000A";
a96102be 734 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 735 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 736 MIPS_CPU_LLSC;
1da177e4
LT		 737 c->tlbsize = 32;
738 break;
739 case PRID_IMP_RM7000:
740 c->cputype = CPU_RM7000;
cea7e2df 741 __cpu_name[cpu] = "RM7000";
a96102be 742 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 743 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 744 MIPS_CPU_LLSC;
1da177e4 745 /*
70342287 746 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 747 * the RM7000 v2.0 indicates if the TLB has 48 or 64
748 * entries.
749 *
70342287
RB		 750 * 29 1 => 64 entry JTLB
751 * 0 => 48 entry JTLB
1da177e4
LT		 752 */
753 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
754 break;
755 case PRID_IMP_RM9000:
756 c->cputype = CPU_RM9000;
cea7e2df 757 __cpu_name[cpu] = "RM9000";
a96102be 758 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 759 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 760 MIPS_CPU_LLSC;
1da177e4
LT		 761 /*
762 * Bit 29 in the info register of the RM9000
763 * indicates if the TLB has 48 or 64 entries.
764 *
70342287
RB		 765 * 29 1 => 64 entry JTLB
766 * 0 => 48 entry JTLB
1da177e4
LT		 767 */
768 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
769 break;
770 case PRID_IMP_R8000:
771 c->cputype = CPU_R8000;
cea7e2df 772 __cpu_name[cpu] = "RM8000";
a96102be 773 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 774 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 775 MIPS_CPU_FPU | MIPS_CPU_32FPR |
776 MIPS_CPU_LLSC;
1da177e4
LT		 777 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
778 break;
779 case PRID_IMP_R10000:
780 c->cputype = CPU_R10000;
cea7e2df 781 __cpu_name[cpu] = "R10000";
a96102be 782 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 783 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 784 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 785 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 786 MIPS_CPU_LLSC;
1da177e4
LT		 787 c->tlbsize = 64;
788 break;
789 case PRID_IMP_R12000:
790 c->cputype = CPU_R12000;
cea7e2df 791 __cpu_name[cpu] = "R12000";
a96102be 792 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 793 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 794 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 795 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 796 MIPS_CPU_LLSC;
1da177e4
LT		 797 c->tlbsize = 64;
798 break;
44d921b2
K		 799 case PRID_IMP_R14000:
800 c->cputype = CPU_R14000;
cea7e2df 801 __cpu_name[cpu] = "R14000";
a96102be 802 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 803 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 804 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 805 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 806 MIPS_CPU_LLSC;
44d921b2
K		 807 c->tlbsize = 64;
808 break;
2a21c730
FZ		 809 case PRID_IMP_LOONGSON2:
810 c->cputype = CPU_LOONGSON2;
cea7e2df 811 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 812
813 switch (c->processor_id & PRID_REV_MASK) {
814 case PRID_REV_LOONGSON2E:
815 set_elf_platform(cpu, "loongson2e");
816 break;
817 case PRID_REV_LOONGSON2F:
818 set_elf_platform(cpu, "loongson2f");
819 break;
820 }
821
a96102be 822 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 823 c->options = R4K_OPTS |
824 MIPS_CPU_FPU | MIPS_CPU_LLSC |
825 MIPS_CPU_32FPR;
826 c->tlbsize = 64;
827 break;
2fa36399
KC		 828 case PRID_IMP_LOONGSON1:
829 decode_configs(c);
b4672d37 830
2fa36399 831 c->cputype = CPU_LOONGSON1;
1da177e4 832
2fa36399
KC		 833 switch (c->processor_id & PRID_REV_MASK) {
834 case PRID_REV_LOONGSON1B:
835 __cpu_name[cpu] = "Loongson 1B";
b4672d37 836 break;
b4672d37 837 }
4194318c 838
2fa36399 839 break;
1da177e4 840 }
1da177e4
LT		 841}
842
cea7e2df 843static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 844{
4194318c 845 decode_configs(c);
1da177e4
LT		 846 switch (c->processor_id & 0xff00) {
847 case PRID_IMP_4KC:
848 c->cputype = CPU_4KC;
cea7e2df 849 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 850 break;
851 case PRID_IMP_4KEC:
2b07bd02
RB		 852 case PRID_IMP_4KECR2:
853 c->cputype = CPU_4KEC;
cea7e2df 854 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 855 break;
1da177e4 856 case PRID_IMP_4KSC:
8afcb5d8 857 case PRID_IMP_4KSD:
1da177e4 858 c->cputype = CPU_4KSC;
cea7e2df 859 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 860 break;
861 case PRID_IMP_5KC:
862 c->cputype = CPU_5KC;
cea7e2df 863 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 864 break;
78d4803f
LY		 865 case PRID_IMP_5KE:
866 c->cputype = CPU_5KE;
867 __cpu_name[cpu] = "MIPS 5KE";
868 break;
1da177e4
LT		 869 case PRID_IMP_20KC:
870 c->cputype = CPU_20KC;
cea7e2df 871 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 872 break;
873 case PRID_IMP_24K:
874 c->cputype = CPU_24K;
cea7e2df 875 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 876 break;
42f3caef
JC		 877 case PRID_IMP_24KE:
878 c->cputype = CPU_24K;
879 __cpu_name[cpu] = "MIPS 24KEc";
880 break;
1da177e4
LT		 881 case PRID_IMP_25KF:
882 c->cputype = CPU_25KF;
cea7e2df 883 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 884 break;
bbc7f22f
RB		 885 case PRID_IMP_34K:
886 c->cputype = CPU_34K;
cea7e2df 887 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 888 break;
c620953c
CD		 889 case PRID_IMP_74K:
890 c->cputype = CPU_74K;
cea7e2df 891 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 892 break;
113c62d9
SH		 893 case PRID_IMP_M14KC:
894 c->cputype = CPU_M14KC;
895 __cpu_name[cpu] = "MIPS M14Kc";
896 break;
f8fa4811
SH		 897 case PRID_IMP_M14KEC:
898 c->cputype = CPU_M14KEC;
899 __cpu_name[cpu] = "MIPS M14KEc";
900 break;
39b8d525
RB		 901 case PRID_IMP_1004K:
902 c->cputype = CPU_1004K;
cea7e2df 903 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 904 break;
006a851b
SH		 905 case PRID_IMP_1074K:
906 c->cputype = CPU_74K;
907 __cpu_name[cpu] = "MIPS 1074Kc";
908 break;
1da177e4 909 }
0b6d497f
CD		 910
911 spram_config();
1da177e4
LT		 912}
913
cea7e2df 914static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 915{
4194318c 916 decode_configs(c);
1da177e4
LT		 917 switch (c->processor_id & 0xff00) {
918 case PRID_IMP_AU1_REV1:
919 case PRID_IMP_AU1_REV2:
270717a8 920 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 921 switch ((c->processor_id >> 24) & 0xff) {
922 case 0:
cea7e2df 923 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 924 break;
925 case 1:
cea7e2df 926 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 927 break;
928 case 2:
cea7e2df 929 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 930 break;
931 case 3:
cea7e2df 932 __cpu_name[cpu] = "Au1550";
1da177e4 933 break;
e3ad1c23 934 case 4:
cea7e2df 935 __cpu_name[cpu] = "Au1200";
270717a8 936 if ((c->processor_id & 0xff) == 2)
cea7e2df 937 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 938 break;
939 case 5:
cea7e2df 940 __cpu_name[cpu] = "Au1210";
e3ad1c23 941 break;
1da177e4 942 default:
270717a8 943 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 944 break;
945 }
1da177e4
LT		 946 break;
947 }
948}
949
cea7e2df 950static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 951{
4194318c 952 decode_configs(c);
02cf2119 953
1da177e4
LT		 954 switch (c->processor_id & 0xff00) {
955 case PRID_IMP_SB1:
956 c->cputype = CPU_SB1;
cea7e2df 957 __cpu_name[cpu] = "SiByte SB1";
1da177e4 958 /* FPU in pass1 is known to have issues. */
aa32374a 959 if ((c->processor_id & 0xff) < 0x02)
010b853b 960 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 961 break;
93ce2f52
AI		 962 case PRID_IMP_SB1A:
963 c->cputype = CPU_SB1A;
cea7e2df 964 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 965 break;
1da177e4
LT		 966 }
967}
968
cea7e2df 969static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 970{
4194318c 971 decode_configs(c);
1da177e4
LT		 972 switch (c->processor_id & 0xff00) {
973 case PRID_IMP_SR71000:
974 c->cputype = CPU_SR71000;
cea7e2df 975 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 976 c->scache.ways = 8;
977 c->tlbsize = 64;
978 break;
979 }
980}
981
cea7e2df 982static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 983{
984 decode_configs(c);
985 switch (c->processor_id & 0xff00) {
986 case PRID_IMP_PR4450:
987 c->cputype = CPU_PR4450;
cea7e2df 988 __cpu_name[cpu] = "Philips PR4450";
a96102be 989 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 990 break;
bdf21b18
PP		 991 }
992}
993
cea7e2df 994static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 995{
996 decode_configs(c);
997 switch (c->processor_id & 0xff00) {
190fca3e
KC		 998 case PRID_IMP_BMIPS32_REV4:
999 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1000 c->cputype = CPU_BMIPS32;
1001 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1002 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1003 break;
1004 case PRID_IMP_BMIPS3300:
1005 case PRID_IMP_BMIPS3300_ALT:
1006 case PRID_IMP_BMIPS3300_BUG:
1007 c->cputype = CPU_BMIPS3300;
1008 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1009 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1010 break;
1011 case PRID_IMP_BMIPS43XX: {
1012 int rev = c->processor_id & 0xff;
1013
1014 if (rev >= PRID_REV_BMIPS4380_LO &&
1015 rev <= PRID_REV_BMIPS4380_HI) {
1016 c->cputype = CPU_BMIPS4380;
1017 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1018 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1019 } else {
1020 c->cputype = CPU_BMIPS4350;
1021 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1022 set_elf_platform(cpu, "bmips4350");
602977b0 1023 }
0de663ef 1024 break;
602977b0
KC		 1025 }
1026 case PRID_IMP_BMIPS5000:
1027 c->cputype = CPU_BMIPS5000;
1028 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1029 set_elf_platform(cpu, "bmips5000");
602977b0 1030 c->options |= MIPS_CPU_ULRI;
0de663ef 1031 break;
1c0c13eb
AJ		 1032 }
1033}
1034
0dd4781b
DD		 1035static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1036{
1037 decode_configs(c);
1038 switch (c->processor_id & 0xff00) {
1039 case PRID_IMP_CAVIUM_CN38XX:
1040 case PRID_IMP_CAVIUM_CN31XX:
1041 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1042 c->cputype = CPU_CAVIUM_OCTEON;
1043 __cpu_name[cpu] = "Cavium Octeon";
1044 goto platform;
0dd4781b
DD		 1045 case PRID_IMP_CAVIUM_CN58XX:
1046 case PRID_IMP_CAVIUM_CN56XX:
1047 case PRID_IMP_CAVIUM_CN50XX:
1048 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1049 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1050 __cpu_name[cpu] = "Cavium Octeon+";
1051platform:
c094c99e 1052 set_elf_platform(cpu, "octeon");
0dd4781b 1053 break;
a1431b61 1054 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1055 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1056 case PRID_IMP_CAVIUM_CN66XX:
1057 case PRID_IMP_CAVIUM_CN68XX:
0e56b385
DD		 1058 c->cputype = CPU_CAVIUM_OCTEON2;
1059 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1060 set_elf_platform(cpu, "octeon2");
0e56b385 1061 break;
0dd4781b
DD		 1062 default:
1063 printk(KERN_INFO "Unknown Octeon chip!\n");
1064 c->cputype = CPU_UNKNOWN;
1065 break;
1066 }
1067}
1068
83ccf69d
LPC		 1069static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1070{
1071 decode_configs(c);
1072 /* JZRISC does not implement the CP0 counter. */
1073 c->options &= ~MIPS_CPU_COUNTER;
1074 switch (c->processor_id & 0xff00) {
1075 case PRID_IMP_JZRISC:
1076 c->cputype = CPU_JZRISC;
1077 __cpu_name[cpu] = "Ingenic JZRISC";
1078 break;
1079 default:
1080 panic("Unknown Ingenic Processor ID!");
1081 break;
1082 }
1083}
1084
a7117c6b
J		 1085static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1086{
1087 decode_configs(c);
1088
809f36c6
ML		 1089 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1090 c->cputype = CPU_ALCHEMY;
1091 __cpu_name[cpu] = "Au1300";
1092 /* following stuff is not for Alchemy */
1093 return;
1094 }
1095
70342287
RB		 1096 c->options = (MIPS_CPU_TLB |
1097 MIPS_CPU_4KEX |
a7117c6b 1098 MIPS_CPU_COUNTER |
70342287
RB		 1099 MIPS_CPU_DIVEC |
1100 MIPS_CPU_WATCH |
1101 MIPS_CPU_EJTAG |
a7117c6b
J		 1102 MIPS_CPU_LLSC);
1103
1104 switch (c->processor_id & 0xff00) {
2aa54b20
J		 1105 case PRID_IMP_NETLOGIC_XLP8XX:
1106 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1107 c->cputype = CPU_XLP;
1108 __cpu_name[cpu] = "Netlogic XLP";
1109 break;
1110
a7117c6b
J		 1111 case PRID_IMP_NETLOGIC_XLR732:
1112 case PRID_IMP_NETLOGIC_XLR716:
1113 case PRID_IMP_NETLOGIC_XLR532:
1114 case PRID_IMP_NETLOGIC_XLR308:
1115 case PRID_IMP_NETLOGIC_XLR532C:
1116 case PRID_IMP_NETLOGIC_XLR516C:
1117 case PRID_IMP_NETLOGIC_XLR508C:
1118 case PRID_IMP_NETLOGIC_XLR308C:
1119 c->cputype = CPU_XLR;
1120 __cpu_name[cpu] = "Netlogic XLR";
1121 break;
1122
1123 case PRID_IMP_NETLOGIC_XLS608:
1124 case PRID_IMP_NETLOGIC_XLS408:
1125 case PRID_IMP_NETLOGIC_XLS404:
1126 case PRID_IMP_NETLOGIC_XLS208:
1127 case PRID_IMP_NETLOGIC_XLS204:
1128 case PRID_IMP_NETLOGIC_XLS108:
1129 case PRID_IMP_NETLOGIC_XLS104:
1130 case PRID_IMP_NETLOGIC_XLS616B:
1131 case PRID_IMP_NETLOGIC_XLS608B:
1132 case PRID_IMP_NETLOGIC_XLS416B:
1133 case PRID_IMP_NETLOGIC_XLS412B:
1134 case PRID_IMP_NETLOGIC_XLS408B:
1135 case PRID_IMP_NETLOGIC_XLS404B:
1136 c->cputype = CPU_XLR;
1137 __cpu_name[cpu] = "Netlogic XLS";
1138 break;
1139
1140 default:
a3d4fb2d 1141 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1142 c->processor_id);
1143 c->cputype = CPU_XLR;
1144 break;
1145 }
1146
a3d4fb2d 1147 if (c->cputype == CPU_XLP) {
a96102be 1148 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1149 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1150 /* This will be updated again after all threads are woken up */
1151 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1152 } else {
a96102be 1153 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1154 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1155 }
a7117c6b
J		 1156}
1157
949e51be
DD		 1158#ifdef CONFIG_64BIT
1159/* For use by uaccess.h */
1160u64 __ua_limit;
1161EXPORT_SYMBOL(__ua_limit);
1162#endif
1163
9966db25 1164const char *__cpu_name[NR_CPUS];
874fd3b5 1165const char *__elf_platform;
9966db25 1166
234fcd14 1167__cpuinit void cpu_probe(void)
1da177e4
LT		 1168{
1169 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1170 unsigned int cpu = smp_processor_id();
1da177e4 1171
70342287 1172 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1173 c->fpu_id = FPIR_IMP_NONE;
1174 c->cputype = CPU_UNKNOWN;
1175
1176 c->processor_id = read_c0_prid();
1177 switch (c->processor_id & 0xff0000) {
1178 case PRID_COMP_LEGACY:
cea7e2df 1179 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1180 break;
1181 case PRID_COMP_MIPS:
cea7e2df 1182 cpu_probe_mips(c, cpu);
1da177e4
LT		 1183 break;
1184 case PRID_COMP_ALCHEMY:
cea7e2df 1185 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1186 break;
1187 case PRID_COMP_SIBYTE:
cea7e2df 1188 cpu_probe_sibyte(c, cpu);
1da177e4 1189 break;
1c0c13eb 1190 case PRID_COMP_BROADCOM:
cea7e2df 1191 cpu_probe_broadcom(c, cpu);
1c0c13eb 1192 break;
1da177e4 1193 case PRID_COMP_SANDCRAFT:
cea7e2df 1194 cpu_probe_sandcraft(c, cpu);
1da177e4 1195 break;
a92b0588 1196 case PRID_COMP_NXP:
cea7e2df 1197 cpu_probe_nxp(c, cpu);
a3dddd56 1198 break;
0dd4781b
DD		 1199 case PRID_COMP_CAVIUM:
1200 cpu_probe_cavium(c, cpu);
1201 break;
83ccf69d
LPC		 1202 case PRID_COMP_INGENIC:
1203 cpu_probe_ingenic(c, cpu);
1204 break;
a7117c6b
J		 1205 case PRID_COMP_NETLOGIC:
1206 cpu_probe_netlogic(c, cpu);
1207 break;
1da177e4 1208 }
dec8b1ca 1209
cea7e2df
RB		 1210 BUG_ON(!__cpu_name[cpu]);
1211 BUG_ON(c->cputype == CPU_UNKNOWN);
1212
dec8b1ca
FBH		 1213 /*
1214 * Platform code can force the cpu type to optimize code
1215 * generation. In that case be sure the cpu type is correctly
1216 * manually setup otherwise it could trigger some nasty bugs.
1217 */
1218 BUG_ON(current_cpu_type() != c->cputype);
1219
0103d23f
KC		 1220 if (mips_fpu_disabled)
1221 c->options &= ~MIPS_CPU_FPU;
1222
1223 if (mips_dsp_disabled)
ee80f7c7 1224 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1225
4194318c 1226 if (c->options & MIPS_CPU_FPU) {
1da177e4 1227 c->fpu_id = cpu_get_fpu_id();
4194318c 1228
e7958bb9 1229 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 1230 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1231 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1232 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 1233 if (c->fpu_id & MIPS_FPIR_3D)
1234 c->ases |= MIPS_ASE_MIPS3D;
1235 }
1236 }
9966db25 1237
da4b62cd 1238 if (cpu_has_mips_r2) {
f6771dbb 1239 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1240 /* R2 has Performance Counter Interrupt indicator */
1241 c->options |= MIPS_CPU_PCI;
1242 }
f6771dbb
RB		 1243 else
1244 c->srsets = 1;
91dfc423
GR		 1245
1246 cpu_probe_vmbits(c);
949e51be
DD		 1247
1248#ifdef CONFIG_64BIT
1249 if (cpu == 0)
1250 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1251#endif
1da177e4
LT		 1252}
1253
234fcd14 1254__cpuinit void cpu_report(void)
1da177e4
LT		 1255{
1256 struct cpuinfo_mips *c = &current_cpu_data;
1257
9966db25
RB		 1258 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1259 c->processor_id, cpu_name_string());
1da177e4 1260 if (c->options & MIPS_CPU_FPU)
9966db25 1261 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1262}
Linux kernel - Deliverables
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