[deliverable/linux.git] / arch / mips / kernel / i8259.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994 - 2000 Ralf Baechle
 */
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>

#include <asm/i8259.h>
#include <asm/io.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

static int i8259A_auto_eoi = -1;
DEFINE_RAW_SPINLOCK(i8259A_lock);
static void disable_8259A_irq(struct irq_data *d);
static void enable_8259A_irq(struct irq_data *d);
static void mask_and_ack_8259A(struct irq_data *d);
static void init_8259A(int auto_eoi);

static struct irq_chip i8259A_chip = {
	.name			= "XT-PIC",
	.irq_mask		= disable_8259A_irq,
	.irq_disable		= disable_8259A_irq,
	.irq_unmask		= enable_8259A_irq,
	.irq_mask_ack		= mask_and_ack_8259A,
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
	.irq_set_affinity	= plat_set_irq_affinity,
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
static unsigned int cached_irq_mask = 0xffff;

#define cached_master_mask	(cached_irq_mask)
#define cached_slave_mask	(cached_irq_mask >> 8)

static void disable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = ~(1 << irq);
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask;
	unsigned long flags;
	int ret;

	irq -= I8259A_IRQ_BASE;
	mask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1 << irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *d)
{
	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	irqmask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	smtc_im_ack_irq(irq);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static void i8259A_resume(void)
{
	if (i8259A_auto_eoi >= 0)
		init_8259A(i8259A_auto_eoi);
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	if (i8259A_auto_eoi >= 0) {
		outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
		outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
	}
}

static struct syscore_ops i8259_syscore_ops = {
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static int __init i8259A_init_sysfs(void)
{
	register_syscore_ops(&i8259_syscore_ops);
	return 0;
}

device_initcall(i8259A_init_sysfs);

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_p - this has to work on a wide range of PC hardware.
	 */
	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
};

static struct resource pic1_io_resource = {
	.name = "pic1",
	.start = PIC_MASTER_CMD,
	.end = PIC_MASTER_IMR,
	.flags = IORESOURCE_BUSY
};

static struct resource pic2_io_resource = {
	.name = "pic2",
	.start = PIC_SLAVE_CMD,
	.end = PIC_SLAVE_IMR,
	.flags = IORESOURCE_BUSY
};

/*
 * On systems with i8259-style interrupt controllers we assume for
 * driver compatibility reasons interrupts 0 - 15 to be the i8259
 * interrupts even if the hardware uses a different interrupt numbering.
 */
void __init init_i8259_irqs(void)
{
	int i;

	insert_resource(&ioport_resource, &pic1_io_resource);
	insert_resource(&ioport_resource, &pic2_io_resource);

	init_8259A(0);

	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
		irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
		irq_set_probe(i);
	}

	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	7	*
	8	* Copyright (C) 1992 Linus Torvalds
	9	* Copyright (C) 1994 - 2000 Ralf Baechle
	10	*/
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/kernel.h>
	16	#include <linux/spinlock.h>
84652e83	17	#include <linux/syscore_ops.h>
ca4d3e67	18	#include <linux/irq.h>
1da177e4 LT	19
	20	#include <asm/i8259.h>
	21	#include <asm/io.h>
	22
1da177e4 LT	23	/*
	24	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	25	* present in the majority of PC/AT boxes.
	26	* plus some generic x86 specific things if generic specifics makes
	27	* any sense at all.
	28	* this file should become arch/i386/kernel/irq.c when the old irq.c
	29	* moves to arch independent land
	30	*/
	31
a0be2f79	32	static int i8259A_auto_eoi = -1;
89650870	33	DEFINE_RAW_SPINLOCK(i8259A_lock);
7c8d948f TG	34	static void disable_8259A_irq(struct irq_data *d);
	35	static void enable_8259A_irq(struct irq_data *d);
	36	static void mask_and_ack_8259A(struct irq_data *d);
d80c1c0b	37	static void init_8259A(int auto_eoi);
1da177e4	38
2cafe978	39	static struct irq_chip i8259A_chip = {
7c8d948f TG	40	.name = "XT-PIC",
	41	.irq_mask = disable_8259A_irq,
	42	.irq_disable = disable_8259A_irq,
	43	.irq_unmask = enable_8259A_irq,
	44	.irq_mask_ack = mask_and_ack_8259A,
f571eff0	45	#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
7c8d948f	46	.irq_set_affinity = plat_set_irq_affinity,
f571eff0	47	#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
1da177e4 LT	48	};
	49
	50	/*
	51	* 8259A PIC functions to handle ISA devices:
	52	*/
	53
	54	/*
	55	* This contains the irq mask for both 8259A irq controllers,
	56	*/
	57	static unsigned int cached_irq_mask = 0xffff;
	58
2cafe978 AN	59	#define cached_master_mask (cached_irq_mask)
2cafe978 AN	60	#define cached_slave_mask (cached_irq_mask >> 8)
1da177e4	61
7c8d948f	62	static void disable_8259A_irq(struct irq_data *d)
1da177e4	63	{
7c8d948f	64	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	65	unsigned long flags;
1da177e4 LT	66
2fa7937b	67	mask = 1 << irq;
89650870	68	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	69	cached_irq_mask \|= mask;
1da177e4 LT	70	if (irq & 8)
2cafe978	71	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	72	else
2cafe978	73	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	74	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	75	}
1da177e4 LT	76
7c8d948f	77	static void enable_8259A_irq(struct irq_data *d)
1da177e4	78	{
7c8d948f	79	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	80	unsigned long flags;
1da177e4 LT	81
2fa7937b	82	mask = ~(1 << irq);
89650870	83	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	84	cached_irq_mask &= mask;
1da177e4 LT	85	if (irq & 8)
2cafe978	86	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	87	else
2cafe978	88	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	89	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	90	}
	91
	92	int i8259A_irq_pending(unsigned int irq)
	93	{
2fa7937b	94	unsigned int mask;
1da177e4 LT	95	unsigned long flags;
	96	int ret;
	97
2fa7937b AN	98	irq -= I8259A_IRQ_BASE;
2fa7937b AN	99	mask = 1 << irq;
89650870	100	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	101	if (irq < 8)
2cafe978	102	ret = inb(PIC_MASTER_CMD) & mask;
1da177e4	103	else
2cafe978	104	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
89650870	105	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	106
	107	return ret;
	108	}
	109
	110	void make_8259A_irq(unsigned int irq)
	111	{
	112	disable_irq_nosync(irq);
e4ec7989	113	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
1da177e4 LT	114	enable_irq(irq);
	115	}
	116
	117	/*
	118	* This function assumes to be called rarely. Switching between
	119	* 8259A registers is slow.
	120	* This has to be protected by the irq controller spinlock
	121	* before being called.
	122	*/
	123	static inline int i8259A_irq_real(unsigned int irq)
	124	{
	125	int value;
	126	int irqmask = 1 << irq;
	127
	128	if (irq < 8) {
21a151d8	129	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
2cafe978	130	value = inb(PIC_MASTER_CMD) & irqmask;
21a151d8	131	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
1da177e4 LT	132	return value;
1da177e4 LT	133	}
21a151d8	134	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
2cafe978	135	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
21a151d8	136	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
1da177e4 LT	137	return value;
	138	}
	139
	140	/*
	141	* Careful! The 8259A is a fragile beast, it pretty
	142	* much _has_ to be done exactly like this (mask it
	143	* first, _then_ send the EOI, and the order of EOI
	144	* to the two 8259s is important!
	145	*/
7c8d948f	146	static void mask_and_ack_8259A(struct irq_data *d)
1da177e4	147	{
7c8d948f	148	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	149	unsigned long flags;
1da177e4 LT	150
2fa7937b	151	irqmask = 1 << irq;
89650870	152	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	153	/*
2cafe978 AN	154	* Lightweight spurious IRQ detection. We do not want
	155	* to overdo spurious IRQ handling - it's usually a sign
	156	* of hardware problems, so we only do the checks we can
	157	* do without slowing down good hardware unnecessarily.
1da177e4	158	*
2cafe978 AN	159	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	160	* usually resulting from the 8259A-1\|2 PICs) occur
	161	* even if the IRQ is masked in the 8259A. Thus we
	162	* can check spurious 8259A IRQs without doing the
	163	* quite slow i8259A_irq_real() call for every IRQ.
	164	* This does not cover 100% of spurious interrupts,
	165	* but should be enough to warn the user that there
	166	* is something bad going on ...
1da177e4 LT	167	*/
	168	if (cached_irq_mask & irqmask)
	169	goto spurious_8259A_irq;
	170	cached_irq_mask \|= irqmask;
	171
	172	handle_real_irq:
	173	if (irq & 8) {
2cafe978 AN	174	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	175	outb(cached_slave_mask, PIC_SLAVE_IMR);
21a151d8 RB	176	outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
21a151d8 RB	177	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
1da177e4	178	} else {
2cafe978 AN	179	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	180	outb(cached_master_mask, PIC_MASTER_IMR);
21a151d8	181	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
1da177e4	182	}
1146fe30	183	smtc_im_ack_irq(irq);
89650870	184	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	185	return;
	186
	187	spurious_8259A_irq:
	188	/*
	189	* this is the slow path - should happen rarely.
	190	*/
	191	if (i8259A_irq_real(irq))
	192	/*
	193	* oops, the IRQ _is_ in service according to the
	194	* 8259A - not spurious, go handle it.
	195	*/
	196	goto handle_real_irq;
	197
	198	{
2cafe978	199	static int spurious_irq_mask;
1da177e4 LT	200	/*
	201	* At this point we can be sure the IRQ is spurious,
	202	* lets ACK and report it. [once per IRQ]
	203	*/
	204	if (!(spurious_irq_mask & irqmask)) {
	205	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	206	spurious_irq_mask \|= irqmask;
	207	}
	208	atomic_inc(&irq_err_count);
	209	/*
	210	* Theoretically we do not have to handle this IRQ,
	211	* but in Linux this does not cause problems and is
	212	* simpler for us.
	213	*/
	214	goto handle_real_irq;
	215	}
	216	}
	217
84652e83	218	static void i8259A_resume(void)
1da177e4	219	{
a0be2f79 AN	220	if (i8259A_auto_eoi >= 0)
a0be2f79 AN	221	init_8259A(i8259A_auto_eoi);
2cafe978 AN	222	}
2cafe978 AN	223
84652e83	224	static void i8259A_shutdown(void)
2cafe978 AN	225	{
	226	/* Put the i8259A into a quiescent state that
	227	* the kernel initialization code can get it
	228	* out of.
	229	*/
a0be2f79 AN	230	if (i8259A_auto_eoi >= 0) {
a0be2f79 AN	231	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
fe0b030c	232	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
a0be2f79	233	}
1da177e4 LT	234	}
1da177e4 LT	235
84652e83	236	static struct syscore_ops i8259_syscore_ops = {
1da177e4	237	.resume = i8259A_resume,
2cafe978	238	.shutdown = i8259A_shutdown,
1da177e4 LT	239	};
1da177e4 LT	240
1da177e4 LT	241	static int __init i8259A_init_sysfs(void)
1da177e4 LT	242	{
84652e83 RW	243	register_syscore_ops(&i8259_syscore_ops);
84652e83 RW	244	return 0;
1da177e4 LT	245	}
	246
	247	device_initcall(i8259A_init_sysfs);
	248
d80c1c0b	249	static void init_8259A(int auto_eoi)
1da177e4 LT	250	{
	251	unsigned long flags;
	252
2cafe978 AN	253	i8259A_auto_eoi = auto_eoi;
2cafe978 AN	254
89650870	255	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	256
2cafe978 AN	257	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
2cafe978 AN	258	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
1da177e4 LT	259
	260	/*
	261	* outb_p - this has to work on a wide range of PC hardware.
	262	*/
2cafe978 AN	263	outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	264	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	265	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
	266	if (auto_eoi) /* master does Auto EOI */
	267	outb_p(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	268	else /* master expects normal EOI */
	269	outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	270
	271	outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	272	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	273	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	274	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
1da177e4 LT	275	if (auto_eoi)
1da177e4 LT	276	/*
2cafe978	277	* In AEOI mode we just have to mask the interrupt
1da177e4 LT	278	* when acking.
1da177e4 LT	279	*/
7c8d948f	280	i8259A_chip.irq_mask_ack = disable_8259A_irq;
1da177e4	281	else
7c8d948f	282	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
1da177e4 LT	283
	284	udelay(100); /* wait for 8259A to initialize */
	285
2cafe978 AN	286	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
2cafe978 AN	287	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
1da177e4	288
89650870	289	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	290	}
	291
	292	/*
	293	* IRQ2 is cascade interrupt to second interrupt controller
	294	*/
	295	static struct irqaction irq2 = {
4e45171c	296	.handler = no_action,
4e45171c	297	.name = "cascade",
1da177e4 LT	298	};
	299
	300	static struct resource pic1_io_resource = {
2cafe978 AN	301	.name = "pic1",
	302	.start = PIC_MASTER_CMD,
	303	.end = PIC_MASTER_IMR,
	304	.flags = IORESOURCE_BUSY
1da177e4 LT	305	};
	306
	307	static struct resource pic2_io_resource = {
2cafe978 AN	308	.name = "pic2",
	309	.start = PIC_SLAVE_CMD,
	310	.end = PIC_SLAVE_IMR,
	311	.flags = IORESOURCE_BUSY
1da177e4 LT	312	};
	313
	314	/*
	315	* On systems with i8259-style interrupt controllers we assume for
28a7879d	316	* driver compatibility reasons interrupts 0 - 15 to be the i8259
1da177e4 LT	317	* interrupts even if the hardware uses a different interrupt numbering.
1da177e4 LT	318	*/
49a89efb	319	void __init init_i8259_irqs(void)
1da177e4 LT	320	{
	321	int i;
	322
639702bd TB	323	insert_resource(&ioport_resource, &pic1_io_resource);
639702bd TB	324	insert_resource(&ioport_resource, &pic2_io_resource);
1da177e4 LT	325
	326	init_8259A(0);
	327
24649c00	328	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
e4ec7989 TG	329	irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
e4ec7989 TG	330	irq_set_probe(i);
24649c00	331	}
1da177e4	332
2fa7937b	333	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
1da177e4	334	}